JPS60107699A - Musical scale converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The industrial field of application is a pitch conversion device that outputs a different pitch in response to the pitch of a human input signal, and is used in records, broadcasting,
Special effects equipment or two of different pitches in the film industry
It is used as a sound source correction device and as an accompaniment pitch conversion device in a mixing device or the like.

Structure of a conventional example and its problems FIG. 1 shows a block diagram of a conventional pitch converter.

In FIG. 1, 1 and 2 are gate means connected to the input terminal 3, and 4 and 5 are shift registers whose one end is connected to the gate means 1 and 2 and the other end is connected to other gate means 6 and 7, respectively. , 8 is an output terminal connected to the gate means 6.7, and 9 is an input/output clock f of the shift registers 4, 6. and a clock generator that generates a clear clock fv; 9;
10 are clocks f0 and fv and gate means 1.2.
11 is a controller that adjusts the control signal generator 1o.

The operation of the conventional example configured as described above will be described below. The original J31I of this conventional example of transformation
! is the read clock fv of the hidden signal with respect to the write clock f0 of the input signal of the shift registers 4 and 6.
It changes the The reason why two shift registers 4 and 5 are used in this conventional example is that it is impossible to write signals during the time when the shift registers are continuously outputting written signals. This is because the means 1.2, 6.7 and the two shift registers 4, 5 eliminate any signal input stop period.

Input/output waveform diagrams output to the output terminal 8 of this conventional example are shown in FIGS. 2 and 3.

Figure 2 shows a case where the signals (a1 to aS) of one wavelength of the input signal A input during the write time T0 determined by the product of the clock frequency f0 and the number of stages of soft registers are the same. , the input signal A1 input at the write clock f0 is outputted from the output signal B1 at the read clock fv.
The case is shown in which the read clock fw is read at twice the write clock f0, and the read clock fw and the write clock f0 have the following relationship.

fv−2×f.

That is, time t. -11 of the input written in A1
The wavelength portion (signals 81 to as) is read out as one wavelength portion (signals a'1 to a'6) of the output signal B1 at times t1 to t2.

However, in this case, since the read clock fv is larger than the write clock f0, there is no signal at all in the interval T1.
The first drawback is that 41.

Next, FIG. 3 shows a case where the write time T0 is not the same as one wavelength of the input signal A2 (signals b1 to b5), and the write clock f0 and read clock f4 are not integral multiples. The conditions are more generalized than in Figure 2. That is, time t. Signals b1 to b4, which are a portion of one wavelength (signals b1 to b5) of the input signal A2 written to 9.-11, are output from time t1 to t3. B2 signals b4 to b- are read out. Similarly, the signals b4 to b7 written from time 11 to t2 are also output from time t2 to t4.
-1, I is displayed one after another.

However, in this case, no signal is generated in the interval T2 from time t2 to t3 and the interval T2 from time t4 to t5, resulting in the second drawback that the output signal becomes discontinuous in such an interval.

FIG. 4 shows another conventional embodiment of the read clock fLL,
is an input/output waveform diagram when , is set to 16 times the write clock f0.

In Figure 4, memory capacity and write clock 4 plus M
shows a case in which data stored in the memory is sequentially read out and supplemented using a plurality of bits, for example, an 8-bit analog-to-digital converter, in an interval T3 in which there is no signal at all in the memory capacity. In this case, the signals C''1 to C'c1 to C'c and the heater are supplemented for the interval T3 where there is no signal at times t2 to t6 and from t7 to t8, but at times t6 and t7 A discontinuous phenomenon occurs in the signal, and when this signal is reproduced, noise will occur.The reason for this is that the signal is expressed by multiple bits, so most of the values at any given time are either two values or exactly the same value. This is considered to be because the probability that it is a near-difference value is very low. Therefore, in order to supplement the discontinuous interval, in a configuration equipped with a multi-bit analog-to-digital converter and a circular memory, It is necessary to use complicated signal processing technology using a microcomputer or the like to calculate the optimal connection point and then perform the connection, which has the drawback of not being able to reduce costs and save space.

This method was created in view of the drawbacks mentioned in 1. It compensates for discontinuous parts of the output signal, improves naturalness, and compares the pitch of the output signal with the pitch of the input signal. The object of the present invention is to provide a pitch conversion device that can arbitrarily change the pitch.

Release lX! I] Configuration In order to achieve the above object, the pitch converter of the present invention includes a 1-bit analog-to-digital converter, a 1-bit digital-to-analog converter, two digital memories, and an operation of the digital memory. means for generating a signal for selecting either writing or reading from each other; means for increasing the write address of the digital memory by 1 bit; and means for increasing the read address of the memory by 1 bit; A configuration comprising: a clock generation means with a fixed frequency of a digital converter; a clock generation means with a variable frequency of the analog converter; and an adjustment means for adjusting the clock generation means with a variable frequency. It has become.

With this configuration, the pitch of the input signal can be naturally converted by a signal having a pitch different from that pitch.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 is a block diagram of a pitch y conversion device according to an embodiment of Kibatsu J. In FIG. 5, 12 is an analog-to-digital converter that converts the signal input to the input terminal 3 into a 1-bit digital signal S6, and a signal S51' obtained by dividing the digital signal s6 into two by means of 13.14ij2 branching means.
The memory input to S52 usually uses a digital memory called RAM (Random Access Memory), and this memory 13.14 is limited to a 6-bit memory that can use memory addresses in a circular manner, and is not suitable for a shift register. . Reference numeral 15 denotes a write enable signal generator that causes the memory 13.14 to perform read or write operations depending on the voltage levels of its output signals S61 and S62.
1 Color level, (ilIlf” When S62 is at high level, the memory 13 is in a write operation, and the memory 14 is in a read operation.The timing of switching between the low and high levels of the signal S61 and signal S62 is determined by the memory bit capacity of the memory 13 and 14. In other words, the entire memory bit capacity (for example, 65536 bits) of the memory 13 is sequentially written by the write clock f0 (for example, 250
song) button for writing operation (i.e. 1/25
0KX65536 seconds), the memory 14 is the bladder output clock of the read clock generator 17. (For example, 376 songs)
so that the read operation is in progress.

The input signal s-,1 of the fixed write clock generator 16 uses the fixed write master clock generator 18 whose frequency is fixed and the output signal S7 of the counter 19 as an input signal. On the other hand, the input signal S of the bladder release clock generator 17, the output signal S8 of the variable release master clock generator 21 whose frequency can be varied by the controller 20 and the counter 22 are used as input signals.

23 and 24 are memory control signal generators that generate row address strobes and column address strobes among the signals that control the memory, and the memory control signal generator 23 for writing uses the output signal S7 of the counter 19 as an input signal. On the other hand, the read memory control signal generator 24 uses the output signal S8 of the counter 22 as an input signal. The output signals S9°S1o of the memory control signal generators 23 and 24 are selected by the data selector 26 in synchronization with the timing of whether the operation of the memory 13 and the memory 14 is writing or reading.

This timing is synchronized with the timing of the low level and high level of the output signal Sr 362 of the write enable signal generator 16.

The digital signal S11 read from the memory 13 or the memory 14 is converted into an analog signal S12 by a 1-bit digital-to-analog converter 26 and sent to the output terminal 8.
is output to. 271'j counter 19 output signal S7
A write address counter counts the address to be written using the input signal as an input signal, and specifies the write address to the memo 1)-13 and 14 via the data selector 28 which multiplexes 16-bit data to 8 pins. Reference numeral 29 denotes a read address counter which receives the output signal S8 of the counter 22 as an input signal and counts the addresses to be read.The read address counter 29 designates the read address to the memories 13 and 14 via the multiplex data selector 30. 31 is a data selector that outputs address data from data selector 28.30 to memory 13.14 in town.

The operation of this embodiment configured as described above will be described below.

The read clock 'vo' and the write clock f.

A case will be described in which the first drawback in which a section with no signal occurs in a larger state will be solved.

In Table 1 below, the number of addresses of the memory 13 or memory 14 is M bits, and the write clock is f.

This shows the state in which digital data D1 to DM (one of two values, high level or low level) is stored in the memory.

As described above, the memory 13 and the memory 14 alternately execute read and write operations, but the timing of the alternation of operations is determined by the write clock f. This is the point at which the number of memory addresses becomes equal to the total address number, that is, the capacity. In Table 1, digital data D1 ・D2 ~
DM is sample-linked by write clock f0;
The write address counter 27 and address multiplex data selector 28 sequentially store addresses in the memory starting from address number 1, and when the total number of write clocks f0 is M, address numbers 1 to M in the memory are stored in the memory in order. All digital data D1, D2 to DM will be stored in .

Margin below, then 1] Data written in two series D1 to D
The case of reading M is explained in Table 2 E11-1. No selection,
Read clock fv0 and write clock f. Toga fv
When there is a relationship of 0≦fo, there is data to be read, so it is only necessary to consider the case when f7°>fo.

In order to retrieve the digital data D1 to DM stored in the memory using the read clock fv0, the read address of the memory is designated by the read address counter 29 and the data selector 30 for address multiplexing. Since the total number of read clocks fv0 corresponds to the read address, output data is output according to the read clock fvo.

First, when the total number of read clocks fv0 is 1, the read address number is 1, so the memory content D1 stored at that address becomes output data. As the read clock f is counted up by 1, the address number is also counted up by 1. Then, when the total value of the read clock f becomes M +1, that is, at 1 o'clock when the memory capacity h↓M is exceeded, the read address is M
Instead of becoming +1, it becomes 1 again. When this read address exceeds the memory capacity iM, the method of decrementing M can be achieved simply by skipping the carry signal for incrementing the digit of the read address counter 29. That is, as shown in Table 2, when the total number of read clocks fvo is M-1-1, the address number is 1, and data D1 is obtained as output data. Thereafter, when the total number of read clocks fvo counts up by 1, the address number is counted up by 1 in the range 1 to M 1111, and the phenomenon that the memory operates as a circular memory and there is no output data at all does not occur. After switching, the read clock fv0 is interpolated by the clock f. This means that the section where there is no signal at all, which occurs when the value is larger, does not occur.

Next, a case will be described in which the second drawback in which discontinuous points occur is eliminated.

FIG. 6 shows an input/output waveform diagram of this embodiment when a 1-bit analog-to-digital converter typified by an ADM and the above-mentioned circular memory are used.

In FIG. 6, as seen in the conventional example, there is a period T where there is no signal at all, which occurs from time t9 to t1o and from time t11 to t12.
4 [Signal d) 4 to dl14 and d'7 to d''7 are supplemented, and these signals are continuously connected to the original signal. That is, the signal changes by one bit between high level and low level. Since it is expressed only in binary values, even if any two pieces of at'v snow data in the memory are connected, the data will be connected naturally and no discontinuity will occur.

As described above, according to this embodiment, a 1-bit analog-to-digital converter represented by an ADM is used as the analog-to-digital converter, and a digital memory represented by a RAM or the like is used as the memory, and its address is set to 1. Since it uses two circular memories that increase bit by bit, it is possible to easily obtain signals with different pitches with naturalness compared to the sound quality of the input signal, and it is also useful for complex signal processing. Node components such as microcomputers and software technology are no longer required, resulting in lower costs and space savings.

In this embodiment, the effect of the 1-bit analog-to-digital converter remains unchanged even when ADPCM or the like is used in addition to ADM.

Effects of the Invention As described in Section 2, according to the pitch conversion device of the present invention, when the frequency of the output signal of the variable frequency generator is made variable, it is possible to naturally convert a signal of a pitch different from the pitch of the input signal. It can be easily obtained with high performance, and it eliminates the need for hardware components such as microcomputers and software technology to perform complex signal processing, allowing for roasting and space saving, and the effects are outstanding. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional pitch conversion device, FIGS. 2 and 3 are doujin output waveform diagrams, FIG. 4 is an input/output waveform diagram of another conventional pitch conversion device, and FIG. Figure 5 is a failure]
FIG. 6, which is a block diagram of the pitch conversion device of one embodiment, is a doujin output waveform diagram. 12... 1-bit analog-to-digital converter, 13, 14... Memory, 16...
・Write enable signal generator, 18... Fixed write master clock generator, 19... Counter, 20... Controller, 21...
Ei Dinghen readout master clock generator, 22...
・Counter, 26...1 bit digital
analog converter. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure ///θ

Claims (1)

[Claims] A 1-bit analog-digital converter, a 1-bit digital-to-analog converter, two digital memories, and a signal 3° that selects the operation of the 1j0 digital memory as a single force for inputting or outputting each other. means for increasing the slipping address of the digital memory by 1 bit; means for increasing the escape address of the digital memory by 1 bit; and a clock with a fixed frequency for the analog/digital converter. A pitch converter comprising: a generating means; a clock generating means for changing the frequency of the output of the analog converter by 8J'; and an adjusting means for adjusting the clock generating means for adjusting the brightness by JN.