JPS6010459B2 - PLL circuit low-pass filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a low-pass filter for a PLL (phase locked loop) circuit, and particularly to a low-pass filter for a PLL circuit in a PLL synthesizer tuner of a receiver.

In a PLL synthesizer tuner, a comparator compares the frequency and phase of a reference oscillation signal and an output signal of a voltage controlled oscillator (VCO), and the output of this comparator is passed through a low-pass filter to a variable capacitance diode of the VCO. A PLL circuit is used to control the output signal frequency of the VCO, and the VCO output signal in this Pu circuit is used as a local oscillation signal of the receiver. An example of a phase comparator and a low-pass filter in a PLL circuit is shown in FIGS. 1A and 1B.

In Figure A, the output a of the phase comparator 1 becomes the base input of the bipolar transistor Q, which constitutes the low-pass filter 2, via the resistor R, and the resistor R2 is connected to one end of the integrating capacitor C. applied via. Transistor Q has an emitter follower configuration, and the output from its emitter resistor R3 becomes the base input of Darlington-connected output transistors Q2 and Q. The emitter of transistor Q3 is grounded, and its collector is connected to the terminal of capacitor C, and collector load resistance R.
It is connected to the positive power supply 10B via 4. The collector output of the transistor Q3 becomes an LPF (low pass filter) output, and is used as a control voltage for a variable capacitance diode of VC◯ (not shown). In figure B,
This is an example of a circuit in which a field effect transistor Q4 is used as an active element in the input stage of the LPF 2 to make the input impedance of the LPF almost infinite, thereby improving the circuit characteristics.

In the above configuration, the power supply voltage of the phase comparator 1 is generally a power supply for integrated circuits and is approximately 5V, and its output a
A so-called three-value (three-state) circuit configuration of OV (L), 5V (H), and open is used.

That is, the phase between the reference signal and the output signal of the VCO. When the frequencies match, the output a becomes extremely high impedance and becomes an almost open state. If there is a difference between the two, the duty (during pulse) will vary depending on the magnitude and direction of the difference, and the level will change. It is configured to output a pulse train of L or day. The output a of the phase comparator 1 is input to the low-pass filter 2, integrated, and converted to a DC level, which is then used as the control voltage of the VCO.When the output of the phase comparator 1 is in the oven state, the input of the LPF 2, i.e. The potential of the control electrodes of the input transistors Q, , Q4 is 3×V88×18V in the figure A, and 2×V88×1.2V in the figure B.

Furthermore, VB8 is the base of a bipolar transistor. The field effect transistor Q4 is assumed to operate at so-called loss (VGs=0).In this state, when a channel selection operation is performed and the frequency of the reference signal is varied and set to a desired value. , the PLL circuit is unlocked and operates to lock the output of the VCO to the reference frequency again.Therefore, the output a of the phase comparator is in the open state (1.8V) as shown in FIG. 2A. Therefore, if the LPF output in the locked state before the channel selection operation is 9V or IV (both voltages value corresponds to the maximum or minimum control voltage of the variable capacitance diode of the VCO), the output of the LPF after the tuning operation (after time t) is:
It changes as shown by curve 3 or 4 depending on the input state, that is, the pulse train of L or day, respectively. Incidentally, for convenience of explanation, the curve in FIG. B shows the case where the channel selection frequency is selected from the maximum to the minimum or vice versa. In this case, the output voltage of the output a of the phase comparator in the open state becomes 1 as described above.
．． 8V or 1.2V, which is different from the middle level (approximately 2.5V) of the pulse train and the L level, so the falling time situation m, as shown by curves 3 and 4 in FIG. There is a difference in the rise time T2 (T.<T2), and as a result, the PLL
The lock-up time of the circuit will be different between the two,
Therefore, designing the loop filter 2 is difficult.

Therefore, an object of the present invention is to provide a low-pass filter for use in a PLL circuit, which can equalize the rise and fall times of the filter output, adjust the lock-up time, and stabilize the operation of the PLL circuit.

The low-pass filter circuit of the present invention sets the voltage level of the control electrode of the transistor, which is an input active element, to approximately the middle between the highest and lowest output levels of the phase comparator when the output of the phase comparator is approximately in an open state. It is characterized by having bias means.

A preferred embodiment is characterized in that in an example in which a bipolar transistor is used as the input active element, a bias means made of a diode or a resistor is provided between the emitter of the transistor and a reference potential (ground).

In another embodiment, a field effect transistor is used as the input active element, and a bias means such as a diode or a resistor is provided between the source of the transistor and the reference potential (ground).

The present invention will be explained below with reference to the drawings.

3A and 3B are diagrams showing an embodiment of the present invention, and show circuit examples corresponding to those in FIGS. In A, a diode is used as the bias means 5 in series with the emitter resistor R3 between the emitter of the input transistor Q and the ground, and in B of the same figure, a diode is used in series with the source resistor R3 between the source of the input transistor Q and the ground. 5 series-connected diodes are provided as the bias means 5. Therefore, when the output a of the phase comparator 1 is open in both circuits A and B, the base and gate voltage levels are both 4×VBB. The voltage is 2.4V, and therefore, it is possible to set it to an intermediate potential with respect to approximately 5V.

As a result, the output a of the phase comparator 1 becomes as shown in FIG. It can be seen that both rise times are equal to T. Although a diode is shown as a biasing means, a resistive element may also be used, and a bibolar transistor may be used as a biasing means.
It is also possible to insert a stage or two stages into the same aircraft.

Furthermore, it is clear that biasing means may be used between the emitter and base of Darlington transistors Q2 and Q3. As described above, according to the present invention, the lock-up time of the PLL circuit can be made equal for both the falling and rising edges of the output of the LPF, thereby facilitating the design of the low-pass filter and stabilizing the loop.

[Brief explanation of the drawing]

FIGS. 1A and B are diagrams showing a conventional circuit array, FIGS. 2A and B are diagrams explaining the operation of the circuit in FIG. 1, and FIGS. 3A and B are circuit diagrams showing an embodiment of the present invention, 4A and 4B are diagrams for explaining the circuit operation of FIG. 3. FIG. Explanation of symbols of main parts, 1...Phase comparator, 2...
LPF, 5...Bias means, Q. ~Q...
・Transistor. Trunk/Figure 2 Fisting figure Shigaku Liu

Claims (1)

[Claims] 1. Provided in a phase lock loop having a phase comparator that compares the phases of a reference oscillation signal and a voltage-controlled oscillation signal and outputs a substantially open state when the two match, the output of the phase comparator is controlled. a low pass filter having a transistor applied to an electrode, the bias setting the voltage level of the control electrode approximately midway between the highest and lowest output levels of the phase comparator when the output of the phase comparator is approximately open; A low-pass filter for a phase locked loop circuit, characterized in that the biasing means comprises a diode and a resistor connected in series between the emitter (or source) of the transistor and a reference potential point.