JPS60103727A - Transistor circuit - Google Patents

Transistor circuit

Info

Publication number
JPS60103727A
JPS60103727A JP21116483A JP21116483A JPS60103727A JP S60103727 A JPS60103727 A JP S60103727A JP 21116483 A JP21116483 A JP 21116483A JP 21116483 A JP21116483 A JP 21116483A JP S60103727 A JPS60103727 A JP S60103727A
Authority
JP
Japan
Prior art keywords
transistor
trs
circuit
transistors
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21116483A
Other languages
Japanese (ja)
Inventor
Koichi Matsumoto
幸一 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP21116483A priority Critical patent/JPS60103727A/en
Publication of JPS60103727A publication Critical patent/JPS60103727A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors

Abstract

PURPOSE:To cope with an input/output condition of circuits connected before and after through the simple change of circuit constant by providing two transistors (TRs) connected in a differential form, two TRs connected in parallel therewith and a TR connected in a differential form. CONSTITUTION:NPN TRs 1, 2 are connected in a differential form and have collector load resistors 6, 7 respectively with equal resistance value. TRs 3, 4 are connected in parallel and receive an output of the TRs 1, 2 respectively. A common collector of the TRs 3, 4 is connected to a load resistor 8. A TR5 is connected to the TR3 (TR4) in a differential form. Through the constitution above, the circuit copes with the input/output condition of circuits connected before after the titled circuit by means of a simple change in the circuit constant and a TR circuit constituted with less number of components and suitable for exclusive OR is obtained.

Description

【発明の詳細な説明】 不発明はトランジスタ回路に関し、特にトランジスタ論
理回路に関する。DETAILED DESCRIPTION OF THE INVENTION The invention relates to transistor circuits, and more particularly to transistor logic circuits.

例えば、排他的論理和等のトランジスタ回路は、相補型
絶縁ゲートトランジスタ（Ｃ−Ｍ（、＋８）ｍａやＴＴ
Ｌ構成などで作られたものが製品化されているが、たと
えば、一つの牛導体果屓回路内部でアナログ、ディジタ
ルの両方の信号を取扱う場合。For example, a transistor circuit such as an exclusive OR is a complementary insulated gate transistor (CM(,+8)ma or TT
Products made with the L configuration have been commercialized, but for example, when handling both analog and digital signals within a single conductor circuit.

従来のＴＴＬ等で用いられている回路全そＶまま集積し
叔うとすると、素子数の増大をまねき、さらには出力レ
ベル合せなどの問題が生じていた。If all the circuits used in conventional TTL etc. were to be integrated with the same voltage, the number of elements would increase and problems such as output level matching would arise.

不発明の目的はｂ　ｎ’ｌＪ後に接続される回路の入出
力条件に対して簡単な回路定数の変更で対応でき。The object of the invention is to be able to respond to the input/output conditions of the circuit connected after b n'lJ by simply changing the circuit constants.

しかも少ない素子数でイノ１４成できる排他的論理和に
適したトランジスタ回路全提供することにある。Moreover, it is an object of the present invention to provide a complete transistor circuit suitable for exclusive OR which can be implemented with a small number of elements.

不発明の他の目的は、ディジタルおよびアナログ信号の
両方？処理する集積回路に構成された排他的論理和に適
したトランジスタ回路を提供することにある。Other purposes of non-invention both digital and analog signals? An object of the present invention is to provide a transistor circuit suitable for an exclusive OR configured in an integrated circuit for processing.

不発明によるトランジスタ回路は、入力１ぎ号を受け差
′ＩｊＩＪ型弐に接続された第１および第２のトランジ
スタと、これらの谷コレクタ出力全それぞれ受け互い並
列に接続された第３および第４　ｖ）ランジスタと、第
３のトランジスタ（第４のトランジスタ）ＩＣ対して差
動型式に接続された第５のトランジスタと全有すること
全特徴とする。The transistor circuit according to the invention includes first and second transistors connected in a differential 'IjIJ type two receiving an input signal, and third and fourth transistors receiving all of their valley collector outputs and connected in parallel with each other. v) a transistor and a third transistor (fourth transistor) and a fifth transistor connected differentially to the IC.

以下、不発明を図面を用いて詳細に説明する。Hereinafter, the invention will be explained in detail using the drawings.

第１図に不発明の第一の実施例金示す、ＮＰＮｌ゛ラン
ジスタ１，２は差動型式に接続され、夫々コレクタ負荷
抵抗６，７を有する・抵抗６，７の抵抗値は互いに等し
い。定電流源９は差ｗＪ型式のトランジスタ１，２の電
流源で、Ｉ９なる定電流を流す、ＮＰＮトランジスタ３
，４．５は出力回路を構成する。トランジスタ３，４は
並列接続されトランジスタ１，２の出力全夫々受ける。A first embodiment of the invention is shown in FIG. 1, in which NPN transistors 1 and 2 are connected in a differential manner and have collector load resistors 6 and 7, respectively.The resistance values of resistors 6 and 7 are equal to each other. A constant current source 9 is a current source for differential wJ type transistors 1 and 2, and is an NPN transistor 3 that flows a constant current I9.
, 4.5 constitute an output circuit. Transistors 3 and 4 are connected in parallel and receive all the outputs of transistors 1 and 2, respectively.

トランジスタ３．４の共通コレクタは負荷抵抗８に接続
されている。トランジスタ５は、トランジスタ３（トラ
ンジスタ４）に対して差動型式に接続され、電流１１０
　なる足型Ｒ源１０で駆動される。The common collector of transistor 3.4 is connected to load resistor 8. Transistor 5 is connected differentially to transistor 3 (transistor 4) and has a current of 110
It is driven by a foot-shaped R source 10.

トランジスタ５０ベースはバイアス源１１からバイアス
電圧が供給されている。入力端子１２．１３はトランジ
スタ】、２のベースに、出力端子１４はトランジスタ３
（４）のコレクタにそれぞれ接続されている。端子１５
−１６間に電源電圧ＶＣＣが印加される。A bias voltage is supplied to the base of the transistor 50 from the bias source 11. The input terminals 12 and 13 are the bases of transistors 2 and 2, and the output terminal 14 is the base of transistor 3.
(4) are respectively connected to the collectors. terminal 15
A power supply voltage VCC is applied between -16 and 16.

今仮に、入力端子電圧Ｖ１２とＶ１３　がともにハイレ
ベルであってトランジスタ１，２を飽和させないレベル
ｖＨｉｃ６るとすると、トランジスタ１．２には等しい
％流であ−って定電流源９０半分の一流１／２１ｓが流
れる。したがって、トランジスタ１．２の各コレクタの
電位は等しく、その電位は、負荷抵抗６，７の値ｔ■モ
とおくとｖｃ、−−：ｔ、　＃Ｒ。Now, if the input terminal voltages V12 and V13 are both high level and set to a level vHic6 that does not saturate transistors 1 and 2, the transistor 1.2 has an equal % current, which is half the current of the constant current source 90. 1/21s flows. Therefore, the potentials of the respective collectors of the transistors 1.2 are equal, and if the values of the load resistors 6 and 7 are t, then vc, --:t, #R.

となる。becomes.

入力端子電圧Ｖ１２．Ｖ１３かともにロウレベル■Ｌ〔
このレベルは、ハイレベルｖ、Ｉより少くとも１００・
９７以上低く、かつ尾篭流源９が飽和等の異常動作？お
こさない＃ｆｆ　ＩｔＣあらかじめ定めている〕のとき
、前述の場合と同様トランジスタ１．２のコレクタ電位
は互いに等しくて　ｖｃｃ−１ｇＲ１となる。Input terminal voltage V12. Both V13 and low level L [
This level is at least 100· higher than the high level v,I.
Is it lower than 97 and Ogoro flow source 9 is operating abnormally such as saturation? When #ffItC is not caused (predetermined), the collector potentials of transistors 1 and 2 are equal to each other and become vcc-1gR1, as in the case described above.

すなわち、　Ｖ１２．　Ｖ１３の電位が等しい場合は、
その値がＶＨ，ＶＬのいかんにかかわらず、トランジス
タ３．４のコレクタ電位は等しく、ともにＶ、。−−１
，几□である。That is, V12. If the potentials of V13 are equal,
Regardless of whether its value is VH or VL, the collector potential of transistor 3.4 is the same, both VH and VL. --1
, 几□.

そこで、バイアス＄１１の電圧Ｖｘｘｆなる関係を持つ
よう定めると、トランジスタ５は４通状態、トランジス
タ３，４はしゃ断状態となり、出力端子１４の電位Ｖ１
４は■。０と等しい。Therefore, if the relationship is set to have the voltage Vxxf of bias $11, transistor 5 will be in the 4-on state, transistors 3 and 4 will be in the cut-off state, and the potential of output terminal 14 will be V1.
4 is ■. Equals 0.

次に、Ｖ１２＝ＶＬ　Ｖ１３＝ＶＨ，の場合を考える。Next, consider the case where V12=VL and V13=VH.

このとき、定電流源９の電流はすべて、トランジスタ２
に流れ、トランジスタ１はしゃ断状態となる。したがっ
て、トランジスタ２のコレクタ電位は　■。、−４，・
Ｒ１とな、！２、一方、トランジスタ１のコレクタ電位
は、ＶＣＣに等しくなる。ここで、出力回路のトランジ
スタ３．４．５のペース電位をそれぞれＶａ、　Ｖ４．
　Ｖｓとすると、ｖ３：ｖ、ｏ＞Ｖｓ＝Ｖ１１）Ｖ４＝
Ｖ（（Ｈ−ＩｇＲｌなる関係を持つ。よって、トランジ
スタ４．５はしゃ断状態となり、電流源ｌＯの電流１１
０　は、すべてトランジスタ３に流れる。この結果、負
荷８の値’（ｉ−）ｔ８とおくと、出力端子１４の電位
Ｖ１４Ｖｌ　４＝Ｖ、。−１１ｏｔｔａ となる。At this time, all the current of the constant current source 9 flows through the transistor 2
, and transistor 1 enters a cutoff state. Therefore, the collector potential of transistor 2 is (2). , -4,・
With R1! 2. On the other hand, the collector potential of transistor 1 becomes equal to VCC. Here, the pace potentials of transistors 3, 4, and 5 of the output circuit are set to Va, V4.
If Vs, then v3:v, o>Vs=V11)V4=
V((H-IgRl). Therefore, the transistor 4.5 is cut off, and the current 11 of the current source lO
All 0 flows to transistor 3. As a result, when the value of the load 8 is set to '(i-)t8, the potential of the output terminal 14 is V14Vl4=V. -11otta.

Ｖ　１２＝ＶＨ，ｖｌ　３　：Ｖ−Ｌ　ｖ）場合ｕ　ｓ
　Ｖ　’　＝■ＣＣ＞＞Ｖ５二Ｖ１１＞’Ｖ３＝ＶＣ，
−Ｉ！１几１　となハ　トランジスタ３，５がし一？断
状ｔａ、トランジスタ４が４通し、出力端子１４の゛重
圧Ｖ１４は Ｖ１４＝Ｖｏ、−１１０几８ となる。V 12 = VH, vl 3 :V-L v) If u s
V'=■CC>>V52V11>'V3=VC,
-I! 1 几1 Tonaha Transistor 3, 5 Gashiichi? When the cross section is ta and the number of transistors 4 is four, the pressure V14 at the output terminal 14 is V14=Vo, -110°8.

ここで、新ためてＶ１４＝Ｖｏｏ　を出力のハイレベル
、Ｖ１４二Ｖ。ｃ−ＩｘｏＲ８全出力のロウレベルと足
め、ハイ状態２Ｈ，ｏつ状態’ｔＬで辰わ丁と、第１表
に示す関係〃Ｓ入出力間に成立する・第　１　表 ところで、前述のような入力条件全もつ例としては、Ｂ
ＣＬＣノロクがおる。またＴＴＬ−？ＣＭＯ８とは入力
レベルの分圧等で対応できる。アナログ回路とのインタ
フェースにおいてはひかく的答易に接続可能なことが多
い。バイアス源１１の電圧トランジスタｌ又は２の遮断
状態の時のコレクタ出力より低い電圧全選べば良い、ま
た出力はトランジスタ５のコレクタに負荷金入れて取り
出せば第１表のＶ１４　とは反転した出力全書ることか
できる。Here, V14=Voo is newly output at high level, V142V. The relationship shown in Table 1 is established between the low level of all c-IxoR8 outputs, the low level of all outputs, the high state 2H, and the low state 'tL. As an example with all input conditions, B
CLC Noroku is here. Also TTL-? It can be used with CMO8 by dividing the input level. In many cases, the interface with analog circuits can be easily connected. All voltages of bias source 11 that are lower than the collector output when transistors 1 or 2 are in the cut-off state can be selected, and if the output is taken out by putting a load into the collector of transistor 5, all outputs will be reversed from V14 in Table 1. I can do that.

第２図に第二の実施例？示す、第１図とは、出力回路を
構成するトランジスタの導電型が異なっていてＰＮＰ型
のトランジスタ２１，２２．２５で構成されており、定
電流源２４は、第１図とは逆の電源端子３１側に接続さ
れている。トランジスタ１６．１７は入力差動アンプを
構成し、負荷抵抗１９．２０．定電流源１８？、もつ。The second embodiment in Figure 2? The conductivity type of the transistors constituting the output circuit is different from that shown in FIG. It is connected to the terminal 31 side. Transistors 16, 17 constitute an input differential amplifier, and load resistors 19, 20, . Constant current source 18? ,Motsu.

抵抗１９．２０の抵抗値は等しくてこれｔＲ３とし、゛
電流源１８．２４の電流値上告々１１８．Ｉ２４゜抵抗
２３の抵抗値を几４．バイアス諒２６の電圧値全Ｖ２６
とすると、各定数の関係Ｑよ次のように定められている
。　− ＶＣＣ−ｉｌｇ　’ｉもａ　＞　Ｖ２　ｅ＞Ｖｃ　ｃ−
１□ａ　’Ｒ３几４°Ｉ２４≧Ｖ’ＢＥ２Ｂ 入力端子ｔｔｉ圧Ｖ２　ｇ＝Ｖｆ（、Ｖａ　ｏ＝’ＶＬ
　あるいｕ、Ｖ２．＝ｖＬ　Ｖ３ｏ二ＶＪ（の場合Ｖｃ
１沢り、抵抗２３に電流が流れトランジスタ２８全尋通
状態にし、出力端子３２の電位上’Ｖｒ、（中Ｖｃｅ５
ａｔ）４で下げる。The resistance values of the resistors 19 and 20 are equal and are designated as tR3, and the current value of the current source 18 and 24 is 118. I24°Resistance value of resistor 23 is 4. Bias level 26 voltage value total V26
Then, the relationship Q between each constant is defined as follows. - VCC-ilg 'i also a > V2 e>Vc c-
1□a'R3几4°I24≧V'BE2B Input terminal tti pressure V2 g=Vf(, Va o='VL
Or u, V2. =vL V3o2VJ (in case Vc
1, a current flows through the resistor 23, making the transistor 28 fully conductive, and the potential at the output terminal 32 becomes Vr (middle Vce5).
at) lower by 4.

したがって、入力電圧と出力電圧の胸係會第２表に示す
ように、排他的論理関係が侍られる。尚。Therefore, as shown in Table 2, an exclusive logical relationship is observed between the input voltage and the output voltage. still.

不例でも出力論理振幅が広く、次段へのインタフェース
が答易でおる。Even in rare cases, the output logic amplitude is wide and the interface to the next stage is easy.

第　２　表 本発明はＰＮＰ、ＮＰＮ　）ランジスタの別なく少ない
素子数で排他的論理和を実現でき、半導体集積回路に好
適である。Table 2 The present invention can realize exclusive OR with a small number of elements regardless of whether it is a PNP or NPN transistor, and is suitable for semiconductor integrated circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第１及び第２図は夫々不発明の実施例を示す回路図であ
る。 １〜５・・・・・・トランジスタ、６〜８・・・・・・
抵抗、９〜１０・・・・・・定電流源、１１・・・・・
・バイアス電圧諒、１２〜１５・・・・・・端子、１６
〜１７・・・・・・トランジスタ、１８・・・・・・定
電流源、１９〜２０・・・・・・抵抗、２１〜２２・・
・・・・トランジスタ、２３・・・・・・抵抗、２４・
・・・・・定電流源、２５・・・・・・トランジスタ、
２６・・・・・・ノくイアス玉圧源、２７・・・・・・
抵抗、２８・・・・・・トランジスタ、２９〜３２・・
・・・・１〆Ｉ′１ｊ子。 笛２〆1 and 2 are circuit diagrams each showing an embodiment of the invention. 1-5...transistor, 6-8...
Resistance, 9-10... Constant current source, 11...
・Bias voltage, 12-15...Terminal, 16
~17...Transistor, 18...Constant current source, 19-20...Resistor, 21-22...
...Transistor, 23...Resistor, 24.
...constant current source, 25...transistor,
26... Nokuias ball pressure source, 27...
Resistor, 28...Transistor, 29-32...
...1〆I'1j child. Flute 2〆

Claims (1)

【特許請求の範囲】[Claims] 差動型式に接続された第１および第２のトランジスタ（
１）、　（２）と、前記第１および第２のトランジスタ
の出力’ｔ−／夫々受夫々−に並列に接続された第３お
よび第４のトランジスタ（３３，（４１と、前記第３の
トランジスタに対して差動型式に接続された第５のトラ
ンジスタ（５）とを有することを特徴とするトランジス
タ回路。a first and a second transistor (
1), (2), and the third and fourth transistors (33, (41) and the third A transistor circuit characterized in that it has a fifth transistor (5) differentially connected to the transistor.
JP21116483A 1983-11-10 1983-11-10 Transistor circuit Pending JPS60103727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21116483A JPS60103727A (en) 1983-11-10 1983-11-10 Transistor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21116483A JPS60103727A (en) 1983-11-10 1983-11-10 Transistor circuit

Publications (1)

Publication Number Publication Date
JPS60103727A true JPS60103727A (en) 1985-06-08

Family

ID=16601457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21116483A Pending JPS60103727A (en) 1983-11-10 1983-11-10 Transistor circuit

Country Status (1)

Country Link
JP (1) JPS60103727A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5498982A (en) * 1994-07-29 1996-03-12 Texas Instruments Incorporated High speed comparator with a precise sampling instant

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5498982A (en) * 1994-07-29 1996-03-12 Texas Instruments Incorporated High speed comparator with a precise sampling instant

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