JPS60101699A - 2-wire type transmitter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention <Industrial Application Field> The present invention detects a process quantity, converts it into a current signal of a predetermined span such as 4 to 20 mA, and connects two wires to a series circuit of a power source and a load at a remote point. 2-wire transmitter.

<Prior art> Figure 1 shows an example of the configuration of a typical conventional two-wire transmitter.
ESl'i process amount P is set as current signal 1. 12 indicates a feedback current, these currents flow through a series circuit of resistors R4 and R2, and the voltage ei generated at the connection point of Rll and R2 is amplified by an operational amplifier op forming an amplifier circuit. . R3 is a potentiometer for setting a potentiometer for setting the operating point of this operational amplifier OP. TS is a current adjustment means controlled by the output of oP, and adjusts the output current in a span of 4 to 20 mA. R4 is the output current i. is supplied to the feedback potentiometer, and the voltage drop is divided by the slider and converted into a voltage eF for generating the feedback current 12. T1° is applied and the output current l. flows. The series circuit of the constant current circuit CC and the Zener diode ZD is a constant current receiving type voltage stabilizing means connected between the two wires L11L2, and supplies a stabilized voltage v2 to ES and OP.

In such a configuration, the span is changed by changing the voltage division ratio of the feedback potentiometer R4.

The problem here is the output current l corresponding to the change in the process amount P detected and converted by the ES. When changing the relationship (span) with the amount of change in R4 by operating R4, in addition to the change in the feedback voltage ep from R4, the resistance network RRR connected from the output point of ES to the common potential point C A change in the combined resistance value occurs, and el shifts 41 21 4 tosi, therefore l. The operating zero point (4 mA) of is shifted. This is generally called a zero shift associated with a span changing operation, and it has been difficult to easily avoid this mutual interference effect.

As another means of configuring the resistor network of the feedback circuit, as shown in FIG.
How to connect to the bias setting side of the e
There is a method in which the voltage obtained by dividing F and ■2 by resistors R5 and R2 is used as one input of the operational amplifier OP, and the bias setting by R3 is connected to the other input of the operational amplifier OP along with the resistor R1 via the resistor R6. However, the occurrence of zero shift by changing the potentiometer R4 is the same as in the case of FIG.

An effective solution to this mutual interference problem is to insert a buffer amplifier with a gain of 1 between the potentiometer R and the resistor R2, but since the input burst of this amplifier is on the negative side of the common potential C, A two-wire configuration is difficult to implement because there is no means for supplying power to the buffer amplifier.

<Configuration of the Present Invention> The present invention has been made in view of the problems of the prior art described above, and focuses on the fact that the cause of the problem is that the circuit constant of the feedback circuit changes when changing the amount of feedback. Instead of conventional analog feedback, the output current value to be adjusted is converted into a continuous pulse signal such as a duty cycle to generate a feedback signal, and the current/duty cycle conversion characteristics are adjusted. It is characterized by changing the amount of feedback and changing the span.

<Examples> Examples of the present invention will be described below based on the drawings. Fourth
The figure is a basic configuration diagram showing one embodiment of the present invention, and the same elements as those of the prior art shown in FIG. 1 are given the same reference numerals and redundant explanations will be omitted. In this example, the output ep of the process amount detection conversion circuit ES is the same as the output of the C-MOS gate G1, and the peak value ■2. It is given by a continuous pulse train signal of Tutee Ds. On the other hand, the output current 1° is converted to a duty D which is inversely proportional to io by the current/tidy cycle conversion circuit CD.
. is converted into a continuous pulse signal eF, and then converted into a signal 8F' whose peak value is regulated to V2 via a C-MOS gate (G) driven at V2. eP and p eF' are added via resistors R1 and R2, respectively, to form a non-inverting input filter of operational amplifier OP.

In such a configuration, when the bias voltage of the operational amplifier op set by R3 is VR5, the circuit is balanced when the sum of the average voltages of eP and e' matches VRs. That is, VR3-Vz (DS ・R2+ Dc -n,)/
(R1+R2) (For example, Vz=6'V
, Vn s = 5 V, R1 = R2, the equilibrium condition is according to equation (1). The duty of Dc and Ds is Ds = 4.
When 0%, DC=60% When Ds=50%, D
C is 50 inches Ds: When it is 60%, DC is 40 inches.

In the above explanation, the ES output (lp is the duty cycle signal ep), but any analog output, e.g.
s, the equilibrium condition is VR3,= (R8・R2+V2−Do−R,)/(
R1+R2) (2) Tonashi, v2= 6 V,
The equilibrium conditions when VR3 = 3'V, R, = R2 are: When Es, = 2.4 V, DC = 60% Es = 3
．． At 0 V, DC=50%Es: At 5.6 V, DC=40%.

That is, the current/duty cycle conversion circuit CD outputs an output current I. The equilibrium condition of equation (2) above means that the amount of change in the process amount P corresponds to the amount of change in the output current I. Therefore, by changing the data D, the range of change of 1 degree of output current, that is, the span, can be changed arbitrarily.

The one-dot chain line block in FIG. 5 shows an example of the basic configuration of the current/duty cycle conversion circuit CD, which is the main part of the present invention. BP is a bypass circuit, and is composed of a transistor whose emitter-collector circuit is connected between the common potential point C and the output terminal 12. TA is a triangular wave generation circuit that controls the base potential of this transistor to control the bypass current capacity iB flowing through the emitter-collector circuit in a triangular wave shape, and CT is a base-emitter circuit that is connected between the common potential point C and the output terminal 12. A transistor forming a connected current detection circuit whose collector is connected to the stabilizing voltage v2 via a high impedance load CL and whose collector voltage is used as a feedback signal eF with a duty inversely proportional to 1°. The structure is as follows.

6 and 7 are operation explanatory diagrams, and FIG. 6 (4) shows the output current l. This shows the relationship between the bypass current capacity lB (shown by the dotted line) and the output current i during the period T1 where rB≧io. flows through the bypass circuit BP to the terminal T2, so the current lD flowing through the base and emitter of the current detection circuit CT is zero as shown in ψ), so the transistor of the current detection circuit CT is turned off, and the collector potential eF becomes high level v2 as shown in (C). l
In the period T2 where B<io, the current I of lD=1o-1B
Since D flows through the base-emitter circuit of the CT and the CT is turned on, the collector potential is at a low level, that is, the output terminal T2.
It is held at a potential of Duty D of ely in this case
. becomes T1/(TI+T2).

1o is l as shown in FIG. 7(4). ′, the period T during which the ID is zero, and the period T2 during which the ID is on is shortened, so the duty DC of eF is
is Tlt/(T,'+T2'), and the duty ratio in FIG. 6 becomes a dog. That is, the duty of eF is the output current l. is inversely proportional to.

FIG. 8 shows an example of a circuit configuration for concretely realizing a current/date cycle conversion circuit, and shows an example suitable for integrating the entire circuit into an integrated circuit. The triangular wave generation circuit TA is an integrator Q.
Comparator Q2. From C-MO8 gate G3), the voltage obtained by dividing the integrated output of Ql with the span setting potentiometer RV was compared with a constant set voltage (3V) in G2, and the comparison output was waveform-shaped in G3. feedback to the input of Ql.9th
Figure (4) shows the waveform of the output eT of Ql, 03) shows the output waveform of G, and (C) shows the input waveform of G2. The output has an amplitude of 4v
The slope of the triangular wave eT can be changed by setting jll and RVl.

BP is a control circuit that receives the output eT of Q and controls the bypass current iB into a triangular wave, and includes an operational amplifier Q3 and small current generation transistors Q4 and G3 driven by its output.
Clamping transistor Q5 connected between the input and output of
Q8 supplies a minute current of il/n from G4 to bypass circuit BP2. BP2 is transistor Q9~Q
, 2 and the bypass current iB are detected and fed to the control circuit BP.
Output terminal T2
Has the ability to bypass. G4°Qqp Q10 forms a so-called current mirror circuit. With this configuration, the bypass ability of the bypass current IB is controlled in a triangular waveform following the triangular wave output eT of Ql.

The current detection circuit CD is composed of transistors Q13 to Q14, and its high impedance load CL is a transistor Q
, Q and their control trunks 16 17 and star Q18. G4 and Q181Q16 are B
P2 transistor Q91 Ql. Similarly, it forms a current mirror circuit together with G4.

In such a configuration, as shown in ) in FIG.
In the period T1 where B≧IO, the bypass current IBa i. However, the actual bypass current is the output current l. Since the above cannot be achieved, the feedback loop of control circuit BP1 does not close, and the output of G3 tries to swing out, but the output is clamped flat by the clamp circuit formed by Q5 to Q8, and IB is approximately When the level is equal to l, ip becomes zero, so IIF becomes high level as shown in (g)). 13〈io period T
2 is the same as in Figure 6, 1D=io-1B, and e
p is held at low level. In ([)) I. is i. When the data falls to
T.D. l as explained in FIG. increases in inverse proportion to.

The period T of the flat part of the bypass current 1 in Figure 9)
1. T,' can be changed by changing the operation setting potential E□ of the operational amplifier Q3 of the control circuit BP1. In other words, when ER is increased, T
, the period of time becomes shorter. In this way, depending on the ER settings,
A change in the flat part of the l. Since the point of comparison with the current value changes, the zero point of the eF date is changed.

The embodiment shown in FIG. 11 is an embodiment in which the operational amplifier OP part in the embodiment shown in FIG. It is effective when given as a pulse signal. With this configuration, it is possible to realize a two-wire transmitter that has an extremely high degree of freedom in performing various non-linear calculations, compensation, etc. that cannot be realized with an operational amplifier, and can also be equipped with a digital display function such as an LD. can.

It should be noted that the present invention can be applied to the continuous pulse signal even if it is a pulse frequency signal other than a data cycle signal.

<Effects> As explained above, according to the present invention, since a continuous pulse signal related to the output current is used as a feedback signal, changes in the span that were unavoidable with conventional resistance network coupling occur. It is possible to completely avoid mutual interference with the zero point, and it is possible to realize a two-wire transmitter that ensures independence of zero point adjustment and span adjustment.

[Brief explanation of the drawing]

Figures 1 to 3 are basic configuration diagrams of conventional two-wire transmitters;
FIG. 4 is a basic configuration diagram showing one embodiment of the present invention, FIG. 5 is a basic configuration diagram showing an example of a current/tute cycle conversion circuit which is the main part, and FIG. FIG. 7 is an explanatory diagram of its operation, FIG. 8 is a circuit configuration diagram showing an example of a concrete implementation means of FIG. 5, FIGS. 9 and 10 are explanatory diagrams of its operation, and FIG. FIG. 2 is a basic configuration diagram showing an embodiment of the present invention. ES...detection conversion circuit, OP...operational amplifier, TS
...Current adjustment means, CD...Current/date cycle conversion circuit, BP...Bypass circuit, CT...Current detection circuit, TA...Triangular wave generation circuit, io...Output current, ep...feedback signal.

Claims (1)

[Claims] A constant current receiving type voltage stabilizing means is supplied with power through two wires and is connected between the two wires, a process quantity detection conversion circuit energized by this means, and a process amount detection conversion circuit of this detection conversion circuit. an amplifier circuit that amplifies the difference between the output and the feedback signal; current adjustment means that adjusts the current flowing through the two wires in response to the output of the amplifier circuit; A two-wire transmitter, comprising: conversion means for converting into a continuous mode, and using the pulse signal as the feedback signal.