JPS599966B2 - Synchronous signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a synchronization signal generation circuit for obtaining a synchronization signal corresponding to speed deviation when a tape recorder that mainly records analog signals, such as an audio tape recorder, is used for recording and reproducing digital signals. Regarding.

Generally, when magnetically recording and reproducing digital signals, a highly accurate dedicated magnetic recording and reproducing device is required to maintain a constant tape speed, resulting in high costs.

The present invention proposes a circuit that generates a synchronization signal in accordance with fluctuations in the playback speed appearing in the playback signal when recording and playing back digital signals in a tape recorder with a large speed deviation such as an audio tape recorder. It is.

The details of the present invention will be described below in accordance with illustrative embodiments. Fig. 1 is a block diagram showing the main parts of the synchronization signal generation circuit according to the present invention, and Fig. 2 shows waveform diagrams of each part. The zero cross detection circuit 2 generates a pulse by
Sawtooth wave generation circuit reset by input pulse, 3
is a level detection circuit that detects a potential above a certain level,
4 is a bistable multivibrator; 5 and 1 are first and second gate circuits; 6 is a reference pulse generation circuit whose period is extremely small compared to the time between zerox points of an FS modulation pilot signal, which will be described later; 8 and 9 are first and second counters that count input pulses; 10 is a coincidence detection circuit that generates a pulse when the outputs of both counters match; 11 is a frequency dividing circuit that divides the frequency of the pulse by one; 12 2 respectively show OR circuits, and the illustrated waveforms in FIG. 2 are waveform diagrams of various parts at point ai in FIG. 1.

The operation of the present invention will be described in detail below. The recording signal is composed of 3-value 5 information (1 information/lmsec) of pilot signal, digital signal "0", "1", and n (n = A pilot signal is placed every 10 meters, and the pilot signal is set to FO in order to record the signal.
(FO is a frequency with a period for one information) (1KHz),
FS modulation is performed to a three-value frequency in which 'O'' of the digital signal is 2f0 (2KHz) and Obi of the digital signal is 3f0 (3KHz), and magnetically recorded on the audio tape recorder (not shown). When reproducing a modulated recording signal, first input the reproduced signal a to the zero-crossing detection circuit 1 to convert the zero-crossing point of each modulated signal into a pulse,
By resetting the sawtooth wave generating circuit 2 which enables a bootstrap circuit or the like using the converted output pulse b, the pulse interval is converted into a high/low potential. Next, from the sawtooth wave output width c, the output pulses P, P2d of the level detection circuit 3 whose level is set so that only the sawtooth wave based on the pilot signal can be detected are input to the subsequent flip-flop 4. , a rectangular wave e having a width half the period of the FS modulated pilot signal in the reproduced signal is obtained. Furthermore, the rectangular wave e
Then, the pulse output is input to the first gate circuit 5, and the pulse P1 is taken out and the first counter circuit 8 is cleared. Further, the reference pulse generation output g/(1MHz) when the flip-flop output is in the 0N state is passed through the second gate circuit 7 and inputted to the first counter 8 after clearing, and the pano μg is counted. By doing so, at the same time as setting the reference period, the clearing of the second counter 9 is canceled by the flip-flop output e that has passed through the 0R circuit 12, and counting of the reference pulse generation output is started. The output pulse h of the coincidence detection circuit 10, which is emitted when the numerical value matches the count value of the first counter 8, is used as a reset pulse for the second counter 9, and the pulse h that has been cleared in advance by the output of the flip-flop circuit 4 is used. The frequency is divided by one in the circuit and the synchronization signal 1 is generated.
can be obtained. Note that, in order to derive the odd-numbered output pulse h as the synchronization signal h, the -frequency divider circuit 11 is constituted by, for example, a flip-flop that inputs the output pulse and a differentiation circuit that differentiates the rising edge of the flip-flop output. Yes. Furthermore, the number j in FIG. 2 is a demodulated output obtained by inputting the reproduced signal a to an FS demodulation circuit (not shown). According to the present invention, when the playback speed increases due to a change in tape speed, the width of the pilot signal becomes shorter and the reference period of the first counter also becomes shorter, so that the synchronization signal is generated at a shorter period, and When the playback speed becomes slow, a synchronization signal with a long cycle is generated.

Therefore, with the synchronization signal obtained by the above method, FM
If the demodulated output obtained from the FS demodulating circuit is sampled, reliable digital reproduction is possible regardless of the tape speed, which is highly effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a synchronizing signal generating circuit according to the present invention, and FIG. 2 shows a waveform at point a-1 in FIG. Explanation of main figure numbers, 1... Zero cross detection circuit,
2... Sawtooth wave generation circuit, 3... Lebel detection circuit, 4... Bistable multivibrator,
6... Reference pulse generation circuit, 8... First counter, 9... Second counter, 10...
...match detection circuit, 11...1 minute)
) 2-circuit circuit.

Claims (1)

[Claims] 1. In a reproducing device that reproduces a magnetic tape that is made by interpolating a 1-bit pilot signal into a digital signal and recording the pilot signal at the fundamental frequency and the digital signal at its multiplied frequency using FS modulation, the pilot signal is a detection circuit that detects a half cycle of the data bit; a reference pulse generation circuit that generates a reference pulse whose cycle is sufficiently shorter than that of the data bit; a first counter that counts the reference pulse during the detection output generation period; a second counter that counts the reference pulses immediately after the completion of counting, a coincidence detection circuit that detects coincidence between the outputs of the first and second counters, and a line that uses the coincidence detection output as a reset input of the second counter; 1 for generating a synchronization signal for sampling the demodulated output of the reproduced signal by dividing the frequency of the coincidence detection output by 1/2;
/2 frequency divider circuit.