JPS5999238A - Surface inspecting device - Google Patents

Surface inspecting device

Info

Publication number
JPS5999238A
JPS5999238A JP57209047A JP20904782A JPS5999238A JP S5999238 A JPS5999238 A JP S5999238A JP 57209047 A JP57209047 A JP 57209047A JP 20904782 A JP20904782 A JP 20904782A JP S5999238 A JPS5999238 A JP S5999238A
Authority
JP
Japan
Prior art keywords
circuit
width
signal
inspected
histogram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57209047A
Other languages
Japanese (ja)
Other versions
JPH0562293B2 (en
Inventor
Chiaki Fukazawa
深沢 千秋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP57209047A priority Critical patent/JPS5999238A/en
Publication of JPS5999238A publication Critical patent/JPS5999238A/en
Publication of JPH0562293B2 publication Critical patent/JPH0562293B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84Systems specially adapted for particular applications
    • G01N21/88Investigating the presence of flaws or contamination
    • G01N21/89Investigating the presence of flaws or contamination in moving material, e.g. running paper or textiles

Landscapes

  • Engineering & Computer Science (AREA)
  • Textile Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Biochemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Immunology (AREA)
  • Pathology (AREA)
  • Length Measuring Devices By Optical Means (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Image Processing (AREA)
  • Image Analysis (AREA)

Abstract

PURPOSE:To decide on the kind of a flaw from the distribution state of a signal outputted after a height and then a breadthwise decision on the histogram of a body to be inspected, by making those decision on the histogram at specific conveyance-directional intervals of length in every breadthwise division. CONSTITUTION:A pulse corresponding to the specific conveyance-directional length of the body 11 to be inspected is outputted by a pulse generator 20 and counted by a counter 144 to sends an operation command to a control circuit 145. The control circuit 145 starts reading data out of a buffer memory 143 and the data is compared by a height deciding circuit 15 with a set value H to output a signal to the output terminal of a comparing circuit when the data is larger than the set value. The output signal is counted by the counter 161 of a width deciding circuit 16 and the counted value is compared with a width set value W by a comparing circuit 162, which outputs a signal when the counted value is smaller than W. The width deciding circuit 16 generates a signal in response to a linear flaw pattern and a dot flaw pattern, and the signal is ceased in case of a dirt pattern. When the counted value is larger than a set value N, a decision on the linear flaw pattern is made, and the decision on the dirt pattern is made by the output of a detecting circuit 17.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、例えば鋼板、アルミニウム板などの被検査物
の表面を検査する表面検査装置に係り、特に被検査物表
面の疵の種類を正確に判定する表面検査装置に関する。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a surface inspection device for inspecting the surface of an object to be inspected, such as a steel plate or an aluminum plate, and in particular, to an apparatus for accurately detecting the types of flaws on the surface of an object to be inspected. The present invention relates to a surface inspection device for making a determination.

〔発明の技術的背景及びその問題点〕[Technical background of the invention and its problems]

従来のこの種の装置は、工業用テレビジョンカメラを用
いて、搬送されてくる被検査物の幅方向一端から他端を
光学的に走査することにより被検査物の表面像を取込ん
だ後、その表面像のアナログ信号を2値化し、さらに幅
方向に分割して量子化データを得る。そして、量子化さ
れた前回データと今回データとを突合せ加算してヒスト
グラムを作成した後、そのヒストグラムを分割区分ごと
に被検査物の一定長について読出し、′″1”の数が連
続して最とも多いものを代表疵と判断し、その代表疵の
幅および面積から疵の種類を判定していた。
Conventional devices of this type use an industrial television camera to optically scan the transported object from one end to the other in the width direction, capturing a surface image of the object. , the analog signal of the surface image is binarized and further divided in the width direction to obtain quantized data. After comparing and adding the quantized previous data and current data to create a histogram, the histogram is read out for a certain length of the inspected object for each division, and the number of consecutive ``1'' is the highest. The type of flaw was determined based on the width and area of the representative flaw.

しかしながら、以上のような疵判定手段は、例えば第2
図(、)のように多数の線状疵の集合した線状疵パター
ン1の場合には第2図(b)に示すヒストグラムの矢印
イを代表疵として評価するので、イ以外の多数の線状疵
は検出できない。
However, the above-described flaw determination means, for example,
In the case of linear flaw pattern 1, which is a collection of many linear flaws as shown in the figure (,), arrow A in the histogram shown in Fig. 2(b) is evaluated as a representative flaw, so many lines other than A are evaluated. No defects can be detected.

また、第4図(、)のように点状疵パターン2の中に1
個の線状疵3が含まれていると、第4図(b)に示すヒ
ストグラムの矢印口を代表疵として評価するので、他の
点状疵参は全く無視されてしまい、疵の種類を正確に判
別できない欠点がある。
In addition, as shown in Figure 4 (,), there is a
If the number of linear flaws 3 is included, the arrow mark in the histogram shown in Fig. 4(b) is evaluated as a representative flaw, so other dot-like flaws are completely ignored, and the type of flaw cannot be determined. There is a drawback that it cannot be accurately determined.

〔発明の目的〕[Purpose of the invention]

本発明は被検査物の疵の種類をオンラインかつリアルタ
イムにより正確に判定する表面検査装置を提供すること
を目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a surface inspection device that accurately determines the type of flaw on an object to be inspected online and in real time.

〔発明の概要〕[Summary of the invention]

本発明は被検査物の一定長についてヒストグラムを作成
し、このヒストグラムを幅方向の分割区分ごとに被検査
物の搬送方向の一定長について高さ判定を行ない、続い
て幅方向の判定を行ない、これら両判定を経て出力され
る信号の分布状態から被検査物の疵の種類を判定する表
面検査装置である。
The present invention creates a histogram for a certain length of the object to be inspected, performs a height judgment on the fixed length of the object to be inspected in the conveyance direction for each divided section in the width direction, and then performs a judgment in the width direction, This is a surface inspection device that determines the type of flaw on the object to be inspected from the distribution state of the signals outputted through both of these determinations.

〔発明の実施例〕[Embodiments of the invention]

第1図は本発明装置の一実施例を示す図である。この装
置は、矢印入方向に搬送される被検査物1ノの幅方向一
端から他端を光学的に走査して被検査物11の表面像を
得る撮像装置12と、この撮像装置12から出力される
表面像のアナログ信号を2値化し、さらに量子化する2
値化−量子化回路13と、この2値化−量子化回路13
によって得られた2値化データをヒストグラム化するヒ
ストグラム作成回路14と、この回路14から読出され
た2値化データの高さおよび幅を判定する高さ判定回路
15および幅判定回路16と、両回路15.16をパス
した信号を計数するピーク数検出回路17と、この回路
17の出力から疵の種類を判定する計算機18とを備え
ている。前記2値化−量子化回路13は、撮像装置12
から出力される表面像のアナログ信号を予め定めたレベ
ルに基づいて波高弁別することにより2値化データを得
るとともに、搬送ラインに設置されたローラ19に連結
されているパルス発生器20からのパルスを受けて被検
査物11の幅方向に適当な画素に分割して量子化するも
のである。次に、ヒストグラム作成回路14は、加算回
路141、メインメモリ142、バッファメモリ143
、ノ臂ルス発生器20からのパルスをカウントするカウ
ンタ144および制御回路145よシなっている。この
加算回路141は被検査物11の幅方向に分割した前回
走査の2値化データと今回走査の2値化データとを分割
区分ごとに突合せ比較して2値化データの積算を行なう
ものであシ、メインメモリ142は被検査物11の幅方
向分割数に相応するクロックCPの入力によって一5− 巡しながら前記加算回路14ノで得た積算データを順次
記憶し被検査物1ノの搬送方向の一定長について積算し
た疵のヒストグラムを作成して記憶する。バッファメモ
リ143は、メインメモリ142のヒストグラムを一時
記憶するとともに、制御回路145からの読出し指令に
基づいて幅方向の分割区分ごとに被検査物11の搬送方
向の一定長についてヒストグラムデータを出力する機能
をもっている。カウンタ144は、被検査物11の搬送
方向の一定長に相応する数だけノ4ルス発生器20から
ノやルスを受けると、制御回路145に信号を与えるも
のである。
FIG. 1 is a diagram showing an embodiment of the apparatus of the present invention. This device includes an imaging device 12 that obtains a surface image of the object 11 by optically scanning the object 1 to be inspected, which is transported in the direction of the arrow, from one end in the width direction to the other end, and an output from the imaging device 12. Binarize and further quantize the analog signal of the surface image
Valueization-quantization circuit 13 and this binarization-quantization circuit 13
A histogram creation circuit 14 that creates a histogram from the binarized data obtained by the above, and a height judgment circuit 15 and a width judgment circuit 16 that judge the height and width of the binarized data read out from this circuit 14. It is provided with a peak number detection circuit 17 that counts signals that have passed through circuits 15 and 16, and a calculator 18 that determines the type of flaw from the output of this circuit 17. The binarization-quantization circuit 13 is connected to the imaging device 12
Binarized data is obtained by discriminating the wave height of the analog signal of the surface image output from the converter based on a predetermined level, and pulses from a pulse generator 20 connected to a roller 19 installed on the conveyance line are obtained. Then, the object to be inspected 11 is divided into appropriate pixels in the width direction and quantized. Next, the histogram creation circuit 14 includes an addition circuit 141, a main memory 142, and a buffer memory 143.
, a counter 144 for counting pulses from the arm pulse generator 20, and a control circuit 145. This adder circuit 141 integrates the binarized data by comparing the binarized data of the previous scan and the binarized data of the current scan, which are divided in the width direction of the object 11 to be inspected, for each division. In addition, the main memory 142 sequentially stores the accumulated data obtained by the adder circuit 14 in one cycle by inputting a clock CP corresponding to the number of divisions in the width direction of the object 11 to be inspected, A histogram of flaws accumulated over a certain length in the conveyance direction is created and stored. The buffer memory 143 has a function of temporarily storing the histogram in the main memory 142 and outputting histogram data for a fixed length in the transport direction of the object to be inspected 11 for each division in the width direction based on a read command from the control circuit 145. have. The counter 144 provides a signal to the control circuit 145 when it receives a number of pulses from the pulse generator 20 corresponding to the fixed length of the object 11 in the transport direction.

前記高さ判定回路15は、バッファメモリ143から読
出されたヒストグラムデータと予め定められた高さ設定
値■とを比較し、高さ設定値Hを越えたヒストグラムデ
ータを出力する比較回路15ノと、この比較回路151
の出力データを前記クロックCPが入力されるごとに出
力するアンドデート152とを備えている。
The height determination circuit 15 includes a comparison circuit 15 which compares the histogram data read from the buffer memory 143 with a predetermined height setting value H, and outputs the histogram data exceeding the height setting value H. , this comparison circuit 151
and an AND date 152 that outputs the output data every time the clock CP is input.

さらに、幅判定回路16はカウンタ161と比6− 較回路162とを有し、アンドダート152から出力さ
れる信号をカウンタ161でカウントして被検査物表面
の疵の幅値を得るとともに、この幅値が例えば幅設定値
W以内のときに比較回路162より信号を出力する。ピ
ーク数検出回路17は、比較回路162から出力される
信号の数をカウントするカウンタ171と、このカウン
タ1710カウント値が設定値N以上であるか否かを判
断する比較回路172とからなっている。
Further, the width determination circuit 16 has a counter 161 and a comparison circuit 162, and counts the signal output from the AND-DART 152 with the counter 161 to obtain the width value of the flaw on the surface of the object to be inspected. When the width value is within the width setting value W, for example, the comparison circuit 162 outputs a signal. The peak number detection circuit 17 includes a counter 171 that counts the number of signals output from the comparison circuit 162, and a comparison circuit 172 that determines whether the count value of this counter 1710 is greater than or equal to a set value N. .

次に、以上のように構成された装置の作用を説明する。Next, the operation of the device configured as above will be explained.

被検査物11Fi搬送ライン上において矢印A方向に搬
送されているが、このとき搬送ライン上に設置されてい
る撮像装置12は被検査物11の表面幅方向一端から他
端を光学的に走査してその被検査物11の表面像を一走
査ごとに取り込んでアナログ信号とし、これを2値化−
量子化回路13へ送出する。この2値化−量子化回路1
3は、撮像装置12から入力される表面像のアナログ信
号を予め定められた設定レベルで比較して2値化すると
ともに、ノ4ルス発生器20から出力されるパルスを受
けて被検査物1ノの幅方向に適当な画素に分割して量子
化し、この量子化された2値化データを加算回路141
へ順次供給する。加算回路141ではメインメモリ14
2から一巡して入力される前回の一走査分の2値化デー
タと2値化−量子化回路13から入力される今回の一走
査分の2値化データとを突合せ加算し、その加算値を後
続のメインメモリ142に格納する。
The object to be inspected 11Fi is being transported in the direction of arrow A on the transport line, and at this time, the imaging device 12 installed on the transport line optically scans the surface of the object to be inspected 11 from one end in the width direction to the other end. The surface image of the object to be inspected 11 is captured every scan, converted into an analog signal, and then converted into a binary signal.
It is sent to the quantization circuit 13. This binarization-quantization circuit 1
3 compares and binarizes the analog signal of the surface image inputted from the imaging device 12 at a predetermined setting level, and also converts the analog signal of the surface image inputted from the imaging device 12 into the inspected object 1 by receiving the pulse outputted from the pulse generator 20. The quantized binary data is divided into appropriate pixels in the width direction of the pixel, and the quantized binary data is added to the adding circuit 141.
sequentially supplied to In the adder circuit 141, the main memory 14
The binarized data for the previous one scan input from 2 and the binarized data for the current one scan input from the binarization-quantization circuit 13 are compared and added, and the added value is calculated. is stored in the subsequent main memory 142.

以上のような信号処理は、被検査物11の搬送方向の一
定長について行ない、第2図6)ないし第4図(b)の
ようなヒストグラムを作成した後、バッファメモリ14
3に移される。この場合、被検査物11の表面に第2図
(a)、第3図(a)、第4図(、)のような線状疵・
母ターン1、汚れ・母ターン4、点状疵ノやターン2が
生じていると、バッファメモリ143には第2図(b)
、第3図(b)、第4図(b)のようにヒストグラム化
されたデータが格納されることになる。
The signal processing as described above is performed for a certain length of the object to be inspected 11 in the transport direction, and after creating histograms as shown in FIG. 2 6) to FIG. 4(b), the buffer memory 14
Moved to 3. In this case, the surface of the object to be inspected 11 has linear flaws and
If there is a mother turn 1, dirt/mother turn 4, spot flaws or turn 2, the buffer memory 143 will have a message as shown in FIG. 2(b).
, FIG. 3(b), and FIG. 4(b), histogram data will be stored.

しかして、被検査物11の搬送方向の一定長に相応する
数の・やルスが・ぐルス発生器20から出力されるとそ
れをカウンタ144がカウントして制御回路145に動
作指令を与える。ここで制御回路145はバッファメモ
リ143のヒストグラムデータを読出し始める。この場
合、被検査物11の幅方向の分割区分ごとに被検査物1
ノの搬送方向の一定長について一定の時間ごとに読み出
される。バッファメモリ143から読み出されたデータ
は高さ判定回路15の比較回路15ノで高さ設定値Hと
比較され、設定値H以上のときだけ比較回路151の出
力端に信号を出力する。このとき、高さ設定値Hとして
、第2図ないし第4図のようにHl又はH。
Thus, when a number of pulses corresponding to a certain length of the object to be inspected 11 in the transport direction are outputted from the pulse generator 20, the counter 144 counts the number and gives an operation command to the control circuit 145. At this point, the control circuit 145 starts reading the histogram data from the buffer memory 143. In this case, the object to be inspected 1 for each division in the width direction of the object to be inspected 11
The data is read out at regular intervals for a constant length in the transport direction. The data read from the buffer memory 143 is compared with the height setting value H in the comparison circuit 15 of the height determination circuit 15, and a signal is outputted to the output terminal of the comparison circuit 151 only when it is equal to or greater than the setting value H. At this time, the height setting value H is set to Hl or H as shown in FIGS. 2 to 4.

の何れか1つ又は連続可変、さらにはHlを持った高さ
判定回路とH2を持った高さ判定回路の両方をヒストグ
ラム作成回路14に接続してもよいものである。
Either one or continuously variable, or furthermore, both the height determination circuit with H1 and the height determination circuit with H2 may be connected to the histogram creation circuit 14.

以下、説明の便宜上、高さ設定値としてH。Hereinafter, for convenience of explanation, H is used as the height setting value.

を用いた場合について説明する。この場合には9− 第2図の線状疵ノ4ターン1のときには比較回路151
からは多数の信号が生じ、第3図の汚れi4ターン4の
ときも同様に多数の信号が生ずる。
We will explain the case using . In this case, 9- When the linear flaw in Fig. 2 is 4 turns 1, the comparator circuit 151
A large number of signals are generated from the turn 4, and a large number of signals are similarly generated at the dirt i4 turn 4 in FIG.

第4図の点状疵パターン2の場合には1個しか信号が生
じない。このようにして比較回路15ノから出力された
信号は高速クロックCPでy−トオンされるアンドダー
ト152を通って幅判定回路16のカウンタ16ノでカ
ウントされる。
In the case of point-like flaw pattern 2 in FIG. 4, only one signal is generated. The signal outputted from the comparison circuit 15 in this manner passes through the AND/DART 152 which is turned on by the high speed clock CP, and is counted by the counter 16 of the width determination circuit 16.

このカウンタ161は例えば比較回路15ノの出力端が
立下ったときにリセットされるようになっている。カウ
ンタ161のカウント値は比較回路162に送られ、こ
こで幅設定値Wと比較され、カウント値が幅設定値W以
内のときに信号が出力される。従って、幅判定回路16
からは線状疵パターン1と点状疵パターン2のときに信
号を生じ、第3図のような汚れパターン4のときには消
去される。このようにして幅判定回路16から出力され
た信号は後続のピーク数検出回路17のカウンタ17ノ
でカウントされるが、更にこのカウント値は設定値Nと
比較10− され、N以上のときには計算機18で線状疵パターン1
であると判定する。仮に、高さ設定値H1の高さ判定回
路15と、幅設定値W以内の信号を出力する幅判定回路
16と、設定値Nの信号を出力するピーク数検出回路1
7とを第1図に付加すれば、これらの回路から出力され
る信号をもって点状疵パターン2と判定することができ
る。更に、幅設定幅Wを大きくし、とのN以上のときに
幅判定回路16から信号を出力するようにすれば、ピー
ク数検出回路17の出力をもって汚れパターンと判定す
ることができる。
This counter 161 is reset, for example, when the output terminal of the comparison circuit 15 falls. The count value of the counter 161 is sent to a comparison circuit 162, where it is compared with the width setting value W, and when the count value is within the width setting value W, a signal is output. Therefore, the width determination circuit 16
A signal is generated when there is a linear flaw pattern 1 and a dotted flaw pattern 2, and it is erased when it is a dirt pattern 4 as shown in FIG. The signal outputted from the width judgment circuit 16 in this way is counted by the counter 17 of the subsequent peak number detection circuit 17, but this count value is further compared with a set value N, and when it is greater than or equal to N, a calculator Linear flaw pattern 1 at 18
It is determined that Suppose that the height judgment circuit 15 has a height setting value H1, the width judgment circuit 16 outputs a signal within the width setting value W, and the peak number detection circuit 1 outputs a signal of a setting value N.
7 to FIG. 1, it is possible to determine the dot pattern 2 based on the signals output from these circuits. Furthermore, if the width setting width W is increased and a signal is output from the width determination circuit 16 when the width is greater than or equal to N, it is possible to determine a dirt pattern based on the output of the peak number detection circuit 17.

〔発明の効果〕〔Effect of the invention〕

以上詳記したように本発明によれば、被検査物の幅方向
表面像を2値化および量子化しかつ被検査物の搬送方向
の一定長についてヒストグラム化したデータを、量子化
の際の分割区分ごとに高さ判定を行ない、さらに幅方向
に生ずるヒストグラムデータの幅判定を行ない、高さお
よび幅判定の結果得られる信号を計数して疵の分布状態
を知るようにしたので、疵の種類を正解にかつオンライ
ン、リアルタイムに判定でき、また線状および点状の度
合を正確に判定できる。
As described in detail above, according to the present invention, the data obtained by binarizing and quantizing the surface image in the width direction of the object to be inspected, and converting it into a histogram for a certain length in the transport direction of the object to be inspected, is divided during quantization. The height is determined for each section, the width of the histogram data generated in the width direction is determined, and the signals obtained as a result of the height and width determination are counted to know the distribution state of the flaw, so the type of flaw can be determined. It is possible to determine the correct answer online and in real time, and it is also possible to accurately determine the degree of linearity and dot-likeness.

また、ピーク数検出回路でピーク数を計数して直ちに判
定の用に供しえるので、高速処理が可能となる表面検査
装置を提供できる。
Furthermore, since the peak number can be counted by the peak number detection circuit and immediately used for determination, a surface inspection apparatus that can perform high-speed processing can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る表面検査装置の一実施例を示す構
成図、第2図ないし第4図は被検査物表面の疵ノ9ター
ンおよびそのヒストグラムを示す図である。 11・・・被検査物、12・・・撮像装置、13・・・
2値化−量子化回路、14・・・ヒストグラム作成回路
、15・・・高さ判定回路、16・・・幅判定回路、1
7・・・ピーク数検出回路。 出願人代理人  弁理士 鈴 江 武 彦第2図   
第3図 第4図 223−
FIG. 1 is a block diagram showing an embodiment of a surface inspection apparatus according to the present invention, and FIGS. 2 to 4 are diagrams showing nine turns of flaws on the surface of an object to be inspected and their histograms. 11... Inspection object, 12... Imaging device, 13...
Binarization-quantization circuit, 14... Histogram creation circuit, 15... Height judgment circuit, 16... Width judgment circuit, 1
7...Peak number detection circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 2
Figure 3 Figure 4 223-

Claims (1)

【特許請求の範囲】[Claims] 搬送されてくる被検査物の幅方向一端から他端を光学的
に走査して被検査物の表面像を得る撮像装置と、この撮
像装置で得た幅方向の表面像のアナログ信号を2値化す
るとともに搬送ラインのローラに連結するパルス発生器
から出力されるパルスを用いて幅方向に分割して量子化
する2値化−量子化回路と、この2値化−量子化回路か
ら出力される前回走査の2値化データと今回走査の2値
化データとを突合せ加算しながら前記被検査物の搬送方
向の一定長についてヒストグラムを作成するヒストグラ
ム作成回路と、この回路のヒストグラムを幅方向の分割
区分ごとに搬送方向の一定長について読出して予め定め
られた高さ設定値と比較しヒストグラムが高いときに信
号を出力する高さ判定回路と、この高さ判定回路から出
力された信号を計数して得た幅値と予め定められた幅設
定値とを比較し幅判定信号を出力する幅判定回路とを備
え、この幅判定回路から出力する信号の数を計数して疵
の種類を判定することを特徴とする表面検査装置。
An imaging device that optically scans the surface image of the object to be inspected by optically scanning it from one end of the object to be inspected in the width direction to the other end, and a binary analog signal of the surface image in the width direction obtained by this imaging device. A binarization-quantization circuit divides and quantizes in the width direction using pulses output from a pulse generator connected to the rollers of the conveyance line, and the output from the binarization-quantization circuit A histogram creation circuit that creates a histogram for a certain length in the transport direction of the object to be inspected by comparing and adding the binarized data of the previous scan and the binarized data of the current scan; A height judgment circuit reads out a certain length in the transport direction for each division, compares it with a predetermined height setting value, and outputs a signal when the histogram is high, and counts the signal output from this height judgment circuit. and a width judgment circuit that compares the obtained width value with a predetermined width setting value and outputs a width judgment signal, and determines the type of flaw by counting the number of signals output from this width judgment circuit. A surface inspection device characterized by:
JP57209047A 1982-11-29 1982-11-29 Surface inspecting device Granted JPS5999238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57209047A JPS5999238A (en) 1982-11-29 1982-11-29 Surface inspecting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57209047A JPS5999238A (en) 1982-11-29 1982-11-29 Surface inspecting device

Publications (2)

Publication Number Publication Date
JPS5999238A true JPS5999238A (en) 1984-06-07
JPH0562293B2 JPH0562293B2 (en) 1993-09-08

Family

ID=16566369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57209047A Granted JPS5999238A (en) 1982-11-29 1982-11-29 Surface inspecting device

Country Status (1)

Country Link
JP (1) JPS5999238A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013002810A (en) * 2011-06-10 2013-01-07 Institute Of National Colleges Of Technology Japan System and method for checking abrasive plane of abrasive tool

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56114747A (en) * 1980-02-14 1981-09-09 Nippon Steel Corp Surface inspection device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56114747A (en) * 1980-02-14 1981-09-09 Nippon Steel Corp Surface inspection device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013002810A (en) * 2011-06-10 2013-01-07 Institute Of National Colleges Of Technology Japan System and method for checking abrasive plane of abrasive tool

Also Published As

Publication number Publication date
JPH0562293B2 (en) 1993-09-08

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