JPS5995702A - Phased array antenna - Google Patents
Phased array antennaInfo
- Publication number
- JPS5995702A JPS5995702A JP20634582A JP20634582A JPS5995702A JP S5995702 A JPS5995702 A JP S5995702A JP 20634582 A JP20634582 A JP 20634582A JP 20634582 A JP20634582 A JP 20634582A JP S5995702 A JPS5995702 A JP S5995702A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- output
- level
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q3/00—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system
- H01Q3/26—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture
- H01Q3/30—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array
- H01Q3/34—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array by electrical means
- H01Q3/36—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array by electrical means with variable phase-shifters
Landscapes
- Variable-Direction Aerials And Aerial Arrays (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はラッチングフェライト移相器（以下移相器と
呼ぶ）を使用したコエイズドアレーアンテナに関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cored array antenna using a latching ferrite phase shifter (hereinafter referred to as a phase shifter).
まず、従来のフエイズドアレーアンテナ装置の駆動回路
におけるパルス幅変換部について説明する。First, a pulse width converter in a drive circuit of a conventional phased array antenna device will be described.
第１図は従来の移相器駆動回路のパルス幅変換部の回路
構成図である。FIG. 1 is a circuit diagram of a pulse width conversion section of a conventional phase shifter drive circuit.
（１）はレジスタ、（２）はＤ／Ａコンバータ、（３）
はＤ／Ａ変換用基準電源、（４）はセット終了用比較器
。(1) is a register, (2) is a D/A converter, (3)
is a reference power supply for D/A conversion, and (4) is a comparator for set completion.
（５）はセット終了用Ｆ／Ｆ回路、（６）は定電流回路
。(5) is a set end F/F circuit, and (6) is a constant current circuit.
（力は積分コンデンサ、（８）はディスチャージ回路。(Power is an integrating capacitor, (8) is a discharge circuit.
（９）はゲ・−ト回路である。 □
第２図は第１図の回路動作を示すタイミングチャートで
ある。(9) is a gate circuit. □ FIG. 2 is a timing chart showing the circuit operation of FIG. 1.
第２図（Ａ）のＬＯＡＤ信号にょシ、移相量に対応する
ディジタル信号Ｓｄを同図（０）に示すようにレジスタ
（１）に取９込む、と同時に同図（Ｂ）に示すようにセ
ット終了用Ｆ／Ｆ回路（５）の可動子を初期状態のＨレ
ベルに設定する。The digital signal Sd corresponding to the phase shift amount of the LOAD signal in Fig. 2 (A) is loaded into the register (1) as shown in Fig. 2 (0), and at the same time, as shown in Fig. 2 (B). The movable element of the F/F circuit (5) for setting completion is set to the initial state H level.
次に、同図（Ｄ）に示すＳＥＴ信号が入力されるとゲー
ト回路（９）は同図（Ｆ）に示すように開き２一方では
定電流回路（６）が起動され、積分コンデンサ（刀には
時間に比例した電荷がチャージされる為、セット終了用
比較器（４）の入力端子（ａ）側には同図（Ｇ）に示す
ようガ
但し、Ｃ４：コンデンサ容量
Ｑｌ：電荷
■、：電流
ｔｌ：時間
なる電圧が発生する。またセット終了用比較器（４）の
他の入力端子（ｂ）側にはディジタル信号ｓｂに対応し
た電圧ＩＥｌｄ’がＤ／Ａコンバータ（２）によりＤ／
Ａ変換されておシ、この両者をセット終了用比較器（４
）で比較し、一致した時点で第２図（Ｂ）で示すように
セット終了用Ｆ／Ｆ回路（５）の出力可を反転させ同図
（Ｆ）で示すようにゲート回路（９）を閉じる。その結
果、ディジタル信号Ｓ（ｌは同図（Ｆ）で示すようにパ
ルス幅に変換されたパルス幅信号ｓＯが出力される。Next, when the SET signal shown in (D) of the same figure is input, the gate circuit (9) opens as shown in (F) of the same figure.2 On the other hand, the constant current circuit (6) is activated, and the integrating capacitor (2) is activated. Since the is charged with an electric charge proportional to time, the input terminal (a) side of the set completion comparator (4) is charged with a charge as shown in the same figure (G). However, C4: capacitor capacity Ql: charge ■, : Current tl: A voltage corresponding to time is generated. Also, on the other input terminal (b) side of the set completion comparator (4), a voltage IEld' corresponding to the digital signal sb is outputted to D by the D/A converter (2). /
A has been converted, and both of these are set to a comparator (4
), and when they match, the output enable of the set end F/F circuit (5) is inverted as shown in Figure 2 (B), and the gate circuit (9) is activated as shown in Figure 2 (F). close. As a result, a pulse width signal sO, in which the digital signal S(l is converted to a pulse width as shown in FIG. 1F), is output.
なお、パルス幅変換稜の積分コンデンサ（７）に蓄積さ
れた電荷は、ディスチャージ回路（８）をＳＥＴ信号の
後縁で起動させることにより行い１次のＳＥＴ信号の前
縁まで動作を続けている。The charge accumulated in the integrating capacitor (7) at the pulse width conversion edge is discharged by activating the discharge circuit (8) at the trailing edge of the SET signal, and the operation continues until the leading edge of the primary SET signal. .
ところが、定電流回路（６）またはティスチャ・−ジ回
路（８）のどちらか一方でも故障した場合、セット終了
用比較器（４）の出力はＬレベルまたはＨレベルに一定
となる為、セット終了用Ｆ′／Ｆ回路（５）の出力可は
反転せず、ＳＥＴ信号がそのままパルス幅信号Ｓ。にな
ってしまう。However, if either the constant current circuit (6) or the gesture circuit (8) fails, the output of the set end comparator (4) will remain constant at L level or H level, so the set will not end. The output of the F'/F circuit (5) is not inverted, and the SET signal remains as the pulse width signal S. Become.
しかも、前述のような故障が生じたか否かの判定は、移
相量に対応するディジタル信号Ｅｌｄを入力し、移相量
に対応した位相が変化するか否かを測定しながら判定し
なければならず、多数の移相器を複数の移相器駆動回路
を用いて制御するようなフエイズドアレーアンテナにお
いては検出が難しいという欠点があった。Moreover, it is necessary to determine whether or not the above-mentioned failure has occurred by inputting the digital signal Eld corresponding to the amount of phase shift and measuring whether or not the phase corresponding to the amount of phase shift changes. Moreover, in a phased array antenna in which a large number of phase shifters are controlled using a plurality of phase shifter drive circuits, detection is difficult.
そこでこの発明は、従来の移相器駆動回路に故障検出機
能を付加し、この欠点を解消するとともに、故障検出時
にはパルス幅信号ＳＯを出力しないようにする機能を備
えたものである。Therefore, the present invention adds a failure detection function to the conventional phase shifter drive circuit to eliminate this drawback and also provides a function of not outputting the pulse width signal SO when a failure is detected.
第３図はこの発明による移相器駆動回路内のパルス幅変
換部の回路構成図である。FIG. 3 is a circuit diagram of a pulse width converter in a phase shifter drive circuit according to the present invention.
（１）はレジスタ、（２）はＤ／ Ａコンバータ、（３
）はＤ／Ａ変換用基準電源、（４）はセット終了用比較
器。(1) is a register, (2) is a D/A converter, (3
) is the reference power supply for D/A conversion, and (4) is the comparator for set completion.
（５）はセット終了用Ｆ ／ Ｆ回路、（６）は定電流
回路。(5) is a set end F/F circuit, and (6) is a constant current circuit.
（７）は積分コンデンサ、（８）はディスチャージ回路
。(7) is an integrating capacitor, and (8) is a discharge circuit.
（９）はゲート回路、Ｃ１はセット開始用比較器、Ｑυ
はセット開始用Ｆ ／ Ｆ回路、（１２はセット開始用
基準電源、Ｕは故障検出用Ｆ／Ｆ回路である。(9) is the gate circuit, C1 is the comparator for starting the set, Qυ
is an F/F circuit for starting a set, (12 is a reference power supply for starting a set, and U is an F/F circuit for detecting a failure.
第４図は、第３図の回路動作が正常な場合のタイミング
チャートを、第５図は第３図の回路動作が異常な場合の
タイミングチャートを示す。FIG. 4 shows a timing chart when the circuit operation shown in FIG. 3 is normal, and FIG. 5 shows a timing chart when the circuit operation shown in FIG. 3 is abnormal.
ただし、第５図の−Ｘ−は定電流回路（６）が故障した
場合を、−・−はディスチャージ回路（８）が故障した
場合を示す。However, -X- in FIG. 5 indicates a case where the constant current circuit (6) has failed, and -.- indicates a case where the discharge circuit (8) has failed.
第４図（Ａ）のＬＯＡＤ信号によ見移相量に対応するデ
ィジタル信号Ｓｄを同図（０）に示すように。The digital signal Sd corresponding to the amount of phase shift determined by the LOAD signal in FIG. 4(A) is as shown in FIG. 4(0).
レジスタ（１）に取り込む、と同時に同図（Ｈ）・（Ｂ
）に示すように、セット開始用Ｆ／Ｆ回路（１１）のＱ
１端子をＬレベルに、セット終了用Ｆ／Ｆ回路（５）の
す端子をＨレベルに初期設定する。(H) and (B) in the same figure.
), the Q of the set start F/F circuit (11)
1 terminal is initially set to L level, and the terminal of the set completion F/F circuit (5) is initially set to H level.
次に同図（Ｄ）に示すＳＥＴ信号によシ定電流回路（６
）が起動され積分コンデンサ（７）には時間に比例した
電荷がチャージされる。ところが、ディスチャージ回路
（８）にはトランジスタが使用されており。Next, the constant current circuit (6
) is activated, and the integrating capacitor (7) is charged with an electric charge proportional to time. However, the discharge circuit (8) uses a transistor.
この）・ランジスタを用いて積分コンデンサ（７）をデ
ィスチャージした場合、トランジスタのコレクターエミ
ッタ間の電圧は０■にならず、コレクターエミッタ間飽
和電圧Ｖｓが残留する。その為、積分コンデンサ（力に
はコレクターエミッタ間飽和電圧ｖ８に相当する電荷が
残留する為、セット開始用比較器Ｑ０の入力端子（ａｌ
）およびセット終了用比較器（４）の入力端子（ａ）側
には、同図（Ｇ、）に示すようなＱ２＋Ｑ２′■２
ｖ ＝ −＝ −ｔ２＋Ｖ８・・・・曲回・曲・
（２）２Ｃ２
但し、Ｃ２：コンデンザ容量
Ｑ２：電荷
Ｑ２′：残留電荷
■２：電流
ｔ２：時間
ＶＢ＝残留電圧
なる電圧が発生する。また、セット開始用比較器００の
他の入力端子（ｂｌ）側のセット開始用基準電源αりは
、前記残留電圧Ｖ８よシ高い電圧■、に設定されておシ
、この両者をセット開始用比較器θ臼で比較し、一致し
た時点で第４図（Ｈ）に示すようにセット開始相Ｆ／Ｆ
回路αυの出力Ｑ１を反転させ同図（Ｌ）で示すように
ゲート回路（９）を開ける、次に。When the integrating capacitor (7) is discharged using this ) transistor, the collector-emitter voltage of the transistor does not become 0■, and the collector-emitter saturation voltage Vs remains. Therefore, since a charge corresponding to the collector-emitter saturation voltage v8 remains in the integrating capacitor (power), the input terminal (al
) and the input terminal (a) side of the set end comparator (4), Q2+Q2'■2 v = -= -t2+V8...... Song times, songs,
(2) 2C2 However, C2: capacitor capacitance Q2: charge Q2': residual charge ■2: current t2: time VB=residual voltage A voltage is generated. In addition, the set start reference power α on the other input terminal (bl) side of the set start comparator 00 is set to a higher voltage than the residual voltage V8. Compare with the comparator θ mill, and when they match, set start phase F/F as shown in Figure 4 (H).
Next, the output Q1 of the circuit αυ is inverted and the gate circuit (9) is opened as shown in (L) in the figure.
セット終了用比較器（４）の他の入力端子（ｂ）側には
ディジタル信号Ｓｄに対応した電圧Ｓｄ’がＤ／Ａコン
バータ（２）により Ｄ ／ Ａ変換されており、これ
と前記■の電圧をセット終了用比較器（４）で比較し。On the other input terminal (b) side of the set end comparator (4), the voltage Sd' corresponding to the digital signal Sd is D/A converted by the D/A converter (2), and this and the Compare the voltages with the set completion comparator (4).
一致した時点で第４図（Ｂ）で示すようにセット終了用
Ｆ／Ｆ回路（５）の出力可を反転させ同図（Ｌ）で示す
ようにゲート回路（９）を閉じる。その結果、ディジタ
ル信号Ｓｄは第４図（Ｌ）に示すようにパルス幅に変換
されたパルス幅信号Ｓｏが出力される。When they match, the output enable of the set termination F/F circuit (5) is inverted as shown in FIG. 4(B), and the gate circuit (9) is closed as shown in FIG. 4(L). As a result, the digital signal Sd is converted into a pulse width signal So as shown in FIG. 4(L).
まだ、故障検出用Ｆ／Ｆ回路α９の出力Ｑ２は。The output Q2 of the failure detection F/F circuit α9 is still.
第４図（Ｈ）のセット開始用Ｆ ／ Ｆ回路αυの出力
Ｑ１を同図（Ｄ）のＳＥＴ信号の後縁で取り返んでいる
ので同図（Ｍ）に示すようにＨレベルのまま変化しない
。Since the output Q1 of the set start F/F circuit αυ in Figure 4 (H) is recovered at the trailing edge of the SET signal in Figure 4 (D), it remains at H level as shown in Figure 4 (M). do not.
なお、パルス幅変換後の積分コンデンサ（７）に蓄積さ
れた電荷は、ディスチャージ回路（８）をＳＥＴ信号の
後縁で起動させることによシ行い２次のＳＥＴ信号の前
線まで動作を続けている。The charge accumulated in the integrating capacitor (7) after pulse width conversion is discharged by activating the discharge circuit (8) at the trailing edge of the SET signal, and continues operating until the front edge of the secondary SET signal. There is.
次に、定電流回路（６）まだはディスチャージ回路（８
）が故障した場合の回路動作を説明する。Next, the constant current circuit (6) and the discharge circuit (8)
) is broken, the circuit operation will be explained.
まず、定電流回路（６）が故障した場合、ＳＥＴ信号が
入力されても定電流回路（６）が動作しない為。First, if the constant current circuit (6) fails, the constant current circuit (6) will not operate even if the SET signal is input.
セット開始用比較器Ｏｅの入力端子（ａｌ）の電圧は第
５図（Ｔ）に示すように他の入力端子（ｂｌ）のセット
開始用基準電源ｕ２の電圧ＶＲ′−ｉで上昇せず、同図
（Ｑ）に示すようにセット開始用比較器任υの出力はＬ
レベルの１１反転しないので、セラ１１始用Ｆ／Ｆ’回
路０υの出力Ｑ１ も同図（Ｎ）に示すようにＬレベル
のままとなＪ、ＳＥＴ信号の後縁で故障検出用Ｆ ／
Ｆ回路ｕ槽の出力Ｑ２は同図（Ｕ）に示すようにＬレベ
ルに反転し、故障信号Ｓ８としてＬレベルが出力される
。まだ、ディスチャージ回路（８）が故障した場合、第
５図（Ｔ）に示すようにセット開始用比較器αυの入力
端子（ａ、）の電圧が他の入力端子（ｂｌ）のセット開
始用基準電源（Ｉりの電圧籾以下に落ちないため、セッ
ト開始用比較器［１１の出力は同図（Ｑ）に示すように
Ｈレベルのままで、ＬレベルからＨレベルに立上らない
ため、セット開始相Ｆ／Ｆ回路ａυの出力Ｑ１ も同図
（Ｎ）に示すようにＬレベルのままとなり、ＳＥ’［’
信号の後縁で故障検出用ｙ／ｙ回路Ｌ３の出力Ｑ２は同
図（Ｕ）に示すようにＬレベルに反転し、定電流回路（
６）が故障した場合と同様に故障信号ＳＥにＬレベルが
出力される。As shown in FIG. 5(T), the voltage at the input terminal (al) of the set start comparator Oe does not rise due to the voltage VR'-i of the set start reference power supply u2 at the other input terminal (bl). As shown in the same figure (Q), the output of the comparator for starting the set is L.
Since the level 11 is not inverted, the output Q1 of the cell 11 starting F/F' circuit 0υ remains at the L level as shown in the same figure (N).
The output Q2 of the F circuit u tank is inverted to the L level as shown in FIG. 3(U), and the L level is output as the failure signal S8. If the discharge circuit (8) still fails, the voltage at the input terminal (a,) of the set start comparator αυ becomes the set start reference for the other input terminal (bl), as shown in FIG. 5 (T). Since the voltage does not drop below the voltage level of the power supply (I), the output of the set start comparator [11 remains at the H level as shown in (Q) in the same figure, and does not rise from the L level to the H level. The output Q1 of the set start phase F/F circuit aυ also remains at the L level as shown in (N) in the same figure, and SE'['
At the trailing edge of the signal, the output Q2 of the failure detection y/y circuit L3 is inverted to the L level as shown in the same figure (U), and the constant current circuit (
6), the L level is output as the failure signal SE.
以上の原理に基づくこの発明による移相器駆動回路を用
いることによシ、定電流回路（６）またはディスチャー
ジ回路（８）の故障時には、ゲート回路（９）はセット
開始相Ｆ／Ｆ回路ａυの出力Ｑ１で閉じられたまま開か
ないのでパルス幅信号Ｓｏは出力されず９回路を保護す
るとともに、故障検出用Ｆ／Ｆ回路α階の出力Ｑ２が反
転し、異常信号８ＫにＬレベルが出力され、自己診断が
可能となる。By using the phase shifter drive circuit according to the present invention based on the above principle, when the constant current circuit (6) or the discharge circuit (8) fails, the gate circuit (9) is activated by the set start phase F/F circuit aυ Since the output Q1 remains closed and does not open, the pulse width signal So is not output and the 9 circuits are protected, and the output Q2 of the failure detection F/F circuit α is inverted, and an L level is output as the abnormal signal 8K. self-diagnosis is possible.
第１図は移相器駆動回路の一部であるパルス幅変換部を
示す図、第２図は第１図のパルス幅変換部のタイミング
チャート図、第３図はこの発明による移相器駆動回路の
一部であるパルス幅変換部を示す図、第４図は第３図の
パルス幅変換部の正常動作時のタイミングチャート図、
第５図は第３図のパルス幅変換部の故障時のタイミング
チャートを示す。
図において、（１）はレジスタ、（２）はＤ／’Ａコン
バータ、（３）はＤ ／Ａ変換用基準電源、（４）は比
較器。
（５）はＤフリップフロップ、（６）は定電流回路、（
力は積分用コンデンサ、（８）はディスチャージ回路、
（９）はＡＮＤ回路、 （ＩＱは比較器、任υはＤフリ
ツプフロツブ、 （１３は基準電源、（Ｌ階はＤフリッ
プフロップである。
なお２図中同一あるいは相当部分には同一符号を付して
示しである。
代理人 葛野信−
第２図
時因
第４図
第５図
胛FIG. 1 is a diagram showing a pulse width converter which is a part of a phase shifter drive circuit, FIG. 2 is a timing chart diagram of the pulse width converter in FIG. 1, and FIG. 3 is a diagram showing a phase shifter drive according to the present invention. A diagram showing a pulse width conversion section which is a part of the circuit, FIG. 4 is a timing chart diagram of the pulse width conversion section in FIG. 3 during normal operation,
FIG. 5 shows a timing chart when the pulse width converter shown in FIG. 3 fails. In the figure, (1) is a register, (2) is a D/'A converter, (3) is a reference power source for D/A conversion, and (4) is a comparator. (5) is a D flip-flop, (6) is a constant current circuit, (
Power is an integrating capacitor, (8) is a discharge circuit,
(9) is an AND circuit, (IQ is a comparator, υ is a D flip-flop, (13 is a reference power supply, (L floor is a D flip-flop. Agent Makoto Kuzuno - Figure 2 Time Cause Figure 4 Figure 5 Yoshi
Claims (1)
能と上記ディジタル信号を所定のパルス幅に変換する機
能とを有する駆動回路と、上記駆動回路により駆動され
る移相器とを備えたフエイズドアレーアンテナにおいて
、５ＥｉＴ信号によシ定電流回路を駆動し、電流と時間
に比例する積分信号を生成し、予め設定されている単信
号と前記積分信号を比較器に入力すると共に、上記積分
信号が上記基準信号の電圧レベルに対して所定の割合に
達した時にゲートを開き、前記ディジタル信号に対応す
る位相制御信号と前記積分信号を他の比較器に入力する
と共に、上記積分信号が上記位相制御信号の電圧レベル
に対して所定の割合に達した時に前記ゲートを閉じ、電
流と時間に比例する出力信号を生成する手段を有し、前
記積分信号が前記基準信号の電圧レベルに達しないか、
前記ＳＥＴ信号以前に前言σ基準信号の電圧レベルを越
えている場合に前記出力信号を出力せず故障信号を出力
するように構成したことを特徴とするフエイズドアレー
アンテナ。A drive circuit having a function of storing a digital signal corresponding to the amount of phase shift of the phase shifter and a function of converting the digital signal into a predetermined pulse width, and a phase shifter driven by the drive circuit. In the phased array antenna, a constant current circuit is driven by the 5EiT signal, an integral signal proportional to current and time is generated, and a preset single signal and the integral signal are input to a comparator, and When the integral signal reaches a predetermined ratio with respect to the voltage level of the reference signal, the gate is opened, and the phase control signal corresponding to the digital signal and the integral signal are input to another comparator, and the integral signal means for closing the gate when the voltage level reaches a predetermined ratio with respect to the voltage level of the phase control signal, and generating an output signal proportional to current and time, wherein the integrated signal reaches a voltage level of the reference signal. Don't you reach it?
A phased array antenna characterized in that, when the voltage level of the σ reference signal is exceeded before the SET signal, the output signal is not outputted and a failure signal is outputted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20634582A JPS5995702A (en) | 1982-11-25 | 1982-11-25 | Phased array antenna |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20634582A JPS5995702A (en) | 1982-11-25 | 1982-11-25 | Phased array antenna |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5995702A true JPS5995702A (en) | 1984-06-01 |
Family
ID=16521760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20634582A Pending JPS5995702A (en) | 1982-11-25 | 1982-11-25 | Phased array antenna |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5995702A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0256102A (en) * | 1988-08-22 | 1990-02-26 | Mitsubishi Electric Corp | Beam controller |
-
1982
- 1982-11-25 JP JP20634582A patent/JPS5995702A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0256102A (en) * | 1988-08-22 | 1990-02-26 | Mitsubishi Electric Corp | Beam controller |
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