JPS5995650A - Arithmetical logical operation unit - Google Patents

Abstract

PURPOSE:To simplify a control signal and to constitute a small-sized integrated circuit by providing a complement processing part and a register which is controlled by an arithmetic control signal in an arithmetical logical operation part, and controlling an internal data type and complement processing. CONSTITUTION:Codes for arithmetic data type control, carry control, and control over the complement processing part are written in a data mode register 5 through an arithmetic control line 5 before the arithmetical logical operation part ALS1 which performs arithmetics of three kinds of data type, i.e. a binary number, binary number with a sign, and complement carries out the arithmetics. The control line 5 is connected directly to the ALS1 and the output of the register 4 is connected to the ALS1 through a data type control line 3. Only one arithmetic control line 5 is provided as an external connection line and no complement processing signal line is provided, so the control signal is simplified to constitute the samll-sized integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to an arithmetic and logic unit (hereinafter referred to as ALU) formed of a semiconductor integrated circuit.

(Prior Art) In recent years, along with advances in integrated circuits, data processing arithmetic units are becoming smaller and smaller. However, the current situation is that further miniaturization is required.

Especially in integrated circuits, wiring occupies a large area.
Reducing wiring is as important as miniaturization.

By the way, in an ALU that performs data operations, complements are usually used to represent negative numbers.

Therefore, conventionally, even if it is known whether or not it is a complement in the arithmetic system, control sounds for both complement processing and arithmetic processing must be performed in separate control units, which is an obstacle to miniaturization. For example, if operations on positive and negative numbers are required, complete complement processing is performed if the operation data is in complement representation before processing the operation, and furthermore, even if operations on a specific data type occur subsequently, It was necessary to give a control signal for complement processing to the ALU each time.

In other words, conventional ALUs have complicated control signals;
Furthermore, when integrated circuits are implemented, the area required for wiring increases, making it difficult to miniaturize.

(Object of the Invention) The object of the present invention is to provide a complement processing unit in the ALU and all registers that can be controlled by arithmetic control signals, and to control the data type and complement processing in the ALU by this register. It is an object of the present invention to provide an ALU that eliminates the drawbacks of the prior art, has simplified control signals, and can be made smaller when integrated into an integrated circuit.

The unit of the present invention includes an arithmetic and logic operation section that performs operations on three types of data: binary numbers, codes (binary numbers, and complements), a complement processing section that performs complement processing on operation data before operations, and an operation control section. It includes a data mode register that controls the operation data type, carry control, and the complement processing section according to signals, and the control mode is written in the data mode register in advance according to the control sequence of the arithmetic and logic operation section, and the arithmetic and logic operation section performs operations. The writing is controlled to be updated every time the type of the data to be written changes.

(Principle and operation of the invention) FIG. 1 is a block diagram showing the basic configuration of the ALU of the invention. 1 is an arithmetic and logical operation f corresponding to a conventional ALU.
Data bus 2 is connected to f1lLs. The arithmetic control line 5 is directly connected to A1.81 and to the input of the data mode register 4, and the output of the data mode shift register 4 is connected to ALS1 by a data type control line 31C. That is, in this configuration, there is only one arithmetic control line 5 as an external control line, and the complement processing control line that is conventionally required is not provided.

Next, the operation of this circuit will be explained. Now, before executing all calculations in ALSI, if the code corresponding to the type of calculation data is placed in the data mode register 4 under control from the control unit (not shown), the same calculation will be performed in the same way. If the data type occurs consecutively, the data type can be determined from the direct data mode register, so there is no need to perform both data calculation and data type control each time as in the past, and it is possible to simply control all calculations. That alone will be a good thing. And if the data types are different, A
The control data in the data mode register may be updated in accordance with the control sequence of LS1.

(Description of Examples) Examples of the invention will now be described in detail with reference to the figures.

FIG. 2 is a block diagram showing one embodiment of the present invention. In this figure, the same reference numerals are used for all the same parts as in the above-mentioned FIG. 1.

In this figure, 1 is ALS, one side of the data bus 2 is directly connected to the input of the multiplexer 7, and the inverter 6
The output of the multiplexer 7 is connected to ALS 1 , and the other end of the data bus 2 is connected to the output of ALS 1 . On the other hand, the arithmetic control line 5 is directly connected to ALSI and also to the input of the data mode register 4I. From the data mode register 4, the data type control line 3 is sent to the multiplexer 7, ALS 1 OLSB (least bit)
K pair f galley power lines 8 are connected to ALS 1, respectively. Here, the inverter 6 and multiplexer 7 constitute the complement processing section.

Next, the operation of this embodiment will be explained.

Now, when performing addition processing on a certain data string,
Assume that there are two types of calculation data: one expressed as a complement (unless otherwise specified, it is a complement of R) and the other. Here, in the data string that we are currently processing, there are various combinations of unsigned binary numbers and unsigned binary numbers, binary numbers and complementary binary numbers, and signed binary numbers and signed binary numbers. It is assumed that control data is written to the data mode register 4 under the control of a control section (not shown).

At this time, a data type control signal is given to the multiplexer 7 through the data type control line 3 from the data mode register 4, and the carry to the LSB of ALSI is controlled by ')-8''x through the carry input line 8. Therefore, addition of each data type can be performed.In other words, when adding an unsigned binary number to an unsigned binary number, the signal of data bus 2 of ALSI is input, and the carry 8' to LSB is input.
This is done by not filling the entire area. The same operation can be used for unsigned binary numbers and complement numbers. In addition, in the case of signed binary numbers and signed binary numbers, the data signal 1ALs is obtained by inverting the data on the data bus 2 other than the sign bit by the multiplexer 7 through the inverter 6 for negative data.
1 and by controlling carry 8'. Furthermore, other data types can be added in the same way. Then, depending on these data types, writing and updating of the control data in the data mode register 4 is controlled by a control unit (not shown, but included in the control unit of ALS 1) according to the control sequence of ALS 1. It will be done.

Thus, according to this embodiment, the control line is the arithmetic control line 5.
Since only one wire is required, the control line is simplified and
Further miniaturization can be achieved when the circuit is integrated.

(Effects of the Invention) As explained in detail above, since the ALU of the present invention has the above-described configuration, it is not necessary to perform external control separately for complement processing control, arithmetic control, and sound as in the conventional case. This has the effect of eliminating this problem and simplifying the calculation to one control line. Furthermore, this effect becomes even more significant in terms of miniaturization of the ALU because the wiring area is reduced when integrated circuits are fabricated.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the basic configuration of the present invention;
The figure is a block diagram showing one embodiment of the present invention.

Claims (1)

[Claims] Binary number, code A: '1' An arithmetic logic operation section that performs operations on three types of data: binary numbers and complements, a complement processing section that performs complement processing on operation data before operation, and an operation control signal. The arithmetic and logic operation section writes all control modes to the data mode register in advance according to the control sequence of the arithmetic and logic operation section. An arithmetic and logic operation unit, characterized in that the arithmetic and logic operation unit is controlled to update the incision every time the type of the data to be operated on changes.