JPS599318Y2 - Display control circuit with zero suppression control function - Google Patents

Description

[Detailed description of the invention] The present invention relates to a display control circuit having a zero suppression control function that can prevent the zero digit at the beginning of the number from being displayed on the display when a number is displayed on the display. be.

When displaying a number on the display, there are cases where a zero is added to the beginning of the number and cases where no zero is added at the beginning of the number.

For example, when showing an amount of money on the display, it is common to display the number by cutting off the leading zero.

When displaying 50,000 yen, r50000J is displayed.

Furthermore, when displaying a simple number, it is common to add a zero at the beginning, such as ro045-012-606459J.

Conventionally, zero suppression control for numerical display in cash dispensers, automatic teller machines, and the like has been executed by a program, which has resulted in an increased burden on the CPU, which has been a problem.

The present invention is based on the above considerations, and aims to provide a display control circuit that can perform zero suppression control for numerical display using a simple circuit structure.

Therefore, the display control circuit of the present invention includes a plurality of digit display means, a plurality of parallel type registers connected in multiple stages, each having a one-to-one correspondence with each of the plurality of digit display means, and each parallel type register. means for supplying a clock to the register; a display data line for supplying display data in a parallel signal format to the display data area of the first-stage parallel register;
a zero detector for detecting whether the display data on the display data line is the number zero; and a zero suppression instruction signal for supplying a zero suppression instruction signal indicating whether zero suppression should be performed or zero suppression should be prohibited. line, the output of the zero detector, and the zero suppression instruction signal are input, and the output of the zero detector indicates that the display data is the number zero, and the output of the zero detector indicates that the display data is the number zero. Control information control means outputs a predetermined value of control information only when the zero suppression finger non-signal indicates zero suppression, and the control information output from the control information control means is used as control information of the first stage parallel register. a signal line that supplies the display data in the display data area of each of the parallel registers to the corresponding display means, and control information of the corresponding parallel register for the display means of the most significant digit. When the control information of the area has a predetermined value, power is not supplied, and when it has another predetermined value, power is supplied, and
For display means other than the most significant digit, when the control information in the control information area of the corresponding parallel type register and the control information in the control information area of the parallel type register corresponding to the higher order display means all have predetermined values. The apparatus is characterized in that it includes a power control section that does not supply power to the control information but supplies power if even one of the pieces of control information does not have a predetermined value.

Hereinafter, the present invention will be explained with reference to the drawings.

The figure is a block diagram showing one embodiment of the present invention.

In the figure, 1 is part of the numeric keypad, 2 is an encoder, 3 is a trigger circuit, 4-1 to 4-n are parallel registers, 5 is a zero detection circuit, 6 is a NAND circuit, and 7-1 to 7-n are Numerical display tube, 8-1 to 8-(n-1) are Tohashi circuits, 9 is an inhibition gate line, 10 is a power supply control section, G to Gn are gate signal lines, D1 to Dn are display data lines, PD is This shows the program data line.

Ten key part 1 allows input of decimal numbers 0 to 9.

Now, if a zero number key is pressed, this number is converted into a binary number by encoder 2 and is stored in the first register of register 4-1.
The number is placed in bit to fourth bit.

The number zero is detected by the zero detection circuit 5, and the zero detection circuit 5 outputs a logic "1".

Zero suppression? When performing control, the prohibition gate line 9 has a logic “
1" is added.

As a result, the NAND circuit 6 outputs the logic r.

The output from this NAND circuit 6 is the fifth one of register 4-1.
Stored in bit position.

Next, when the zero number key is pressed again, the same operation as described above is repeated.

Then, by the shift pulse from the trigger circuit 3,
The contents of register 4-1 are shifted to register 4-2,
Newly input numerical data and zero identification information (logic "0" in this case) are placed in the register 4-1.

That is, the contents of registers 4-1 and 4-2 are both roooo
o”.

Next, when the number 7 key is pressed, the contents of register 4-1 are shifted to register 4-2, the contents of register 4-2 are shifted to register 4-3, and the number 7 is shifted to the first bit of register 4-1. It is stored in the 4th bit to 4th bit.

When the number 7 is inputted by the key, the zero detection circuit outputs the logic “O”.
”, which causes the NAND circuit 6 to output logic “1”.
is output, and the fifth bit of register 4-1 is set to logic “1”.
is stored.

The contents of register 4-1 become rl0111J.

From then on, each time a numeric key is pressed, numeric data and zero identification information are input to register 4-1, and
The contents stored in 4-2 are shifted by one digit.

The registers 4-1 to 4n constitute a shift register as a whole.

As a result, the number "007..." appears in the shift register.
・” is memorized.

The zero identification information of the fifth bit of the registers 4-1 to 4-n is applied to the OR circuit 8 via the gate signal lines G1 to Gn.

In the above example where "007..." is manually input, the signals on the gate signal lines Gn and Gn-1 are logic "0", and the signal on gate signal line Gn-2 is logic "1". ”.

Under this state, power is not supplied to the display tubes 7-n, 7-(n-1), and power is supplied to the display tube 7-(n-2).

Since the OR circuit 8-(n-2) outputs logic "1", power is supplied to all display tubes below the OR circuit 8-(n-2).

Therefore, these display tubes 7-(n-2) to 7-
1 can display display data on display data lines Dn-2 to D1.

Then, the leading “00” is cut off and “7” is displayed on the display.
"..." is displayed.

When logic “0” is added to the inhibit gate line 9, NA
The ND circuit 6 always outputs logic "1", so zero suppression control is not performed.

The program data line is used to flow data sent from, for example, the center CPU.

Data from the center is generally sent with zeros padded at the beginning.

As is clear from the above explanation, the display control circuit of the present invention has a bit for storing zero identification information indicating whether this numerical data is zero or not in a register that stores one-digit numerical data. Therefore, each digit display data and control information corresponding to that digit can be set and read out at once, and the timing control circuit and other circuit structures can be simplified. .

Further, according to the present invention, it is possible to easily specify from the outside whether or not to perform zero suppression, and therefore the display tube can be used for purposes other than displaying amounts.

[Brief explanation of the drawing]

The figure is a block diagram of one embodiment of the present invention. 1... Part of the numeric keypad, 2... Encoder, 3... Trigger circuit, 4-1 to 4-n.
...Register, 5...Zero detection circuit, 6.
...HAND circuit, 7-1 to 7-n...
...Numeric display tube, 8-1 to 8-(n-1)...
...OR circuit, 9...Prohibition gate line, 10...
...Power control unit, G1 to Gn...Gate signal line, D1 to Dn...Display data line, PD
...Program/data line.

Claims (1)

[Scope of utility model registration request] a plurality of digit display means, a plurality of parallel registers connected in multiple stages each having a one-to-one correspondence with each of the plurality of digit display means, and means for supplying a clock to each parallel register; A display data line that supplies display data in a parallel signal format to the display data area of the first-stage parallel register, a zero detector that detects whether the display data on the display data line is the number zero, and a zero detector. A zero suppression instruction signal line that supplies a zero suppression instruction signal indicating whether suppression should be performed or zero suppression should be prohibited, and the output of the zero detector and the zero suppression instruction signal are inputted to the zero detector. control information generating means for outputting control information of a predetermined value only when the output indicates that the display data is the number zero and the zero suppression instruction signal instructs zero suppression; A signal line that supplies the control information to be output to the control information area of the first stage parallel register, a signal line that supplies the display data in the display data area of each of the parallel registers to the corresponding display means, and a display of the least significant digit. For the means, if the control information in the control information area of the corresponding parallel type register has a predetermined value, power is not supplied; if it has another predetermined value, power is supplied and displays other than the most significant digit. Power is supplied to the means when the control information in the control information area of the corresponding parallel type register and the control information in the control information area of the parallel type register corresponding to the higher-order display means all have predetermined values. A display control circuit having a zero suppression control function, comprising: a power supply control section that supplies power if even one of the control information does not have a predetermined value.