JPS5992527A - Pattern for measurement - Google Patents

Pattern for measurement

Info

Publication number
JPS5992527A
JPS5992527A JP57201965A JP20196582A JPS5992527A JP S5992527 A JPS5992527 A JP S5992527A JP 57201965 A JP57201965 A JP 57201965A JP 20196582 A JP20196582 A JP 20196582A JP S5992527 A JPS5992527 A JP S5992527A
Authority
JP
Japan
Prior art keywords
pattern
patterns
measurement
mask
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57201965A
Other languages
Japanese (ja)
Inventor
Nobuyuki Irikita
信行 入来
Hiroshi Maejima
前島 央
Susumu Komoriya
進 小森谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57201965A priority Critical patent/JPS5992527A/en
Publication of JPS5992527A publication Critical patent/JPS5992527A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To perform both measurement inspection and matching inspection using one kind of cell by a method wherein a measurement cell is formed in square framelike shape, and the measurements of the frames are deviated corresponding to the mask so that the frames are formed without overlapping with each other. CONSTITUTION:Measuring patterns 15-17 are formed into square frame shape in such a manner that the center position of each frame will be in coincidence with each other. Also, the length of a side of said frames is to be increased from the pattern 15 toward the pattern 17, and when each of them is printed on the wafer, each of patterns 15A-17A is not overlapped with each other, and they are constituted in such a manner that gaps 18A and 19A are formed between each pattern. The patterns 15A-17A are formed on the patterns 15-17 in such a manner that their lower side will be in parallel with X direction and their right and left sides will be in parallel with Y direction, the outside measurements of the X or Y direction of the patterns 15A-17A are compared with the outside measurements of the patterns 15-17 using a pattern recognition device, thereby enabling to detect the accuracy of measurements.

Description

【発明の詳細な説明】 本発明は半導体装置の製造工程の一つであるホトリソグ
ラフィ工程により形成された素子パターンの検査の容易
化および自動化を図った測定用パターンに関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a measurement pattern that facilitates and automates the inspection of element patterns formed by a photolithography process, which is one of the manufacturing processes of semiconductor devices.

半導体装置の製造に利用されるホトリソグラフィ工程で
は、夫々パターンの異なる複数枚のマスクを半導体ウェ
ー八表面に順序的に焼き付けて所定の素子パターンを得
るようにしている。このため、各マスクの焼付けたパタ
ーンの1つにでも寸法誤差が生じていたり、各マスクの
焼付はパターン間に相対的な位置ずれが生じたりすると
パターン不良が生じ、素子特性のばらつきや不良が発生
する。
In a photolithography process used in the manufacture of semiconductor devices, a plurality of masks each having a different pattern are sequentially printed onto the surface of a semiconductor wafer to obtain a predetermined device pattern. For this reason, if there is a dimensional error in even one of the patterns printed on each mask, or if there is a relative positional shift between the printed patterns on each mask, pattern defects will occur, causing variations in device characteristics and defects. Occur.

したがって従来では各マスクに測定用パターンを設けて
おき、素子パターンの焼付けと同時にとの測定用パター
ンを焼付け、工程の完了後にウェーハ上に形成された測
定用パターンの形状や寸法を測定することにより、各マ
スクのパターン焼付の良否、即ち素子パターンの良否を
検査するようにしている。例えば、第1図はその一例で
あり、2枚のマスク1,2の夫々には略コ字状の寸法測
定セル(パターン)3,4を形成すると共に、一方のマ
スク1には更に方形のポジ型合せ測定セル5を形成し、
かつ他方のマスク2にはこの測定セル5と同心的位置に
それよりも小寸法のネガ型合せ測定セル6を形成する。
Therefore, in the past, a measurement pattern was provided on each mask, the measurement pattern was baked at the same time as the element pattern was baked, and the shape and dimensions of the measurement pattern formed on the wafer were measured after the process was completed. , the quality of the pattern printing of each mask, that is, the quality of the element pattern is inspected. For example, FIG. 1 shows an example of this, in which two masks 1 and 2 are each formed with approximately U-shaped dimension measurement cells (patterns) 3 and 4, and one mask 1 is further formed with rectangular dimension measurement cells (patterns) 3 and 4. Forming a positive type alignment measurement cell 5,
On the other mask 2, a negative-type matching measurement cell 6 smaller in size than the measurement cell 5 is formed concentrically with the measurement cell 5.

そして、これら両マスり1,2を順序的にウェーハ7に
焼き付けて前記各セ/l/3.4,5,6のパターン3
a、 4a* 5ae6a、を形成すれば、その後の検
査工程において、寸法測定セル3,4の各パターン3a
、 4a、の各辺寸法を測定すれば各マスクの焼付寸法
の良否が検査でき、両合せ測定セル5,6によって形成
された方形枠状のパターン5a、5aの枠幅寸法を測定
すれば両マスクの相対位置関係を検査することができる
Then, these two squares 1 and 2 are sequentially printed on the wafer 7 to form the pattern 3 of each cell/l/3.4, 5, and 6.
a, 4a*5ae6a, each pattern 3a of the dimension measurement cells 3, 4 is formed in the subsequent inspection process.
, 4a, the printing dimensions of each mask can be inspected, and by measuring the frame width of the rectangular frame-shaped patterns 5a, 5a formed by the duplex measurement cells 5, 6, it is possible to inspect the printing dimensions of each mask. The relative positional relationship of the masks can be inspected.

しかしながら、このような各セル形状では、寸法検査と
合せ検査とで2種のセルを必要とすると共に、検査工程
においても各セルのパターンを数多く寸法測定しなけれ
ばならず、特にマスク数が多いときにはセルの形成およ
び寸法測定の作業が極めて困難になるという問題が生じ
ている。
However, for each cell shape like this, two types of cells are required for dimension inspection and alignment inspection, and the dimensions of many patterns for each cell must be measured in the inspection process, especially when the number of masks is large. A problem sometimes arises in that the task of cell formation and dimensional measurement becomes extremely difficult.

したがって本発明の目的は1種のセルで寸法検査と合せ
検査を行なうことができ、これによりセルの形成および
寸法測定の作業を極めて容易なものにする測定用パター
ンを提供することにある。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a measurement pattern that allows dimensional inspection and alignment inspection to be performed using one type of cell, thereby making cell formation and dimensional measurement operations extremely easy.

この目的を達成するために本発明は測定セルの形状を方
形の枠状に設定すると共に、その枠が同心的にかつ互に
重ならないように枠寸法を各マスクに応じて異ならせる
ようにしたものである。
In order to achieve this objective, the present invention sets the shape of the measurement cell to be a rectangular frame, and the dimensions of the frame are varied depending on each mask so that the frames are concentric and do not overlap each other. It is something.

以下、本発明を図示の実施例により説明する。Hereinafter, the present invention will be explained with reference to illustrated embodiments.

第2図は本発明の一実施例を模式的に示しており、10
はその表面に所要の素子パターンを形成する半導体ウェ
ーハ、11けこの半導体ウェーハ10にホトリソグラフ
ィ工程によってパターン焼付を行なうマスク群で、本例
では3枚のマスク12.13.14を図示している。こ
れらマスク12゜13.14は夫々透明ガラス基板12
al  13a#14a上に所定の異なるパターン12
b、13b。
FIG. 2 schematically shows an embodiment of the present invention.
1 is a group of masks on which a pattern is printed by a photolithography process on a semiconductor wafer 10 on which a required element pattern is formed on the surface of the semiconductor wafer 10. In this example, three masks 12, 13, and 14 are shown. . These masks 12, 13 and 14 are respectively transparent glass substrates 12.
Predetermined different patterns 12 on al 13a #14a
b, 13b.

14bを形成しており、順序的に使用されて各パターン
12b、13b、14bを半導体ウェーハ10に焼付け
ることは言うまでもない。
14b and are used in sequence to print each pattern 12b, 13b, 14b onto the semiconductor wafer 10.

測定用パターン(セル)は、各マスク12.13゜14
の一部、つまりパターン12a、13a。
The measurement pattern (cell) is 12.13°14 for each mask.
, that is, patterns 12a and 13a.

14aの領域外に設けてあり、各マスク12,13゜1
4の測定用パターン15,16.17はいずれもマスク
の同一位置に形成している。即ち、各測定用パターン1
5.16.17は正方形をした枠状に形成すると共に、
各枠の中心位置が一致されるようにし、かつパターン1
5から17に向かってその一辺長が増大されて夫々をウ
ェーハ上に焼き付けるときには第3図に示すように各パ
ターン15A、16A、17Aは重ならず、各パターン
間に間隙18A、19Aが形成されるように構成してい
る。また、本例では各パターン15,16゜17はネガ
状に形成しておりウェーハ10上にはポジ像を焼付ける
ようにしている。更に、各パターン15,16.17は
その上、下辺を所謂X方向(X走査方向)と平行に、左
、右辺をY方向(X走査方向)と平行になるように形成
している。
It is provided outside the area of 14a, and each mask 12, 13°1
The measurement patterns 15, 16, and 17 of No. 4 are all formed at the same position on the mask. That is, each measurement pattern 1
5.16.17 is formed into a square frame shape, and
Make sure that the center positions of each frame match, and pattern 1
When the side length is increased from 5 to 17 and each pattern is printed on a wafer, the patterns 15A, 16A, and 17A do not overlap as shown in FIG. 3, and gaps 18A and 19A are formed between each pattern. It is configured so that Further, in this example, each pattern 15, 16.degree. 17 is formed in a negative shape, and a positive image is printed on the wafer 10. Further, each of the patterns 15, 16, and 17 is formed so that its lower side is parallel to the so-called X direction (X scanning direction), and its left and right sides are parallel to the Y direction (X scanning direction).

以上の構成によれば、マスク12,13.14を順序的
に用いてホトリソグラフィ工程を進行させ、ウェーハ1
0の表面に所要の素子パターン10aを完成すればこれ
と同時にウェーハ100表面一部には第3図に示す測定
用パターン20が形成される。この測定用パターン20
は大、中。
According to the above configuration, the photolithography process is performed using the masks 12, 13, and 14 in order, and the wafer 1
When the required element pattern 10a is completed on the surface of the wafer 100, a measurement pattern 20 shown in FIG. 3 is simultaneously formed on a part of the surface of the wafer 100. This measurement pattern 20
is large, medium.

小の正方形枠状のパターン15A、16A、17Aを同
心的に配置した形状であることは前述から明らかであり
、各パターン15A、16A、17Aけポジ像として形
成される。
It is clear from the foregoing that the small square frame patterns 15A, 16A, 17A are arranged concentrically, and each pattern 15A, 16A, 17A is formed as a positive image.

そして蛎この測定用パターン2oを用いた検査において
は、例えばレーザ光とCCDを利用したパターン認識装
置を使用し、レーザ光を略パターンの中心を通るように
してX方向、Y方向に夫々1回走査させればよい。との
走査により、第4図に詳細を示すように各パターン15
A、16A。
In the inspection using Hakoko's measurement pattern 2o, for example, a pattern recognition device using a laser beam and a CCD is used, and the laser beam is passed approximately through the center of the pattern, once in the X direction and once in the Y direction. Just scan it. By scanning each pattern 15 as shown in detail in FIG.
A, 16A.

17A(7)枠のX方向、Y方向の外測寸法1x1. 
tyl 。
17A (7) External dimensions of frame in X direction and Y direction: 1x1.
tyl.

lxs 、 lyx、 lxs 、 tysが測定でき
、かつ各パターン間の間隙18A、19AのX方向、Y
方向の寸法tx1.  tyl、  tyl、  tx
4.  t7t、  tyl、tys。
lxs, lyx, lxs, tys can be measured, and the gaps 18A and 19A between each pattern can be measured in the X direction and Y direction.
Dimension in direction tx1. tyl, tyl, tx
4. t7t, tyl, tys.

ty4.が測定できる。したがって、これらの中から外
側寸法ム1.tx2.ム8 * tyl 、 tF! 
、 、lxsをマスク12,13.14に形成したパタ
ーン15゜16.17の外側寸法に対応して比較するこ
とにより、各マスクにより焼付けられた素子パターン夫
々のX方向およびY方向の寸法精度を検出できる。一方
、各間隙18A 、 19Aの対向する寸法txlとt
x2 、  tytとtym、を比較検討すればマスク
12に対するマスク13の相対位置合せが検出でき、同
様に寸法txAとtx4 、  t7sとty4を比較
検討すればマスク13に対するマスク14の相対位置が
検出できる。
ty4. can be measured. Therefore, among these, the outer dimensions 1. tx2. M8 * tyl, tF!
By comparing . Can be detected. On the other hand, the opposing dimensions txl and t of each gap 18A, 19A
By comparing x2, tyt, and tym, the relative alignment of the mask 13 with respect to the mask 12 can be detected, and similarly, by comparing and examining the dimensions txA and tx4, and t7s and ty4, the relative position of the mask 14 with respect to the mask 13 can be detected. .

勿論、各パターン15A、16A、17Aの枠の幅寸法
、内側寸法を測定して寸法精度を検出してもよく、これ
らの値を利用して位置合せを検出するようにしてもよい
Of course, the dimensional accuracy may be detected by measuring the width dimension and inner dimension of the frame of each pattern 15A, 16A, 17A, or alignment may be detected using these values.

ここで、本実施例では各パターン15.16゜17を正
方形の枠状に形成しているが、検査装置における寸法処
理演算の能力によっては相似な長方形の枠状に形成する
ようにしてもよい。
Here, in this embodiment, each pattern 15.16°17 is formed in the shape of a square frame, but it may be formed in the shape of a similar rectangular frame depending on the dimensional processing calculation ability of the inspection device. .

以−ヒのように本発明の測定用パターンによれば、複数
のマスクに形成する測定用パターンを方形の枠状トし、
かつ各マスクのパターンが重ならないように大きさを異
々らせて同心配置しているので、ウェーハ上に形成され
たパターンのX、Y方向61回の寸法測定だけで各マス
クの寸法精度およびマスク相互の相対位置合せを同時に
検査でき、これにより測定用パターンのマスクへの形成
を容易なものにすると共に検査を簡略化しかつ迅速に行
なうことができるという効果を奏する。
As described below, according to the measurement pattern of the present invention, the measurement pattern to be formed on a plurality of masks is formed into a square frame shape,
In addition, since the patterns on each mask are arranged concentrically with different sizes so that they do not overlap, the dimensional accuracy and accuracy of each mask can be determined by measuring the dimensions of the pattern formed on the wafer 61 times in the X and Y directions. The mutual relative positioning of the masks can be inspected at the same time, thereby making it easier to form a measurement pattern on the mask, and having the effect of simplifying and speeding up the inspection.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来パターンを説明するための模式図第2図は
本発明パターンを説明するための模式第3図は測定用パ
ターンの平面図 第4図はその拡大図である。 10・・・ウェーハ、11・・・マスク群、12,13
゜14・・・マスク、15,16.17・・・測定用パ
ターン、15A、16A、17A・・・測定用パターン
の焼付偉、18A、19A・・・間隙、20・・・焼付
けられた測定用パターン。 第  1  図 の。 第  2 図
FIG. 1 is a schematic diagram for explaining a conventional pattern. FIG. 2 is a schematic diagram for explaining a pattern of the present invention. FIG. 3 is a plan view of a measurement pattern. FIG. 4 is an enlarged view thereof. 10... Wafer, 11... Mask group, 12, 13
゜14...Mask, 15, 16.17...Measurement pattern, 15A, 16A, 17A...Measurement pattern baked in, 18A, 19A...Gap, 20...Baked measurement pattern. Figure 1. Figure 2

Claims (1)

【特許請求の範囲】 1、複数枚のマスクを用いてウェーハ上に所要の素子パ
ターンを形成するものにおいて、前記各マスクに形成す
る測定用のパターンを方形の枠状に形成すると共に、各
パターンは互に重ならないように異なる大きさとしかつ
同心位置関係に設定したことを特徴とする測定用パター
ン。 2、各パターンは相似形の方形枠状である特許請求の範
囲第1項記載の測定用パターン。 3、各パターンは正方形の枠状である特許請求の範囲第
2項記載の測定用パターン。
[Claims] 1. In a device in which a plurality of masks are used to form a required element pattern on a wafer, the measurement pattern formed on each mask is formed in the shape of a rectangular frame, and each pattern is A measurement pattern characterized by having different sizes and being set in a concentric position so as not to overlap each other. 2. The measurement pattern according to claim 1, wherein each pattern has a similar rectangular frame shape. 3. The measurement pattern according to claim 2, wherein each pattern has a square frame shape.
JP57201965A 1982-11-19 1982-11-19 Pattern for measurement Pending JPS5992527A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57201965A JPS5992527A (en) 1982-11-19 1982-11-19 Pattern for measurement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57201965A JPS5992527A (en) 1982-11-19 1982-11-19 Pattern for measurement

Publications (1)

Publication Number Publication Date
JPS5992527A true JPS5992527A (en) 1984-05-28

Family

ID=16449693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57201965A Pending JPS5992527A (en) 1982-11-19 1982-11-19 Pattern for measurement

Country Status (1)

Country Link
JP (1) JPS5992527A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0263049A (en) * 1988-08-30 1990-03-02 Dainippon Printing Co Ltd Substrate with mask pattern and its manufacture
JPH05129178A (en) * 1991-10-31 1993-05-25 Toshiba Corp Method for measuring misalignment
US5545593A (en) * 1993-09-30 1996-08-13 Texas Instruments Incorporated Method of aligning layers in an integrated circuit device
US5580829A (en) * 1994-09-30 1996-12-03 Motorola, Inc. Method for minimizing unwanted metallization in periphery die on a multi-site wafer
US6700142B1 (en) 2001-12-31 2004-03-02 Hyperchip Inc. Semiconductor wafer on which is fabricated an integrated circuit including an array of discrete functional modules
JP2011034120A (en) * 2010-11-17 2011-02-17 Renesas Electronics Corp Photomask pair

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0263049A (en) * 1988-08-30 1990-03-02 Dainippon Printing Co Ltd Substrate with mask pattern and its manufacture
JPH05129178A (en) * 1991-10-31 1993-05-25 Toshiba Corp Method for measuring misalignment
US5545593A (en) * 1993-09-30 1996-08-13 Texas Instruments Incorporated Method of aligning layers in an integrated circuit device
US5580829A (en) * 1994-09-30 1996-12-03 Motorola, Inc. Method for minimizing unwanted metallization in periphery die on a multi-site wafer
US6700142B1 (en) 2001-12-31 2004-03-02 Hyperchip Inc. Semiconductor wafer on which is fabricated an integrated circuit including an array of discrete functional modules
JP2011034120A (en) * 2010-11-17 2011-02-17 Renesas Electronics Corp Photomask pair

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