JPS5990293A - Programmable monolithic integrated circuit - Google Patents

Abstract

PURPOSE:To perform normal operation even when a pulse with a steep leading edge or noise is applied by connecting a control circuit to the connection point between the collector of a PNP transistor (TR) and the base of an NPN TR of a PNP circuit. CONSTITUTION:The control circuit is connected to the collectors of PNP TRs Q1-Qm. When writing operation is performed, the circuit 2 is inactivated to perform the writing operation normally. When reading operation is performed, the circuit 2 is activated all the time to hold the collectors of the Q1-Qm almost at the GND level; even when a pulse with a steep leading edge or noise is impressed to an output terminal, a transient current is conducted from the emitters of the Q1-Qm to the bases and this transient current is base currents of the PNP TRs in the activated PNPN circuit, so that the current specified times as great as those of the PNP TRs is conducted to the collectors. The current, however, is conducted to the circuit 2 and never conducted to the bases of NPN TRs Q'1-Q'm, which never turn on. Therefore, the PNPN circuit does not turn on to perform the reading operation normally.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable monolithic integrated circuit in which a write circuit is composed of a PNPN circuit.
This relates to the configuration of the write circuit.

Conventionally, in a programmable read-only memory (hereinafter referred to as FROM) in which the write circuit is composed of a PNPN circuit, the N area of the first PN junction of multiple PNPN circuits can be shared, and the write circuit can be used to write from the write terminal. A voltage clamp circuit (hereinafter abbreviated as trigger circuit) that clamps to a voltage slightly smaller (for example, 26V) compared to the clamp voltage of the PR/OM% included device (for example, 28V) so that the first PN junction turns on when the input current flows. ) must be connected to the N region of the first PN junction, but since the N region is shared by the PNPN circuits as mentioned above, there is no need to provide a trigger circuit for each PNPN circuit, so one It is advantageous and widely used to configure the write circuit with a PN P N circuit. In addition, in the conventional P-40Δ1, in order to save on the number of terminals, the output terminal is also used as the output terminal, and in order to inactivate the output circuit so that the write current does not leak to the output circuit side, it is controlled by the chip enable terminal etc. The method is to do so. Figure 1 shows the conventional write circuit as P N P N
FIG. 2 is a circuit diagram of an example of a junction destruction type P-ROM configured with a circuit. Number of transistors (Qt, Q; ), −,
(Qm, Q=) is Ql and Q'l l...,
Qm and Q'rr constitute a PNPN circuit. Transistor Q11...Qkl...Qlm...
...Qkm is (k×m) memory cell array 3
, where Xl...Xk is a row line, ¥1...
...Yln each indicates a column line. For example, if the row selection circuit 1 selects the row line X1 and the column selection circuit 2 selects the column line ¥1, then the memory cells Qll arranged between these lines is in the selected state, and when a write current flows from the output terminal, it flows from the first PN junction of transistor Q1 to the trigger circuit 4-\, the output terminal reaches the clamp level of the trigger circuit, and when sufficient charge is achieved, the transistor Q , + and Q'l
The N circuit is turned on, the data flows into the memory cell Q11, and data is normally written. If memory cell Qn is selected in the father type and protrusion operation, then Ql,
The PNPN circuit consisting of Q'+ is in a state where it can be activated at any time, and the output terminal is within the logic voltage range (usually 5.5
Since the PNPN circuit operates only at voltages below V), the PNPN circuit can perform a normal read operation without being activated. However, if a steep rising pulse (several ns) or noise is marked on this total 1 output/double composition output terminal and it becomes 0, the N of the first PN connection (I) of the PNPN circuit. The region rises to almost the same potential as the output terminal, and at this time, a transient current it flows from the initial P range of the PNPN circuit to the N region. As mentioned above <PNP
The N region of the first P N junction of the N circuit is shared with the trigger circuit, and the capacitance (hereinafter referred to as C-5ub capacitance) of the N region with respect to the substrate is large, and the The larger the number, that is, the larger the number, the larger the transient current it becomes.

PNPN circuits other than the PNPN circuit composed of Q1+Q'1 are inactivated by the column selection circuit and are not activated, but in the PNI'N circuit composed of Ql and Qr, the transient current i[ 1) The base current of the PNP transistor Q1 becomes the current hte times that of the PNP transistor Q1, and the current flows through the collector of the PNP transistor.
The signal flows into Ba5e of the transistor Q'1, turns on the NPN transistor Q'1, and turns on the PINPN circuit. In the conventional PN PN circuit, when noise with sharply rising pulses is marked 7jD at the output terminal, the PNPN circuit becomes 0.
[7] There is a possibility that the current θi may pass through the memory cell to the row selection circuit, causing a curvature operation.

The first part of this article is to change the writing circuit to PN.
It is an object of the present invention to provide a PNI)N circuit which is capable of operating normally even when a steep rising p pulse or noise is applied to an output terminal in a P-JtOM configured with a PN circuit.

The present invention focuses on the fact that all PN' P N circuits may be inactivated during a read operation, and the PNPN circuit may operate in the same manner as in the prior art during a cage-in operation.

This will be explained with reference to the drawings.

Figure 2 is the PNP of Figure 1) Ranjisk Ql+...
- Shows a configuration in which a control circuit is connected to the collector of Qm. During a write operation, if the control circuit is inactivated, normal writing can be performed as in the conventional case. During read operation, the control circuit is always activated (PNP).
By setting the collectors of z, ..., Qm at approximately the GND level, even if a steeply rising pulse or noise is applied to the output terminal, the transient current
NP) transistor Ql+...Qm flows from the emitter to the base of the transistor, and in the activated PNPN circuit, this transient current it becomes the base current of the PNP transistor, and a current that is times hfe of the PNP) transistor flows to the collector. , this current flows into the control circuit and does not flow into the base of the NPN transistor,
NPN) transistor Q'1. ...-, Q'm is O
Never say N. In other words, the PNPN circuit is never turned on, and a normal read operation can be performed.

A specific example of the present invention will be explained with reference to FIG.

The input terminal that controls the control circuit is the address (Ad
(dress) input terminal and chip enable terminal. During a write operation, the input terminal of the control circuit is at a potential higher than the breakdown of the Zener diode DIO (
For example, by applying 10V), the NPN transistor Q1o turns on, and the NPN transistors Qll, Q12
turns OFF. That is, the control circuit is inactivated during the write operation, and normal writing can be performed as in the conventional case. During read operation, the input terminal of the control circuit is in the logic voltage range (usually -0, 5
v~+5.5v)l, or NPN since it is not applied) transistor Qz.

is OFF, NPN transistors Q 11 and Q 12
is always on and the PNP transistor Qll...
..., since the collector of Qm is kept almost at the GND level at any time, even if a steeply rising pulse or noise is applied to the output terminal, the transient current it is P
NP transistor Ql? ......, flows to the emitter and base of Qm, and in the activated PNPN circuit, this transient current it becomes the base current of the PNP) transistor, and a current that is hfe times that of the PNP) transistor flows to the collector. However, this current flows into NPN transistor Q12, and NPN transistor Q'1.
. . . without supplying current to the base of Q'm) transistor Q'1. ......,Q'
m is never turned on. The fiPNPN circuit is O
A normal read operation can be performed without any error.

FIG. 4 is a specific example showing the second embodiment of the present invention. The control circuit for the gas stove is the same as the circuit proposed as a specific example in Japanese Patent Application No. 144692/1982.

During a read operation, a part of the program power applied to the output terminal is applied to the PNP) transistor Q13 so that the NPN) transistor Q1g is inactive, and during a write operation, a part of the program power applied to the output terminal is applied to the PNP) transistor Q13.
flows to break down diode D2, and NPN
Activate transistors Q 14 and Q xs,
The potential difference of the resistor R3 at that time flowing into the resistors R2 and R3 is the threshold value of the NPN transistor Q1B.
PNP transistor Q13, NPN) transistor Q1
4, Qls, Q16.

Q1? and resistors Rt, R2, R3, R4, R5, diode D2. When D3 is set, NP is set during write operation.
By activating N transistor Q1s and deactivating NPN transistor Q19, a write operation similar to the conventional one can be performed. During read operation, NPN) transistor Q18 is inactivated, NPN) transistor Q19
Even if a steep rising pulse or noise is applied to the output terminal, the transient current it remains PN.
In the activated PNPN circuit, this transient current it flows from the emitter to the base of the PNP) transistor Qt,..., Qm, and becomes the base current of the PNP) transistor. hfe times the current flows to the collector, but this current
19, NPN) transistor Q'1. ...
..., no current is supplied to Ba5e of Q'm, and the NPN transistor Q'1.・・・・・・、Q
'rn, it will never decline. The PNPN circuit can perform normal read operations without being turned on.

As explained above, in a programmable monolithic integrated circuit in which the write circuit is composed of PNPN circuits, by providing a control circuit that simultaneously controls all the PNPN circuits, even if a steeply rising pulse or noise is applied to the output terminal, F ROM for normal read operation
The effects of the present invention are enormous. Note that the write circuit is a fuse type P- which consists of a PNPN circuit.
Even in 40M, by providing the control circuit of the present invention, it is possible to provide a P-ROM that performs a normal read operation even when a steep rising pulse or noise is applied, and it is also suitable for fuse type and junction 2 P-ROM. The present invention can be applied and the effects are enormous.

[Brief explanation of the drawing]

Figure 1 shows a conventional F in which the write circuit is composed of a PNPN circuit.
2 is a diagram for explaining a ROM, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing a specific example of the present invention, and FIG. 4 is a diagram showing a second specific example of the present invention. Qu~Qkm...Memory cell transistor. Agent: Susumu Uchihara, Patent Attorney, District 7, Figure 3

Claims (3)

[Claims] (1) In a programmable monolithic integrated circuit equipped with an electrically writable fixed memory element and a write circuit composed of a PNPN circuit that writes to the fixed memory element, a PNP) transistor and a PNP) transistor are provided. The collector is connected to the base, and the base is connected to the collector of the PNP) transistor.The connection point between the collector of the PNP) transistor and the base of the NPN) transistor of the PNPN circuit is connected to the control circuit. A programmable monolithic integrated circuit. (2) The programmable monolithic integrated circuit according to claim (1), wherein the control circuit is controlled by a terminal other than the terminal that applies programming power to the fixed memory element. (3) The programmable monolithic integrated circuit according to claim (1), wherein the control circuit is controlled by a terminal that applies programming power to the fixed memory element.