JPS5990121A - Power supply circuit - Google Patents

Abstract

PURPOSE:To prevent the breakdown of an element despite the generation of latch-up by avoiding the supply of voltage to a load for a prescribed period of time in case a current larger than the prescribed value flows to the load. CONSTITUTION:A voltage regulator 31 of a voltage control circuit 3 has the drooping characteristics with which the output voltage is set at O when a load current exceeds a prescribed level. An abnormal current detecting circuit 1 detects the voltage drop corresponding to the load current by a resistance 10. When this voltage drop exceeds a prescribed level, a timer circuit 2 is driven for a prescribed period of time. The supply of voltage to a load circuit is discontinued when transistors 33 and 35 are turned on while the circuit 2 is driven, and reinstated after the voltage stop is continued for a prescribed period.

Description

[Detailed Description of the Invention] This invention relates to electronic devices, robot devices, and
This invention relates to a power supply circuit that automatically releases latch-up when a double-up occurs in a circuit used in a machine tool or the like.

In general, C-MO8 elements are widely used in various fields due to their low power consumption, but depending on the usage conditions, latch-up may occur, causing an abnormally large current to flow. Although various preventive measures have been taken to prevent double-up from occurring, it is difficult to completely prevent double-up. For this reason, once latch-up occurs, not only is the C-MO8 element unable to return to normal operation, but the large current that flows at this time often leads to element destruction, so we have developed a method to completely prevent element destruction. I was very hopeful.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a power supply circuit which can save an element from destruction even if latch-up occurs and can restore the element to a normal operating state.

In order to achieve such an object, the present invention completely stops sending the voltage supplied to the load when a current exceeding a predetermined value flows through the load, and restores the voltage supply to the load after releasing the latch-up. This is what I tried to do. The present invention will be described in detail below using drawings showing embodiments.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 is an abnormal current detection circuit that generates a full output signal when the current supplied to the load circuit exceeds a predetermined value;
2 is an output signal that continues for a predetermined time when the input signal is supplied? The generating timer circuit 3 sends an output voltage to the terminal 3b when no signal is supplied to the terminal 3a, and does not send the output voltage to the terminal 3b during the period when the signal is supplied to the terminal 3a. This is a voltage control circuit that looks like this.

Further, 4 is an input terminal, and 5 is an output terminal.

For example, an IC circuit is connected to the output terminal 5 as a load.

The operation of the circuit according to the present invention configured as described above is as follows. If a latch-up occurs for some reason in a normally operating load, the current supplied to the load from the output terminal 5 will drop to the steady-state value IO as shown in Figure 2 (,).
The abnormal value increases rapidly to 1. As a result, the abnormal current detection circuit 1 detects an fc load current abnormality in which the current supplied to the load becomes larger than a predetermined value, and drives the timer circuit 2. The voltage control circuit 3 generates an output signal for a predetermined time T and supplies this output signal to the input terminal 3a of the voltage control circuit 3. During the period when the signal is supplied to the input terminal 3a, the voltage control circuit 3 outputs the output voltage to the terminal 3b. Since the circuit is configured so as not to send out a signal, when a signal is supplied from the timer circuit 2, the output voltage changes from V8 to zero as shown in FIG. 2(C).

As a result, the current supplied from the output terminal 5 to the load is
It becomes zero as shown in Figure (a).

On the other hand, if an IC is used as a load, there is a PN inside it.
A part of the PN structure may be formed, and this f'L
equivalently constitutes a thyristor circuit. There is no problem if this part is applied with the normally used voltage, but if a surge voltage is supplied fL, it may turn on.
However, as mentioned above, the power supply circuit of the present invention has the following problems:
Abnormal current flows through the load f'1. When the output signal is generated, the current supplied to the load becomes zero, so the equivalent silicon risk inside the IC changes from turn on to turn off. Since the output signal stops as shown in FIG. 2(b), at this time the voltage control circuit 3 starts sending out the output voltage vS again as shown in FIG. 2(c). As a result,
However, at this time, the equivalent circuit inside the IC is turned off, so the current flowing to the load has a steady-state value, as shown in Figure 2 (,). It has been restored to 0. Therefore, even if a double-up occurs in the load and a large current flows, the latch-up is canceled by completely stopping the supply of load current for a predetermined period of time, so that the device will not be destroyed.

FIG. 3 is a block diagram showing another embodiment. The same parts as in FIG. 1 are designated by the same symbols. In this embodiment, the output terminals are divided into two, 5a and 5b, so that two types of loads can be connected to them.In this case, the output terminals 5& are constructed with C-MOS elements that are prone to latch-up. The output terminal 5bK is connected to a load that does not cause latch-up. In this way, since the steady-state value of the current fl-7)N flowing through the load composed of 8 C-MO elements is extremely small, the change in current during abnormal and steady states will be extremely large, causing abnormalities. Current detection becomes easier.

FIG. 4 is a circuit diagram showing details of each circuit shown in FIG. 3. In the figure, the abnormal current detection circuit 1 includes resistors 10, 13,
The timer circuit 2 consists of a transistor 11, a diode 12, capacitors 20, 24, resistors 21, 22,
) The voltage control circuit 3 is composed of a voltage regulator 31, resistors 32, 34, and transistors 33, 35. In this case 1. The voltage regulator has a drooping characteristic in which the output voltage becomes zero when the load current exceeds a predetermined value.

Configured like this! 1-, if the load current is at a steady value, the voltage drop across resistor 10 will be small, and if the resistance value of resistor 10 is set so that this voltage drop does not reach the voltage that turns on all transistors 11, then , timer circuit 2 does not operate. However, when the load current becomes abnormally large, the voltage generated across the resistor 10 becomes large and the transistor 11 is turned on. Since the capacitor 20 is charged instantly, the transistor 23 is turned on. As a result, transistors 33 and 35 are also turned on, so the output of voltage regulator 31 is connected to ground by transistor 35.
A large current flows. Since the voltage regulator 31 has a drooping characteristic, the output voltage becomes zero, but the output voltage is zero? Transistor 23 for the time determined by 20 and resistor 21
remains on. As a result, the voltage regulator 31 also remains in a state where the output voltage is zero for this period of time. Note that the capacitor 24 is provided to ensure instantaneous charging of the capacitor 24.

In the circuit shown in FIG. 4, the transistor 11 may be constructed from a differential amplifier when high detection accuracy and stable temperature characteristics are required. Diode 12 charges capacitor 20
t'Lfc is a diode that prevents charge from being discharged through transistor 11.

FIG. 5 is a circuit diagram showing another embodiment, in which the voltage regulator 30 is configured such that when the input terminal 3m is grounded tl,
The operation of the circuit of FIG. 5, which has the characteristic of not generating an output voltage, is similar to the operation of the circuit of FIG. 4.

FIG. 6 is a circuit diagram showing another embodiment, in which a voltage control circuit 40 is composed of a transistor 41, a resistor 42, and a Zener diode 43 that determines the output voltage. In the t'L-fC circuit configured in this way, when the load current becomes larger than a predetermined value and the transistor 11 is turned on, the transistor 23 is turned on and the Zener diode 43 is turned on.
is short-circuited and the transistor 41 is turned off ○ And,
After a time determined by capacitor 20 and resistor 21, transistor 23 is turned off and transistor 41 is turned on.

FIG. 7 is a circuit diagram showing another embodiment, in which the voltage control circuit 50 includes transistors 51, 54, 57 and resistors 52, 55.
, 56, 58, and a Zener diode 53. This circuit consists of a reference voltage and an output voltage by the Zener diode 53? Transistor 54.57
Amplified by a differential amplifier according to the transistor 51
The operation of the circuit is the same as that shown in FIG.

As explained above, the power supply circuit according to the present invention does not supply voltage to the load for a predetermined period of time when a current of a predetermined value and large Cυ flows through the load, so that the load does not suffer from latte-up. When an abnormally large current occurs and an abnormally large current flows,
Immediately, the voltage is no longer supplied to the load, and the latch-up of the load is released, so that even if latch-up occurs, the load will not be destroyed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a waveform diagram of various parts, and FIGS. 3 to 7 are block diagrams and circuit diagrams showing other embodiments. 1... Abnormal current detection circuit, 2... Timer circuit,
3, 30, 40.50φ...Voltage control circuit. -12' Figure 1 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] An abnormal current detection circuit that detects an abnormal load current when the current supplied to the load circuit increases by a predetermined value, and a timer circuit that generates an output signal that continues for a predetermined time when the abnormal current detection circuit detects an abnormal load current. , and a voltage control circuit that stops sending out the output voltage to the load circuit during the period when the output signal is generated from this timer circuit.