JPS5987813A - Epitaxial growth equipment - Google Patents

Epitaxial growth equipment

Info

Publication number
JPS5987813A
JPS5987813A JP19683282A JP19683282A JPS5987813A JP S5987813 A JPS5987813 A JP S5987813A JP 19683282 A JP19683282 A JP 19683282A JP 19683282 A JP19683282 A JP 19683282A JP S5987813 A JPS5987813 A JP S5987813A
Authority
JP
Japan
Prior art keywords
substrate
gas
growth
vapor phase
reaction tube
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19683282A
Other languages
Japanese (ja)
Inventor
Shotaro Umebachi
梅鉢 昭太郎
Yasuhisa Yamashita
泰久 山下
Koichi Konishi
宏一 小西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP19683282A priority Critical patent/JPS5987813A/en
Publication of JPS5987813A publication Critical patent/JPS5987813A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • H01L21/02576N-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To eliminate the time for purge and reduce the contamination during the purge by a method wherein a surface cleaning domain by the vapor phase etching and a vapor phase epitaxial growth domain are provided individually and an entrance, through which a substrate supporting table can be transferred, is provided to a wall separating these domains. CONSTITUTION:Mixed gas of HCl and H2 is introduced into a gas reaction domain 2 of the 1st reaction tube 1 through an inlet 5 and the growth gas, mixture of SiH4, PH3 and H2 is introduced into the gas reaction domain 2' of the 2nd reaction tube 1' through the inlet 5', controlled to a prescribed volume of flow. In the 1st reaction tube 1, the surface of a substrate 3 is etched by 0.1- 1mum in the time tE and then a susceptor 4 is transferred quickly with the substrate 3 into the 2nd reaction tube 1' and N-type Si epitaxial growth whose carrier density is approximately 1X10<16> and thickness is 1-3mum is continued and the flow of the gases SiH4, PH3 and HCl is stopped and the purge is performed by H2 only.

Description

【発明の詳細な説明】 (〕・r−業上の利用分野) 本発明は、結晶成長装置に関し、特に、シラン(sin
)、フォスフイン(PH3)、ジボラン(B2 HI6
)、水素(I■2)、塩化水1()icA)等の気体を
累月として、気相法でかつpt clによって下地表面
の腐食浄化をしだ後、P型或いはN型のシリコンエビタ
キシャ、ル層をSt半フッ9体基板上成長させるのに好
適な構造を有する気相エピタキシャル成長装置に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Use) The present invention relates to a crystal growth apparatus, and in particular, to a crystal growth apparatus.
), phosphine (PH3), diborane (B2 HI6
), hydrogen (I■2), chloride water 1()icA), etc. for several months, and after corrosive purification of the base surface by the gas phase method and ptcl, P-type or N-type silicon Evita is applied. The present invention relates to a vapor phase epitaxial growth apparatus having a structure suitable for growing a crystalline layer on a St semifluorine substrate.

(従来例の構成とその問題点) 一般に気相成長法、とりわけ第1図に示すいわゆる縦型
気相結晶成長装置を用いたエピタキシートル成長では、
反応管1の中でガスを累月としているため成長を制御し
易く、ガス反応領域2.1;地結晶基板(以−ドノt・
板という。);3、同基板を置く支持台すなわちツセプ
タ−4が縦方向温度勾配の中でそれぞれ同一温度域にあ
るので、大きいシセプター4を用いることにより基板:
3を同時に大fil処理しても均一なエビタキンヤル成
長層が得易い特長がある。なお図中5はガス供給孔、6
1d排気孔である。併し乍ら、この気相成長法を工業的
に大耽生産可能にするためには、成長開始時の基板:3
の表面が清浄で均質でなければその目的を達し得ない。
(Structure of conventional example and its problems) In general, epitaxial growth using the vapor phase growth method, especially the so-called vertical vapor phase crystal growth apparatus shown in FIG.
Since the gas is distributed in the reaction tube 1, it is easy to control the growth, and the gas reaction region 2.1;
It's called a board. ); 3. Since the support bases on which the substrate is placed, that is, the receptors 4, are in the same temperature range within the longitudinal temperature gradient, by using the large receptor 4, the substrate:
It has the advantage that it is easy to obtain a uniform Evita kinial growth layer even if 3 is processed at the same time in a large film. Note that 5 in the figure is the gas supply hole, and 6
1d exhaust hole. However, in order to make this vapor phase growth method industrially viable for large-scale production, the substrate at the start of growth: 3
Unless the surface is clean and homogeneous, this objective cannot be achieved.

そこで一般には、成長開始直前に反応管1内で、HCI
Vなどによるいわゆるガスエツチングを施し清浄化が行
なわれる。
Therefore, in general, HCI is added in the reaction tube 1 immediately before the start of growth.
Cleaning is performed by performing so-called gas etching using V or the like.

そのため、従来、気相成長のプロセスは、第2図に示す
ように、ガスエツチング時間tE後KHC6力どのエツ
チングガスを反応管1より除去するいわゆるパージ用の
時間tpを設けて後、成長時間tGO間に気相成長を行
なわせるものである。
Therefore, conventionally, in the vapor phase growth process, as shown in FIG. In the meantime, vapor phase growth is performed.

上記のような時間経緯で行なう従来の気相成長装置に関
する問題点を列挙すると、第1 K −、”ツチングガ
スをパージするだめの時間t、が余分に必要で、総合的
に成長に要する時間が長く力ること。第2に、バー2用
時間tPO間に素4°4ガス中に含捷れる不純物がff
/浄化された基板:$、−L Vi−堆■f1し、再び
基板3をンリし結晶欠陥の発生源となること。第:(に
、反応管]、基板、3、サセプタ−4などが、ガスエツ
チングの際に生成した物質にさらされるため、パージ用
時間t、内に完全に反応管1内から排出されないで再度
基板:3上Vこ堆積すること、などが多くの問題点をも
っている。
Listing the problems with the conventional vapor phase growth apparatus that performs the above-mentioned time course, the first problem is that an extra time t is required for purging the cutting gas, which reduces the overall time required for growth. Apply pressure for a long time.Secondly, impurities contained in the elementary 4°4 gas during the time tPO for bar 2 are ff
/Cleaned substrate: $, -L Vi-deposition f1, and cleans the substrate 3 again, which becomes a source of crystal defects. No. 1: (Reaction tube) Since the substrate, 3, susceptor 4, etc. are exposed to the substances generated during gas etching, they are not completely discharged from the reaction tube 1 within the purging time t, and are reused again. Substrate: There are many problems such as deposition on the substrate.

(発明の目的) 本発明は」二記の問題点を除去し、エピタキシャル成長
時の、特にパージ用時間を削除して総合的な成長時間を
短縮し、パージ中に生ずる汚染を軽減することを目的と
するものである。
(Objective of the Invention) The purpose of the present invention is to eliminate the above-mentioned problems, to shorten the overall growth time by eliminating the purge time during epitaxial growth, and to reduce contamination caused during the purge. That is.

(発明の構成) 本発明は、結晶成長反応(IJ部に、エツチング用尺゛
応管部を基板支持台の移動可能な隔壁を介して連結した
エピタキシャル成長装買で、特に、エツチングと成長が
独立かつ>Qj uQ シフて行なえる」:うにした構
造のものである。すなわち、ガスエツチング専用の反応
管とエピタキシャル゛成長専用の反応管とが接して、そ
の連接部のそれぞれの管壁の一部が開孔されて通用11
となり、この通用1−1で基板支持台が1丁動自在にな
っている。
(Structure of the Invention) The present invention is an epitaxial growth device in which a growth reaction tube for etching is connected to an IJ part via a movable partition wall of a substrate support, and in particular, etching and growth are independent of each other. In other words, the reaction tube dedicated to gas etching and the reaction tube dedicated to epitaxial growth are in contact with each other, and part of the wall of each tube at the connecting portion is is drilled and used 11
In this case, the substrate support stand can move freely in one direction.

本発明装置によれば、それぞれの反応ガスが壁で仕切ら
れ、基板のみを支貧台で動かせるから、基板のエツチン
グ処理と同基板上へのエピタキシャル成長とが迅速に行
なわれる。
According to the apparatus of the present invention, each reaction gas is partitioned by a wall, and only the substrate can be moved on the supporting table, so that etching of the substrate and epitaxial growth on the same substrate can be performed quickly.

(実施例の説明) 第3図は本発明装置の一実施例の概念的構成図であ、す
、1及び1′は第1及び第2の反応管、2及び2′は第
1及び第2のガス反応領域、3は基板、4はザセプター
、5はガス供給孔、6は排気孔、7は壁を示す。
(Explanation of Embodiment) FIG. 3 is a conceptual configuration diagram of an embodiment of the apparatus of the present invention. 1 and 1' are first and second reaction tubes, 2 and 2' are first and second reaction tubes, 2 is a gas reaction area, 3 is a substrate, 4 is a theceptor, 5 is a gas supply hole, 6 is an exhaust hole, and 7 is a wall.

このような構成の結晶成長装置を用いて、N型S1エピ
タキシヤルを成長させる例につき説明する。
An example of growing an N-type S1 epitaxial layer using a crystal growth apparatus having such a configuration will be described.

第1の反応+?21にはII C1及び112の混合ガ
スを、また第2の反応管1′には成長ガスSi H4、
P 113. 、H2の混合ガスをそわぞれ供給孔5及
び5′から所定の流針に制御してガス反応領域2及び2
′に導入する。寸だ、基板3を載せたサセプター4はグ
ララン−カーボン製で、ガスエツチング及びエピタキシ
ャル成長時の各温度は約1050℃とする。
First reaction +? 21 contains a mixed gas of II C1 and 112, and the second reaction tube 1' contains a growth gas of Si H4,
P 113. , H2 is controlled to a predetermined flow needle from the supply holes 5 and 5', respectively, to the gas reaction regions 2 and 2.
' to be introduced. The susceptor 4 on which the substrate 3 is placed is made of gralan-carbon, and the temperature during gas etching and epitaxial growth is approximately 1050°C.

結晶の成長には、捷ずサセプター=1、−t:にキャリ
ーア濃度+018−1020程度の高濃度の砒素(As
 )ドープのN+型Si基板3を載せ、第3図に示すよ
うに所定の位置に置き、H2バージ後、第4図に示すよ
うにエツチング開始と共に第1及び第、2の反応管1及
びビのそれぞれのガス反応領域2及び2′にそれぞれ前
述の気体を導入する。
For crystal growth, a high concentration of arsenic (As
) A doped N+ type Si substrate 3 is mounted and placed in a predetermined position as shown in FIG. 3, and after H2 barging, as shown in FIG. The aforementioned gases are introduced into each of the gas reaction regions 2 and 2'.

第1の反応管1内で、まず基板3の表部を0.1ないし
1μmだけtE時間柄にエツチングして後、サセプター
4を基板;3と共に第2の反応管1′へ速・やかに移動
し、引き続きギヤリア濃度1×1016程度、17さ1
ないし;1ノtmのN型S1エピタキシヤルを・成長し
て5i114. )) II4. n Cl気体の流入
を停止し、112のみでパージする。
In the first reaction tube 1, first, the surface of the substrate 3 is etched by 0.1 to 1 μm in a time pattern of tE, and then the susceptor 4 is quickly transferred together with the substrate 3 to the second reaction tube 1'. , and continue with gear rear concentration of about 1 x 1016, 17 x 1
Or; grow 1 notm N-type S1 epitaxial to 5i114. )) II4. n Stop the inflow of Cl gas and purge only with 112.

このようにして得たN−(N)型Siエピタキシャルウ
ェハを用い、)l−rl常の拡散、イオン注入、写真食
刻などの半導体処理を施してP−N−(N”)型可変容
量ダイオードを製作E7たところ、基板3のキャリア濃
度が極めて高いにもかかわらず、成長N型層への不純物
Asの混入が少なく、ダイオード耐圧は、設計通りジャ
ストパンチスル一時に35Vと高い値となり、しかも、
結晶欠陥などによるキャリアモヒリティの低下もなく高
周波抵抗の極めて低い優れたダイオードが得られた。
Using the N-(N) type Si epitaxial wafer obtained in this way, the semiconductor processing such as ) l-rl normal diffusion, ion implantation, and photoetching was performed to create a P-N-(N'') type variable capacitor. When a diode was fabricated E7, although the carrier concentration of the substrate 3 was extremely high, there was little As impurity mixed into the grown N-type layer, and the diode withstand voltage was as high as 35 V at the time of just punching, as designed. Moreover,
An excellent diode with extremely low high-frequency resistance was obtained without a decrease in carrier mobility due to crystal defects or the like.

(発明の効果) 以上説明したように、本発明はエピタキシャル成長する
に際して、結晶欠陥の抑制、成長層と基板間の不純物分
布の乱れ、いわゆるクロスドープの抑制に優れた効果を
有すると共に、従来装置では省くことのできないエツチ
ング後のパージを実質的に無くすこ、!:になり、成長
時間を短縮する効果も合せ持ち、コ「業的効果も優れて
いる。
(Effects of the Invention) As explained above, the present invention has excellent effects in suppressing crystal defects, disordering the impurity distribution between the growth layer and the substrate, and suppressing so-called cross-doping during epitaxial growth. Virtually eliminates the inevitable purging after etching! : It also has the effect of shortening the growth time, and has excellent karmic effects.

【図面の簡単な説明】[Brief explanation of drawings]

第1 図は従来の縦型気相結晶成長製鎖のtI′り成を
示す図、第2図は第1図の装置における反応気体導入と
時間の関係の説明図、第3図は本発明装置の一実施例の
概念的構成図、第4図は本発明装置による反応気体導入
と時間のryJ係を示1図である。 1.1′・・・ 反応管1.2.2’  ・・・・ガス
反応領域、 :1 ・・・・・基板、 4 ・・・・・
・・サセプター、5 ・・・・・・・・・ガス供給孔、
 6 ・・・・・・排気孔、7 ・・・ 壁。 第1図 第2図 □端P^ 第3図 第4図 □ 峙 h
Fig. 1 is a diagram showing the tI' composition of a conventional vertical vapor phase crystal growth chain, Fig. 2 is an explanatory diagram of the relationship between reaction gas introduction and time in the apparatus of Fig. 1, and Fig. 3 is an illustration of the present invention. FIG. 4 is a conceptual diagram of an embodiment of the apparatus, and is a diagram showing the relationship between introduction of a reaction gas and time by the apparatus of the present invention. 1.1'...Reaction tube 1.2.2'...Gas reaction area, :1...Substrate, 4...
...Susceptor, 5 ...... Gas supply hole,
6...Exhaust hole, 7...Wall. Figure 1 Figure 2 □ End P^ Figure 3 Figure 4 □ Opposite h

Claims (1)

【特許請求の範囲】[Claims] 気相エツチングによる表面浄化領域と、気相エビタキ7
ヤル成長領域とを個別に設け、かつ、とilら内領域を
区切る壁部に基板支持台を可動ならしめる通用口を有し
、前記支持台上の基板の表面浄化と気相エビタギ/ヤル
成長を、前記の表面浄化領域及び気相エビタキ/ヤル成
長領域において個別にかつ時間的に連続して行うことが
できるように構成したことを特徴とするエピタキシャル
成長装置。
Surface purification area by vapor phase etching and vapor phase shrimp 7
In addition, a wall separating the inside area and the inside area has a side opening that allows the substrate support to be movable, and the surface purification of the substrate on the support and the vapor phase epitaxy/yaru growth are performed. An epitaxial growth apparatus characterized in that the epitaxial growth apparatus is configured to be able to perform the following steps individually and temporally continuously in the surface purification region and the vapor phase epitaxy/yarn growth region.
JP19683282A 1982-11-11 1982-11-11 Epitaxial growth equipment Pending JPS5987813A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19683282A JPS5987813A (en) 1982-11-11 1982-11-11 Epitaxial growth equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19683282A JPS5987813A (en) 1982-11-11 1982-11-11 Epitaxial growth equipment

Publications (1)

Publication Number Publication Date
JPS5987813A true JPS5987813A (en) 1984-05-21

Family

ID=16364404

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19683282A Pending JPS5987813A (en) 1982-11-11 1982-11-11 Epitaxial growth equipment

Country Status (1)

Country Link
JP (1) JPS5987813A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62165323A (en) * 1986-01-15 1987-07-21 Canon Inc Device for formation of deposit film
JPS62176134A (en) * 1985-10-11 1987-08-01 アプライド マテリアルズ インコ−ポレ−テツド Materials and method for etching silicide, polycrystalline silicon and polycide
JPH03270126A (en) * 1990-03-20 1991-12-02 Toshiba Corp Method of semiconductor vapor phase growth and device therefor
US20170301536A1 (en) * 2016-04-14 2017-10-19 United Microelectronics Corp. Method for fabricating semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4833150A (en) * 1971-08-28 1973-05-08
JPS4913658U (en) * 1972-05-08 1974-02-05

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4833150A (en) * 1971-08-28 1973-05-08
JPS4913658U (en) * 1972-05-08 1974-02-05

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62176134A (en) * 1985-10-11 1987-08-01 アプライド マテリアルズ インコ−ポレ−テツド Materials and method for etching silicide, polycrystalline silicon and polycide
JPS62165323A (en) * 1986-01-15 1987-07-21 Canon Inc Device for formation of deposit film
JPH03270126A (en) * 1990-03-20 1991-12-02 Toshiba Corp Method of semiconductor vapor phase growth and device therefor
US20170301536A1 (en) * 2016-04-14 2017-10-19 United Microelectronics Corp. Method for fabricating semiconductor device
US10236179B2 (en) * 2016-04-14 2019-03-19 United Microelectronics Corp. Method for fabricating semiconductor device

Similar Documents

Publication Publication Date Title
TWI399795B (en) Method of reducing memory effects in semiconductor epitaxy
DE112007001523T5 (en) Pre-cleaning of substrates in epitaxy chambers
JPS6134928A (en) Growing process of element semiconductor single crystal thin film
KR100434698B1 (en) Method for growing epitaxial layer in semiconductor device
JPH07302760A (en) Selective semiconductor region formation
JPS5987813A (en) Epitaxial growth equipment
JP4490760B2 (en) Semiconductor device manufacturing method and substrate processing apparatus
JPH01134912A (en) Manufacture of semiconductor thin film
JPH0529234A (en) Epitaxial crowing method
JP2987926B2 (en) Vapor growth method
JPH01290221A (en) Semiconductor vapor growth method
JPH0355438B2 (en)
JP3106526B2 (en) Compound semiconductor growth method
KR100249163B1 (en) Forming method of epitaxial layer
JPH04127522A (en) Method for selective growth of semiconductor crystal
JP3112796B2 (en) Chemical vapor deposition method
JPS6235516A (en) Manufacture of semiconductor device
JP2005217375A (en) Method for manufacturing compound semiconductor element
JPH0562916A (en) Vapor growth method
JPS61134014A (en) Vapor growth method for plural mixed crystal iii-v group compound semiconductor
JPH01226791A (en) Molecular beam growth of silicon
JP2006005076A (en) Method of manufacturing group iii-v compound semiconductor
JPH04192323A (en) Manufacture of semiconductor device
JPH04155831A (en) Method of forming phosphorus nitride insulating film
JPH0687459B2 (en) Vapor phase growth equipment