JPS5985152A - Interleaving processing circuit - Google Patents

Abstract

PURPOSE:To attain a stable interleaving processing with less number of RAMs by converting a series input signal into parallel and controlling simultaneously the write and readout of plural different memories to two RAM groups alternately. CONSTITUTION:A time series input signal is converted into three parallel signals at a series-parallel converting circuit 11, an address generated at a write address generating circuit 19 is selected by selecting circuits 23-25, used as a write address and stored in the 1st memory group A comprising RAMs 12-13. The 2nd memory group B reads out the data by a readout address formed by readout address generating circuits 20-22 and selecting circuits 26-28 during the write and outputted via a parallel-series converting circuit 18, then the signal is converted into an interleaved parallel signal in the same speed as the input signal. The address is formed so as to be written and read at the same time to plural different memories in each group.

Description

[Detailed description of the invention]

The present invention is an interleave processing circuit, and more specifically, in order to facilitate the detection and correction of code errors when recording or transmitting digital signals, the order of the bits constituting a code word is changed and other codes are included in the code word. It relates to a processing circuit that interleaves word bit signals. In a high-density magnetic recording device such as a digital video tape recorder (V'J'), code errors occur during reproduction, so correction by code g1 is performed using an error correction code. In addition to random errors caused by scratches, there are also many code errors during playback, as well as so-called burst 1-errors, in which errors are concentrated in one place due to scratches on the tape, etc. In order to have the ability to correct such burst errors, usually
Error correction codes are temporally interleaved to reduce the length of burst errors included in each error correction code. In addition to realizing this interleaving process using shift registers and switches as shown in Figure 1, recently, memory elements such as F'LAM as shown in Figure 2 have been used to achieve this interleaving process. , M), and by controlling the read address from ltAM. However, digital V T I (, etc.)
/sec for equipment that requires high-speed operation.
, AM, there is no R, AM that operates at such high speed, and it is necessary to make AM multiphase and operate at a low speed. . However, even in this case, among the addresses corresponding to two or more different addresses from the same LLAM? Should I avoid reading both files at the same time? ”, and for this reason, the number of phases of RAM is greatly increased, but only one read address! till j
The present invention has the problem of increasing the complexity of the error correction code used in digital V i' It, etc., the number of error correction codes to be interleaved, and An interleaving process with a certain relationship between the number of polymorphisms [1
1! The object of the present invention is to realize the (1) number of It and AM with a small amount and to easily perform 4 inputs to nA IX4 and 7. Light exit side diagonal. To achieve this purpose, we write temporally continuous input signals into multiple access memories by controlling the write and read addresses.
In the interleave processing circuit that performs reading, the processing circuit L is connected to the serial/parallel converter circuit that converts the input signal into a parallel signal and the serial/parallel converter output is connected in a column 11.
1' A first and a second random access memory group which are alternately read and written, connected in parallel to the output of the above-mentioned dumb/dumb access memory group, and converting the parallel output of the above random access memory group into a serial output signal. do, 1
1 serial conversion circuit and the above two memory groups are alternately read and written, and at the time of readout and readout, parallel signals are written to multiple memories in each group at the same time, and The device is equipped with an address control circuit for reading data. According to the interleave processing circuit of the present invention, as will be described in detail in the embodiments below, ``address control is simplified, and in particular, the write and read speeds are equal to the number of phases in the memory group, and the memory is a random access memory. enable the use of Hereinafter, it will be explained in detail using examples. FIG. 8113 is a block diagram of one embodiment of the interleave processing circuit according to the present invention, and FIG. 4 shows a time chart for explaining the operation of the above embodiment and the state of contents recorded in the memory. When a time-series input signal as shown in (a) of FIG.
are converted into three parallel signals of RAM circuits 12 and 13.
．． The data is recorded in the first memory group A consisting of 14 memory cells. The period during which this memory group A is +iL is fLAM15.16
．． The parallel output signals of the second memory group B consisting of 17 are applied to the parallel-to-serial conversion circuit 18, and are converted into interleaved serial signals at the same operating speed as the original input signals and sent out. Here, the number it of RAMs in the memory group, and W,. W2. The following relationship is established between the length and number of pits of the error correction code that is an input signal such as W3 (n1) and the number of words (m) of the error correction code to be interleaved. n-6R+k (jl is any integer) m = 11
R (b is any integer) where k is I (, smaller than k i (mod I also)
choose a different one for all i=1,...■7. For example, if 1t=4, then =1 becomes 1% when i=1, 2 when i=2, 3 when i=3, and 0 when i=4, which satisfy this condition. Also, if = 2, f\Q'' 1, i = 1
．． Or, the value of ki (mod 4) becomes 2 for j4-8 of 3, and this condition is not satisfied. Also, in the case of 1 (-3, this condition is satisfied, so k is 1 or 3
becomes. In the example shown in FIG. 3 above, ■ is also -3, n=7, +11 =
This is the case of 3. Therefore, due to the above relationship, memory group A can be accessed by one thinning operation (FIG. 4(1)).
Each bit information W1. distribution is recorded. What should be noted is that the first bit of each error correction code, which is the input signal, WI□ (the part marked with diagonal lines in Figure 4 (])) is distributed to different AMs and input into the input signal.
The first pin l-W is in the same EL and AM circuits. (Name l

[First bit of H] is never written multiple times. When the write operation is completed, the memory group A changes to a read operation, and the memory group B changes to a write operation similar to the above. In the above embodiment, since n=7.rp=3, the period is 21 bits.The RAM address is determined by the write address generation circuit 19,
Then, the addresses selected by the full address selection circuits 23 to 28 generated by the read address generation circuits 20, 21, and 22 are input. In this case, selection circuits 23 to 25 and selection circuits 26 to 28 are memory group A and memory group I, respectively.
) selects the address corresponding to the operation. On the other hand, the read address generation circuits 20, 21, and 22 have seven It, A-Ml 2 , 1.5, ■ LAMI 3 ,
1. (3. Generate a read address for AMI4゜17. Next, when reading the signal written in memory group AK as described above, as shown in FIG. 4 (1))] from tAM12 to WI I I W321 W23 + ・・・・・・
iLA-Ml3 W2. , W, , , W33
・-, 11, A M 14 Kara is w31°W22,
By controlling the addresses so that Wl3, . . .
A temporally interleaved code can be obtained without reading the contents corresponding to two or more addresses from M at the same time. In addition, in the present invention, since the number of error correction codes for interleaving processing (111) is set to an integral multiple of the phase number of it AM, when reading from ltAM, Wl
,...W W...W...WRl
l a ten N 2R1+
Reading is performed on bare l m-R1-Wm1. And these pairs are all different it A
Since the contents are stored in M, the contents corresponding to two or more addresses will not be read from the same H, AM at the same time. FIG. 4(d) shows the bit structure of a signal read out from the RAM and converted into a serial signal by the parallel/serial conversion circuit 18, that is, an interleaved signal. The above explanation uses a signal consisting of a combination of outputs of dl when writing to a memory group, writing to the same address of multiple memories in each group, and outputs of different memories from multiple memories in each group when reading. This is a case of address control in which . However, as shown in FIG. 4(e), when writing to a memory group, data is written to mutually separate addresses of multiple memories in each group, and when reading, data is written from multiple memories in each group. The same effect can be obtained by using address control in which a signal consisting of a combination of outputs of the same address is read out. FIG. 5 shows an example of a deinterleaving circuit for restoring the output signal of the interleaving processing circuit shown in FIG. 3 to the original signal. This operation is almost the same as that of the interleave circuit, but the difference is that the write address generation circuit 37.
38 and 39, the read address generation circuits 20, 21 . ,
22, and the read address generating circuit 40 generates the same address as the write address generating circuit [9] of the interleave circuit in FIG. 29i-1 serial-parallel conversion circuit, 30-35)t
AM36 is a parallel-to-serial conversion circuit, and 41 to 46 are selection circuits. FIG. 6 shows another embodiment of the interleave processing circuit according to the present invention! FIG. 7 is a diagram showing the W configuration, and FIG. 7 is a time chart diagram for explaining the operation thereof, and a diagram showing the state of recording and reading of the memory. In this embodiment, the bit length n of the t-fold error correction code is selected as an integral multiple of t, and the error correction code is written and read at the same address in a plurality of AMs in one code memory group at once. It is configured as follows. That is, in this actual measurement example, the code sequence after interleaving is different from that shown in FIG. 4(d), and the interleaving process shown in FIG. 7(b) is performed. In this case, as will be described later, the burst length that can be corrected by interleaving is the same in this embodiment as well. On the other hand, in the intersoap processing as in this embodiment, it is possible to write to and read from multiple RAMs at once using the same address, and therefore, address control is easier than in the previous embodiment. It has the advantage of becoming In FIG. 6, parts having the same configuration and operation as those in FIG. 3 are given the same reference numerals and detailed explanations will be omitted. An input signal is added to the serial-to-parallel conversion circuit 11 to be interleaved with WI'JzCm codes of code composition bit number n (n is an integer multiple of t) with a code capable of correcting t-fold errors as shown in FIG. 7(a). It will be done. In this example, t weight is 3, n=9. m-3
This is an example. The input signal is input to the serial-to-parallel converter circuit 11 with an operating speed of 1.
/3; converted into three parallel codes, memory group A, 1
3 inputs. Memory groups A and B have a period of nX+η-2
Write operations and read operations are performed alternately in a 7-bit period, and when one is performing a write operation, the other is performing a read operation. The addresses necessary for writing and reading are as follows: Write address generation 1.
[IIF circuit] 9. The read address generation circuit 7o generates a signal for specifying address A as shown in FIG. 7(C), ((1). The selection circuits 23 and 26 select the address corresponding to the operation (loading, reading) of each memory circuit, and select the addresses from AM12 to I:LA that constitute the memory.
It will be supplied by M17. The codes read from the memory groups A and 13 are converted to the original operating speed by the parallel-to-serial conversion circuit 18, and from the output of the conversion circuit 18, a code subjected to the interleaving process δ is obtained. On the other hand, the deinterleave circuit that converts the interleaved code into the original code converts the tll write address generation circuit 19 of the interleave circuit in FIG. 6 into a read address generation circuit.
This can be realized by replacing the read address generation circuit 20 with a k't'i write address generation circuit. ' Note that error correction codes used in digital VTI (etc.) are often shortened from code length l to code length !l, and in such cases, as in this example, There are almost no inconveniences caused by setting the code length to an integral multiple of the number of errors that can be corrected.In this embodiment, the interleaved codes are generally Wll, Wl, as shown in FIG. 7(1)). ,...
・w , w w , ・,・, w2. ,wm
,,,,,-・WIT,,. II 21+22 w w w w w w w
1++1 1 1142 1 12t +
21+I 1 2++2 La 22+
+...Wm, , one sign of W is ITI
It appears with a period of t. Considering that the burst length that can be corrected by -C by interleaving is a t-fold error correction code, it can be corrected by mt in both the conventional example and the present invention, and there is no difference in this regard. As explained above with reference to the embodiments, the interleave processing J, 74 circuit according to the present invention has an operation speed that is a fraction of that of the memory circuits constituting the memory circuit group, and a plurality of R in each group.
Since it is possible to write and read from AM at the same time, 1. Digital VTI can reduce the number of tAMO and perform stable interleave processing.
Even in devices that require high-speed operation such as
etc., the effect obtained is significant. In addition, many of the error correction codes used in digital V 'I' H, etc. are shortened, and it is possible to select the code length shown in the present invention at the time of shortening. There are almost no inconveniences caused by limiting the code length of the code.

[Brief explanation of the drawing]

1 and 2 are configuration diagrams for explaining a conventional interleave processing circuit, FIGS. 3 and 6 are configuration diagrams of an embodiment of an interleave processing circuit according to the present invention, and FIG. 4 and FIG. 3 and 6 respectively, and FIG. 5 is a schematic diagram of an embodiment of a circuit that performs inverse interleaving processing on the output signal of the interleaving processing circuit of FIG. 3. Q 11.29...Serial to parallel conversion circuit, 12,13゜14.1
5.1G, 17, 30, 31, 32° 33.34.35
... 几AM circuit, 18.36... Parallel-serial conversion circuit,
19.37, 38.39...Write address generation circuit, 20, 2], 22, 40...Read address generation circuit, 23-28.41-46...Address selection circuit. Figure 1 Figure 2 Concave depth 3 Figure 'iJ, i Figure (phantom (b) 1 l shaku AMI 2 area 1 RAMI visit! child 1 eiMv l*, @1 (C) ffAM12th month 1 (4M13...-1°RAM14 Kasumi 1- (d) 4'z cupwsWIWsr 4IL/jWrWm
/3sWuWWW IAU゛(C)

Claims (1)

[Claims] 1. Write a serial input signal into a random access memory by controlling the write and read addresses;
In the interleave processing circuit that performs reading, the processing circuit is connected to a serial-parallel converter circuit that converts the input signal into a parallel signal, and a serial-parallel converter circuit that is connected in parallel to the output of the serial-parallel converter circuit;
first and second random access memory groups that alternately perform reading and writing; a parallel-to-serial conversion circuit that is connected in parallel to the output of the memory group and converts the parallel output of the memory group into a serial signal; An address control circuit is provided for simultaneously writing or reading parallel signals to the serial-to-parallel conversion circuit and reading them to the parallel-to-serial conversion circuit in correspondence to different memories among the plurality of memories in each group. An interleave processing circuit characterized by: 2. In the interleave processing circuit described in paragraph 1, the address control circuit may write or read data to or from the memory group at least one of the memory groups by writing to or reading from the same address of a plurality of memories in each memory group. Interleave processing circuit designed for reading. 3. In the interleave processing circuit described in item 1, the address control circuit prevents writing to the memory group and reading from the memory group from occurring to the same address of a plurality of memories in each group. interleaving processing circuitry configured to perform ingress and egress;