JPS5981928A - Bridge tap equalizing circuit - Google Patents

Abstract

PURPOSE:To facilitate code discrimination if an error is caused by a noise and to minimize the influence of the code error through simple constitution by adding comparators and a simple logical gate. CONSTITUTION:An analog adder AD and a PCM signal discriminating circuit DET are provided between a signal input terminal 1 and a PCM signal discrimination output terminal 2, and a bridge tap equalization control circuit BT is provided in parallel to the circuit DET. This circuit is provided with the 1st comparators 1 and 2 which compare an input VZN with a threshold value Vref and the 2nd comparators COM 3 and 4 which compare an erasure amount signal for erasing a bridge reflected wave from the circuit BT with a threshold value Vref2. Further, digital delay circuits D1 and D2, AND gates AND1-AND3, an OR gate OR, a multiplying circuit MP, etc., are provided. When the comparators COMP 1-4 detect an erasure amount signal Vref2 and VZN<Vref1, the generation of an echo erasure signal after the next one time slot is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bridge tap equalization circuit whose input is a PCM signal using a bipolar code and whose purpose is to eliminate waves reflected by bridge taps.

Generally, when there is a bridge tap with an open end in the middle of the transmission line as shown in Figure 1 fat, the normal received wave PG is reflected on the output side of the transmission line as shown in 11g1lb+. The waveform on which the wave Pr is superimposed is transmitted,
Code errors occur due to reflected waves. A bridge tap equalization circuit eliminates the reflected wave Pr due to such fluctuations and fluctuations, and a configuration as shown in FIG. 2 is known as a conventional circuit.

Here, 1 is a signal input terminal, 2 is a PCM signal identification output terminal, AD is an analog adder, DET is human power ■ 8 is Va≧
When VDET °'+1", VDET < Va < V
When DET, II OII, Va < -VDF, T (1111) is the PCM signal identification circuit that takes advantage of this, and BT is the bridge tap equalizer that detects this magnitude of the bridge tag reflection IE and outputs the reflected wave cancellation signal Vg. @1 circuit, Dl
indicates a digital delay circuit, and MP indicates a multiplication circuit. PCM
The signal identification circuit DET detects whether the signal waveform is "1,1" or "-".
The magnitude of the reflected wave one time slot after the detection of 1'' is detected by the bridge tap equalization control circuit BT, the magnitude is stored in this control circuit BT, and the PCM signal is input to the delay circuit DI. "+1", "-1", "
The identification result of 0''' is entered as 1.The multiplier circuit MP uses the result obtained by multiplying the identification result of one time slot before held in the delay circuit D1 by the magnitude of the reflected wave as a correction pulse, and inputs the result to the analog adder. It is added to AD with the polarity opposite to the reflected wave sign, and the reflected wave is erased.

In the case of the configuration shown in Figure 2, the magnitude of the reflected wave by the bridge tap is the discrimination level VDE in the PCM signal discrimination circuit MDET.
In the case where T is exceeded, if noise is superimposed on the input and a signal that is originally II O7+ is mistakenly identified as It + I II or "11 + 1," as shown in Figure 3, if the original signal is Even if the signal is II OII, the correction pulse alone exceeds the discrimination level ±VDET of the PCM signal discrimination circuit DET, so until the original ", 4-1" or -1" arrives, there will be an error as marked (*) The present invention aims to eliminate this drawback and provide a bridge tap equalization circuit in which the influence of code errors due to noise is minimized.

The present invention will be explained in detail below with reference to the drawings.

FIG. 4 shows an embodiment of the present invention, in which 1 is a signal input terminal;
2 is a PCM signal identification output terminal, 3 to 6 are reference voltage input terminals for conoparator identification, AD is an analog adder, and DE
T is +1'' when the input voltage VIN is the absolute value VDET of the discrimination level, and y, N ≧+VDET '7).

-VDET < VIN < +Vpgr “0”
, VIN≦VDF, P determined as I11# when T
9. CM signal identification (b) path, BT detects the magnitude of the bridge tap reflected wave and outputs the reflected wave cancellation signal V=. Sita, knob equalization control circuit, COMPI~C01t
P4 outputs a high level (H) when the potential of the - input terminal is higher than the potential of the first input terminal, and a low level (L) when the potential of the ten input terminal is lower than the potential of the first input terminal. MP is a multiplication circuit, IJl, 02
is a digital delay circuit, AND1 to AND3 are AND gates, OR is an OR gate, and Nv is an inverter.

In order to operate this, the identification reference voltage outputs (1)reft+±Vref2 of COMPI to COMP4 are set as follows. Since the bridge tap echo has the same polarity as the main signal, if the maximum bridge tap echo amplitude for which the amplitude of the main signal should be compensated by Vps is VBT (MAX), then
In a bipolar code, the received amplitude is smaller than VP by the bridge tap echo, 11 + 1 # or °
'-1'' reception loss width iV+N(+1)l Id VP
VBT (MAX) ≦IV engineering N (+1) ≦Vp (7
) within the range. COMPI.

In COMP2, to detect that the received signal is not ±1", set vref = Vp - VBT (MAX). Set vref2-" VDET.

FIG. 5 shows an operation time chart of the circuit shown in FIG. 4. I
Figure 5 (7) when I OII is being sent continuously.
Input V I N VCP CM in the first time slot
Signal m Separate circuit 1) Positive side identification level at ET + VDE
When noise exceeding T is multiplied by N, it is mistakenly detected as "+1" in that time slot (as shown by the → mark), and therefore, in the next time slot G (time slots 1 and 2), the amplitude VE is output from the multiplier circuit MP. of negative polarity.

An echo cancellation signal vb is output. At this time, IVbl≧
If it is IVDET+, the pcM signal identification circuit DET will erroneously detect -1'' as shown by the zero mark (*).However, when COMP1 to COMP4 are under the conditions shown in Table 1, COMPI'+COMP2 1Vb1≧vnεT even though it is clearly determined to be '0', and a bridge tap echo canceling signal is generated that causes the PCM signal identification circuit DET to mistakenly identify it as '10' or ttll+. Therefore, in the next third time slot, the AND3 output is forcibly set to 0, stopping the generation of the pre-echo cancellation signal and preventing the error from spreading after the third time slot. (- may be either IIH# or 'L'') In the above explanation, the positive discrimination level of the PCM signal discrimination circuit DET +
We explained the operation in the case of noise exceeding VDET, but P
Negative identification level of CM signal identification circuit DET=VDET
Errors can be prevented from spreading in the same manner even when noise exceeds . Furthermore, in the present invention, the case where there is only one bridge tap and only one reflected waveform due to the bridge tap has been described, but the case where there are multiple bridge taps with a similar configuration and multiple reflected waveforms is also applicable. Applicable. In this embodiment, the bridge tap erase signal V exceeds the discrimination level of the PCM signal discrimination circuit DET.
The occurrence of b is detected by two comparators COMP 3 .

Although it was decided to detect it using COMP4, it is also possible to detect it from the control signal of the bridge tap equalization control circuit BT.

As described above, the present invention has the advantage of satisfying the functions of a normal bridge tap equalization circuit and minimizing the influence of code errors even when code errors occur due to noise. Furthermore, since it can be realized by simply adding a comparator and a simple logic gate to a normal bridge tap equalization circuit, it has the advantage of being easily integrated into an integrated circuit.

[Brief explanation of drawings]

Fig. 1 IFLI Ibl is a transmission system diagram and waveform diagram to explain the definition of a bridged tap and reflected waves by the bridged tap, Fig. 2 is a block diagram showing an example of the circuit configuration of a conventional bridged tap equalization circuit, and Fig. 3 2 is a time chart for explaining the operation of the circuit shown in FIG. 2, FIG. 4 is a block diagram showing an embodiment of the present invention, and FIG. 5 is a time chart for explaining the operation of the circuit shown in FIG. 4. . ■... Signal input terminal, 2... PCM signal identification output terminal, 3-6... Reference voltage input terminal for comparator identification, AD... Analog adder, DET...
PCM signal identification circuit, BT... Bridge tap equalization control circuit, DI, D2... Digital delay circuit, MP
...Multiplication circuit, COMPI~COMP4...Comparator, ANDI~AND3...And gate, OR...OR gate, INV...Inverter. 1st Diagram (b) Clearance trajectory 2nd Leap α 3 Diagram time slot, ・, Toneko・1 spin turn +1(“)−1(″)+1(”)−1(
”)+1(ri) Figure 4

Claims (1)

[Claims] An echo cancellation signal in which the input is a PCM signal using a bipolar code, the magnitude of the waveform of the wave reflected by the bridge tap is detected from the waveform of the input, and the sign of the magnitude of the detected bridge tap reflected wave is inverted. In a bridge tap equalization circuit configured to cancel the bridge tap reflected wave by adding the signal to the input signal,
a first comparator that compares the input VIN and the threshold value Vref1; a second comparator that compares the cancellation M2S number vE for canceling the bridge tap reflected wave with the threshold value "refz; According to each output of the comparator, Vg>Vref2 and Vt+v<
A bridge tap equalization circuit comprising: a circuit that stops generation of HIJ echo cancellation information after the next one time slot when detecting that Vref t.