JPS598191A - Delay discharge circuit - Google Patents

Abstract

PURPOSE:To make a delay discharge circuit small-sized, by connecting a PNP transistor (TR), whose emitter is connected to a high potential-side word line, and a multicollector NPN TR, whose one collector is connected to a low potential-side word line, to constitute a PNPN TR. CONSTITUTION:The delay discharge circuit consists of a PNP TR Q1 whose emitter is connected to a high potential-side word line W, a multicollector NPN TR Q2 whose one collector is connected to a low potential-side word line C which makes a pair together with a word line W1, and a constant current source I which flows a current I to the emitter of the TR Q2. Since the collector of the TR Q1 and the base of the TR Q2 are connected commonly and the base of the TR Q1 and the collector of the TR Q2 are connected commonly, a PNPN TR is constituted. Thus, a sufficient delay time is attained, and the occupied area is small because no capacitors and high resistances are used.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a delayed discharge circuit that quickly lowers the word line potential of a static memory upon transition to non-selection.

Technical Background In memory ICs that use saturated cells such as PNPN memory (C and I2L memory ICs), it is important to quickly lower the potential of a selected word line when it becomes unselected to prevent multiple selections. For this purpose, a discharge circuit is provided for the word line, but this circuit continues to operate for a certain period of time (generally 5 to 10 n5ec) even after the output of the word line driver that drives (selects) the word line switches to the non-selection level. It is necessary to be a delay type that continues to discharge the charges on the selected word line.

Conventional technology and problems In conventional delayed discharge circuits, the discharge time constant (delay time) is generally determined by a capacitor and a resistor. This has the disadvantage that the entire discharge circuit occupies a large area.

OBJECTS OF THE INVENTION The present invention uses elements of PNPN structure in the discharge circuit for each word line to enable delayed discharge and to reduce the overall occupied area.

Structure of the Invention The present invention is a delayed discharge circuit connected to a word line pair to which a static memory cell is connected, and forcibly lowering the potential of the word line when the word line pair is transitioned from selection to non-selection. PNP whose emitter is connected to the high potential side word line via a level shift element) run risk,
The PNP) run risk has its base and first collector connected to the collector and base of the run risk, respectively, and the second collector or second emitter is connected to the low potential side word line, and the NPN) run risk. It is characterized by comprising a constant current source or a constant voltage source connected to the emitter of the word line to cause a word line discharge current to flow through the l-run risk, which will be explained in detail below with reference to the drawings.

Embodiment of the invention FIG. 1 (al is the basic configuration of the delayed discharge circuit of the invention, Q
; is a PNP whose emitter is connected to the positive side (high potential side) word line W! - The transistor Q2 is a multi-collector type NPN whose one collector is connected to the negative side (low potential side) word line C that pairs with the word line W.) Run risk, ■ is the current 1 at the emitter of the transistor Q2. It is a constant current source that causes a current to flow.

The collector of transistor Q1 and the base of transistor Q2 (both P type) are connected in common, and the base of transistor Q1 and the remaining collector of transistor Q2 (
Since both N-type devices are connected in common, the element structure is PNPN like Cyrisk. The same figure (bl shows this, 2 is the emitter of the transistor Q1, 3 is the base of the same transistor and the collector of the transistor Q2, 4 is the collector of the transistor Q1 and the base of the transistor Q2, and 5 is the emitter of the transistor Q2. Yes, Cylisk will not turn on unless it is triggered, but
The DC characteristics of the SIRISK formed by an integrated circuit are equivalent to the diode 6 shown in FIG. 1(C). This is because when current is flowing, the PNP transistor Q
1 and the NPN l-run risk Q2 are saturated and all three junctions are forward biased. Note that two transistors Q + are required to obtain current-voltage characteristics equivalent to the diode 6.

The parameter of Q2 must be controlled to an appropriate value, but this is very easy. The present invention utilizes this saturation characteristic. As is generally known, the collector-emitter junction capacitance of a saturated transistor becomes very large due to the diffusion capacitance component, and there is a large amount of accumulated charge. This means that conventional capacitors can be made smaller. The present invention also takes advantage of this point.

FIG. 2 is a diagram showing an embodiment of the present invention, and 71 to 7n are delayed discharge circuits (elements) provided for each word line, WD+
~WDn are word line drivers, and MC1~MCn are saturated memory cells. PNP of discharge circuit 1+~1n)
Run risks Q1 to Q1n correspond to QI in FIG. 1, and NPN transistors Q,1 to Q2n correspond to Q2. Constant current source 1 is provided in common, and transistor Q21
The emitters of ~Q 2 n are connected in common (forming a current switch). R1-Rn are word lines W I-
This is a level shift or voltage drop resistor inserted between W n and the emitter of the transistor Q+'+ -Q + n. Memory cells MC (MC+, MC2...
. . . (hereinafter the same shall apply) takes the configuration shown in FIG. In the same figure, Q3. Q4 is a PNP that becomes a load.
Transistor, Q5. Q6 is a driving NPN transistor (multi-emitter), and B and B are a bit line pair.

Now, the selection signal
1) is in a non-selected state at a low potential (for example, -1.9V). The current l of the constant current source 1 flows only through the discharge circuit 71 connected to the word line W1 having the highest potential. In other words, when the potential of the word line W1 is high, first the transistor Q1
A current flows between the emitter and base of the transistor 1, which becomes the base current of the transistor, and the collector current flows. This collector current becomes the base current of transistor Q21, and the base current of Q,1 becomes the collector current of C21, turning on transistor Q21. This turns on the PNPN structure from the emitter of transistor Q,1 to the emitter of transistor Q21. At this time, transistors Q, 1, and C21 are deeply saturated, and the base potential of C21 becomes approximately equal to the emitter potential of Qll (the same potential is shown in the figure).

Also, since C21 is a multi-collector transistor,
A certain proportion (eg 80%) of the drawn current (1) flows from the second collector. For example R=1.5
KΩ, 0.4 m from the emitter of Q, 1
A. It will flow. Note that at this time, the discharge circuit (for example, ?n) connected to the non-selected row is also in the on state. That is, since the discharge circuit 7n is connected to a word line with a low potential, no discharge current flows, so the emitter potential of Qln is approximately equal to the potential of Wn (-1.9V). Further, the potential of the second collector of C2n is equal to the potential of Cn (-2, TV). Therefore, the second collector of C2n acts as an emitter and connects P from the emitter of Qln to the second collector of C2n.
NPN will be turned on. However, the PNPN structure of the thread path from the emitters of Q and n to the emitter of C2n is off. Here, driver 1 transistor W of selection column W1
The potential of the base (Xl) of D+ is the selection potential (-0, IV)
Let us consider the case where the voltage is switched from to the non-selection potential (-1, IV).

FIG. 4 is a conceptual diagram showing fluctuations in word line potential and discharge current. As described above, the transistor Q11°C2 is saturated and there is a delay in the fluctuation of the base potential, so that the discharge current I continues to flow for a certain delay time. In this way, even after the word line WI transitions to non-selection, the discharge continues,
The residual charges accumulated in the word lines W, C and the memory cell portion are forcibly removed, and the word lines descend steeply to prevent two-electrode selection.

In addition, the resistor RI''Rn serves to lower the level of the discharge circuit connected to the selected row.
The collector of will be fully forward biased, and the discharge current will be mainly W1. It flows along the path Q, , and the discharge current of the cell disappears.

In Figure 5, the resistors R1-Rn in Figure 4 are replaced with diodes D.
1 to Dn. This is an example modified by focusing on the point that a resistance is necessary for level shift. However, in this case, the PNPN is completely turned off when not selected.

Figure 6 shows that the basic circuit in Figure 1 is a multi-collector NPN
-Tr is used, whereas multi-emitter NPN-Tr is used.
This is an example using . In this case, when selected, the second emitter operates in reverse and acts as a collector. Furthermore, by changing the current amplification factors of the two emitters, it is also possible to control the current drawn from the negative side word line. In this case, the operating principle of the circuit is the same as the circuit of FIG. Note that in either example, the constant current source 1 may be a constant voltage source.

Effects of the Invention As described above, according to the present invention, there is no need to use a capacitor or a high resistance, so the area occupied by the delayed discharge circuit can be small. Furthermore, when used in a PNPN memory with the equivalent circuit shown in FIG. 6, the structure is the same as that of a memory cell, so manufacturing is simple, and there is also the advantage that the time constant changes automatically according to the memory cell capacity.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing the basic configuration of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a circuit diagram showing an example of a saturation type memory cell, and Fig. 4 is a delayed discharge diagram. FIG. 5 is a waveform diagram showing characteristics, FIG. 5 is a block diagram showing another embodiment of the present invention, and FIG. 6 is a block diagram showing another embodiment of the present invention. In the figure, W1 to Wn are positive word lines, C1 to Cn are negative word lines, MC+ to MCn are memory cells, and Qll"
Q In is PNPI-run lister, C2, ~Q 2
n is NPN l-run lister, R+~Rn, D+~Dn
1 is a level shift element, 2 is a constant current source, and 71 to 7n are delayed discharge circuit elements. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi Figure 1 Figure 2 Figure 1 Figure 4 Figure 5

Claims (1)

[Claims] A delayed discharge circuit that is connected to a word line pair to which a static memory cell is connected, and that lowers the potential of the word line in small steps when the word line pair is transitioned from selection to non-selection, and is connected to a high potential side. A PNP l-transistor whose emitter is connected to the word line via a level shift element, the PNP
) NPN whose base and first collector are connected to the collector and base of the transistor, respectively, and whose second collector or second emitter is connected to the low potential side word line.
1. A word line delayed discharge circuit comprising: a transistor; and a constant current source or constant voltage source connected to the emitter of the N P N' transistor to cause a word line discharge current to flow through the transistor.