JPS598033A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS598033A JPS598033A JP11543782A JP11543782A JPS598033A JP S598033 A JPS598033 A JP S598033A JP 11543782 A JP11543782 A JP 11543782A JP 11543782 A JP11543782 A JP 11543782A JP S598033 A JPS598033 A JP S598033A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- semiconductor integrated
- integrated circuit
- comparator
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Liquid Crystal (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、太陽電池で駆動される半導体集積回路装置
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device driven by a solar cell.
従来より、第1図に示すように、太@亀池で駆動される
電子式卓上計算機が公知である。この電子式卓上計算機
では、太陽電池Eから供給される電圧が、その入射光量
によ。て大きく変動してしまうため、外付発光ダイオー
ドL E Dによって電圧オーバーをクリップしている
。したがって、その価格が高(なるとともに、上記電圧
設定が1.EDO順方向電圧で一転的に決定されてしま
うという欠点がある。Conventionally, as shown in FIG. 1, an electronic desktop calculator that is driven by a thick @kameike has been known. In this electronic desktop calculator, the voltage supplied from the solar cell E depends on the amount of incident light. Therefore, an external light emitting diode (LED) is used to clip overvoltage. Therefore, there are disadvantages in that the price is high (and the voltage setting is completely determined by the EDO forward voltage).
この発明の目的は、外付部品な削減するとともに、その
電源電圧の設定が任意にそIなえろ半導体集積回路装置
な提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device in which the number of external components is reduced and the power supply voltage can be set arbitrarily.
この発明の他の目的は、以下の説明及び図面から明らか
になるであろうっ
第2図には、この発明の一実施例の回路図が示されてい
る。Other objects of the invention will become apparent from the following description and drawings. FIG. 2 shows a circuit diagram of an embodiment of the invention.
同図において1点線で囲まれた部分は、半導体集積回路
装置L S lであり、公知の半導体製造方法によって
、1つの半導体基板上において形成される。In the figure, a portion surrounded by a dotted line is a semiconductor integrated circuit device L S 1, which is formed on one semiconductor substrate by a known semiconductor manufacturing method.
記号Eで示されているのは、太陽電池であり。The symbol E indicates a solar cell.
電源インピーダンスな小さくするために、コンデンサC
が並列に設けられている。この実施例では。To reduce the power supply impedance, capacitor C
are installed in parallel. In this example.
上記太陽電池Eで形成された電圧が半導体集積回路装置
LSIに直接供給され、その内部に次に説明するような
電圧クランプ回路が設けられる。The voltage generated by the solar cell E is directly supplied to the semiconductor integrated circuit device LSI, and a voltage clamp circuit as described below is provided inside the semiconductor integrated circuit device LSI.
上記太陽電池Eかも供給される電圧−VF、は、MOS
FET(絶縁ゲート型電界効果トランジスタ)Qのドレ
インDに印加される。そして、電圧比較器OPは、その
反転入力(−)にMO8F’E’l’QのソースSの電
圧を受け、その非反転入力(+)に基準電圧vrefを
受けて、その出力を上記MO8FETQのゲートGに伝
えることにより、MO8FETQのインピーダンスな制
御して、上記ソースSの亀EIa”−VDDを基準電圧
vrefに一致させろ。The voltage −VF, which is supplied by the solar cell E, is MOS
It is applied to the drain D of the FET (insulated gate field effect transistor) Q. The voltage comparator OP receives the voltage of the source S of MO8F'E'l'Q at its inverting input (-), receives the reference voltage vref at its non-inverting input (+), and transfers its output to the MO8FETQ By transmitting the signal to the gate G of the MO8FETQ, control the impedance of the MO8FETQ to make the voltage EIa''-VDD of the source S match the reference voltage vref.
記号LOGで示されているブラックボックスは。The black box is indicated by the symbol LOG.
特に制限されないが、電子式重上計算機を構成するディ
ジタル制御回路であり、上記MO8FETQを通した電
圧−vDDによって、電源供給がなされ動作するもので
ある。このLQUの表示出力は、特に制限されないがブ
ラックボックスで示された液晶表示語[LCDに伝えら
れ、所定の表示が行なわれる。Although not particularly limited, it is a digital control circuit constituting an electronic overlay computer, and is operated by being supplied with power by the voltage -vDD through the MO8FETQ. The display output of this LQU is transmitted to the liquid crystal display word [LCD] indicated by a black box, although not particularly limited, and a predetermined display is performed.
この実施例では、太陽m池Eからの電圧−■。が大きく
なって、内部電源電圧−Vl)Dが上記基準電圧Vre
fより大きくなろうとすると、wL圧比較器OPは、M
O8FETQのイ/ピータ゛/スを大きくして内部電源
電圧−VDDを一定に電圧クランプする。この実施例に
おいでは、電圧クランプ手段が半導体集積回路装置LS
Iに内蔵されているため、外付部品点数の削減が図られ
、その価格ケ低くすることができる。In this example, the voltage from the solar cell E is −■. becomes larger, and the internal power supply voltage -Vl)D becomes equal to the reference voltage Vre.
When the wL pressure comparator OP tries to become larger than f, the wL pressure comparator OP becomes larger than M
The IP address of O8FETQ is increased to clamp the internal power supply voltage -VDD to a constant voltage. In this embodiment, the voltage clamp means is connected to the semiconductor integrated circuit device LS.
Since it is built into the I, the number of external parts can be reduced and the price can be lowered.
また、電圧クランプを開始する電圧は、基準電圧vre
fにより任意に設定することができる。Furthermore, the voltage at which the voltage clamp starts is the reference voltage vre.
It can be set arbitrarily by f.
なお、この実施例のように1表示装置としてLCl)を
用いるものにおいては、半導体集積回路装置LSIの内
部亀#亀田の上昇により、明るさが変動して表示品質?
悪くさせることの他、非選択出力レベルが上昇して誤表
示させる等の問題がある。したがって、LCD駆動回路
を有する半導体集積回路装置では、上記内部電源電圧−
vDDの定電圧化を図る必要がある。In addition, in the case of using LCl as one display device as in this embodiment, the brightness fluctuates due to the increase in the internal capacitance of the semiconductor integrated circuit device LSI, resulting in poor display quality.
In addition to making things worse, there are other problems such as the non-selection output level rising and causing erroneous display. Therefore, in a semiconductor integrated circuit device having an LCD driving circuit, the internal power supply voltage -
It is necessary to stabilize the voltage of vDD.
ナオ、 M OS F ET Q トL テ、エンハン
スメント型のものを用いる場合には、電圧比較器OPの
電源電圧として上記太陽電池Eからの電圧−■。で動作
させるものとすればよい。あるいは、電圧比較器OPを
内部電源電圧−vDDで動作させる場合には、内Fgり
電圧−”DDが所定の電圧まで上昇するまでの間オンす
る起動用MQ8FETな上記MO8FETQに並列に設
けるものとすればよい。When using an enhancement type MOS FET, the voltage from the solar cell E is used as the power supply voltage of the voltage comparator OP. It should be possible to operate it with Alternatively, when the voltage comparator OP is operated with the internal power supply voltage -vDD, a startup MQ8FET that is turned on until the internal Fg voltage -DD rises to a predetermined voltage is installed in parallel with the above MO8FETQ. do it.
上記MO8FETQとして、ディプレッンヨン型のもの
を用いれば、上記起動回路は不用である。If a depletion type MO8FETQ is used, the starting circuit is unnecessary.
また、電圧比較器OPに、入力オフセラ)III圧をも
たせて、これを基準電圧Vrefとして利用するもので
あってもよい。この場合には、非反転入力(+)側が接
地される。Further, the voltage comparator OP may be provided with an input offset voltage (III) voltage, and this may be used as the reference voltage Vref. In this case, the non-inverting input (+) side is grounded.
さらに、上記基準電圧vrefを、内部ロジック回路の
下限動作電圧付近に設定しておいて、液晶表示用の駆動
電圧は倍電圧回路を用いて3値ないし4値の電圧を形成
するものとしてもよい。Furthermore, the reference voltage vref may be set near the lower limit operating voltage of the internal logic circuit, and the drive voltage for the liquid crystal display may be formed into a three-value or four-value voltage using a voltage doubler circuit. .
また、WL圧の極性は、正の極性な用いるものであっで
もよい。Further, the polarity of the WL pressure may be a positive polarity.
この発明は5太陽電池でその電源電圧が形成される半導
体集積回路装置に広く利用することができるものである
。This invention can be widely used in semiconductor integrated circuit devices whose power supply voltage is generated by five solar cells.
第1図は、従来技術の一例な示すブロック図である。第
2図は、この発明の一実踏例を示す回路図である。
OF・・電圧比較器、LOG・・・ディジタル制御回路
、L CI)・・・液晶表示装置、LSI・・・半導体
集積回路装置。FIG. 1 is a block diagram showing an example of the prior art. FIG. 2 is a circuit diagram showing an example of the present invention. OF...voltage comparator, LOG...digital control circuit, LCI)...liquid crystal display device, LSI...semiconductor integrated circuit device.
Claims (1)
Tと、このMOSFETのソース電圧と所定の基準電圧
と比較して、その出力電圧を上記MO8FETのゲート
に伝えて上記ソース電圧を定電圧化する電圧比較器と、
上記MO8FETのソースから電圧供給を受けて動作す
る電子回路とを含むことな特徴とする半導体集積回路装
置。 2、上記電子回路は、液晶表示装置駆動回路を含むもの
であることを特徴とする特許請求の範囲第1項記載の半
導体集積回路装置。 3、上記電子回路は、電子式卓上計算機を構成するもの
であることを特徴とする特許請求の範囲第2項記載の半
導体集積回路装置。[Claims] 1. MOSFE whose drain receives voltage from a solar cell
T, a voltage comparator that compares the source voltage of this MOSFET with a predetermined reference voltage and transmits the output voltage to the gate of the MO8FET to make the source voltage a constant voltage;
A semiconductor integrated circuit device characterized in that it includes an electronic circuit that operates by receiving voltage supply from the source of the MO8FET. 2. The semiconductor integrated circuit device according to claim 1, wherein the electronic circuit includes a liquid crystal display device drive circuit. 3. The semiconductor integrated circuit device according to claim 2, wherein the electronic circuit constitutes an electronic desktop calculator.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11543782A JPS598033A (en) | 1982-07-05 | 1982-07-05 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11543782A JPS598033A (en) | 1982-07-05 | 1982-07-05 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS598033A true JPS598033A (en) | 1984-01-17 |
Family
ID=14662532
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11543782A Pending JPS598033A (en) | 1982-07-05 | 1982-07-05 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS598033A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60157616A (en) * | 1984-01-26 | 1985-08-17 | Toshiba Corp | In-chip power source converting circuit of submicron semiconductor lsi |
JPS62206774A (en) * | 1986-03-06 | 1987-09-11 | 第一電子工業株式会社 | Loosening proof connector |
US4741706A (en) * | 1986-03-06 | 1988-05-03 | Daiichi Denshi Kogyo Kabushiki Kaisha | Locked connector |
JPH0572505A (en) * | 1991-09-12 | 1993-03-26 | Fujitsu Ltd | Electric field absorption type optical modulating circuit |
-
1982
- 1982-07-05 JP JP11543782A patent/JPS598033A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60157616A (en) * | 1984-01-26 | 1985-08-17 | Toshiba Corp | In-chip power source converting circuit of submicron semiconductor lsi |
JPS62206774A (en) * | 1986-03-06 | 1987-09-11 | 第一電子工業株式会社 | Loosening proof connector |
US4741706A (en) * | 1986-03-06 | 1988-05-03 | Daiichi Denshi Kogyo Kabushiki Kaisha | Locked connector |
JPH0355034B2 (en) * | 1986-03-06 | 1991-08-22 | ||
JPH0572505A (en) * | 1991-09-12 | 1993-03-26 | Fujitsu Ltd | Electric field absorption type optical modulating circuit |
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