JPS5980023A - Supplying current source circuit working at low voltage - Google Patents

Supplying current source circuit working at low voltage

Info

Publication number
JPS5980023A
JPS5980023A JP19124982A JP19124982A JPS5980023A JP S5980023 A JPS5980023 A JP S5980023A JP 19124982 A JP19124982 A JP 19124982A JP 19124982 A JP19124982 A JP 19124982A JP S5980023 A JPS5980023 A JP S5980023A
Authority
JP
Japan
Prior art keywords
current
circuit
transistor
base
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19124982A
Other languages
Japanese (ja)
Inventor
Junji Kajiwara
梶原 淳治
Fumio Yasui
文男 安井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP19124982A priority Critical patent/JPS5980023A/en
Publication of JPS5980023A publication Critical patent/JPS5980023A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/091Integrated injection logic or merged transistor logic

Abstract

PURPOSE:To ensure the stable working of a current source circuit down to a low level of voltage, by using the collector current of a transistor circuit containing an emitter-base diode circuit set in parallel to a constant voltage source as a reference current of a current mirror circuit and then applying the output of the current mirror circuit to an ILL. CONSTITUTION:A constant voltage source VREF is provided with a band gap reference circuit and used as a reference power supply having a temperature coefficient set approximately at zero. For an npn transistor TRQ1, the base, emitter and collector are connected to the source VREF, a resistance R1, and the base and the collector of a pnp TRQ2 as well as the base of a pnp TRQ3 respectively. The current I1 flowing to the resistance R1 connected between the emitter of the TRQ1 and an earth is set at (VREF-VBE1)/R1, where VBE1 shows the base-emitter voltage of the TRQ1. This current I1 flows to the TRQ2, and the injecting current Iinj is set equal to the current flowing through the R1 by TRQ2 and Q3 which constitute a current mirror. Thus an IIL circuit 1 can be made to have the stable working down to a low level of power supply voltage.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はIIL回路の注入電流源回路に関するもので、
特に低電圧まで駆動可能な注入電源回路に関するもので
ある。
[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an injection current source circuit for an IIL circuit.
In particular, it relates to an injection power supply circuit that can be driven to low voltages.

(従来例の構成とその問題点) 第1図は従来公知のIIL回路の注入電流源回路の構成
を示す回路図であり、VRIi、Fは定電圧源で、通常
は温度特性を持たないバンドギャップリファレンス回路
が用いられ、その電圧値は約1.5Vであり、IOは定
電流源、Q工〜Q7はトランジスタ、R1+ R2+ 
R3は抵抗、1はIIL回路網を示す。
(Configuration of conventional example and its problems) Fig. 1 is a circuit diagram showing the configuration of an injection current source circuit of a conventionally known IIL circuit. A gap reference circuit is used, the voltage value of which is approximately 1.5V, IO is a constant current source, Q - Q7 are transistors, R1 + R2+
R3 is a resistor, and 1 indicates an IIL network.

−ここで、トランジスターQl−Q5、抵抗R1。- where transistors Ql-Q5, resistor R1;

R2、定電圧源VR□及び定電流源■oからなる回路は
負帰還のかかった差動増幅回路であシ、その出2 力電圧Vo u Vo =  VREF (1+R1−
)となる。
The circuit consisting of R2, constant voltage source VR□, and constant current source ■o is a differential amplifier circuit with negative feedback.
).

トランジスタQ6及びQ7はIILによるインバータ回
路の等価回路を示したもので、IIL回路網1はこれら
等価回路の集合体を示している。抵抗R3はIIL回路
全体に流し込む注入電流を定める/ζめの抵抗で注入電
流は次の式から定まる。
Transistors Q6 and Q7 represent an equivalent circuit of an inverter circuit using IIL, and IIL circuit network 1 represents a collection of these equivalent circuits. The resistor R3 determines the injection current flowing into the entire IIL circuit, and the injection current is determined by the following equation.

(Vo−VBlc6)/R3二11n。(Vo-VBlc6)/R3211n.

但し・ ■ln]は注入電流、 V16はトランジスタQ6のV、。(ベース・エミッタ
電圧) 第1図の回路において、注入電流が保証されるための電
源電圧(VCC)の最低値は次の式より求丑る。
However, *ln] is the injection current, and V16 is the V of transistor Q6. (Base-emitter voltage) In the circuit shown in FIG. 1, the minimum value of the power supply voltage (VCC) for ensuring the injection current is calculated from the following equation.

v−Vo十vや、十VBE3 C :: 1.2v(1+R2/R,)+1.2v≧24v
 (R2−0のとき最低値) 但し、VBE5はトランジスタQ5のVBEVBg3は
トランジスタQ3の”BE 第2圀は第1図の回路に若干の修正を加え、さらに低い
電源電圧まで駆動可能にした回路図である。
v-Vo 10v, 10VBE3 C:: 1.2v (1+R2/R,)+1.2v≧24v
(The lowest value when R2-0) However, VBE5 is the transistor Q5, and VBEVBg3 is the transistor Q3's BE. It is.

トラ7ノスタQ1 、Q2 −Q3 と、抵抗R1。Tiger 7 Nosta Q1, Q2 - Q3, and resistor R1.

R2、定電流源IO%定電圧源”REFからなる差動回
路により出力電圧voは定電圧源の電圧vR□と等しく
なる。
The output voltage vo becomes equal to the voltage vR□ of the constant voltage source by a differential circuit consisting of R2, a constant current source IO%, and a constant voltage source "REF."

電源電圧V。0の最低値は次の式より求まる。Power supply voltage V. The lowest value of 0 is determined by the following formula.

Voo二Vo+Vn、Ba + RI II= 1.8
  + RI II 但し、11は抵抗R1に流れる電流。
Voo2 Vo + Vn, Ba + RI II = 1.8
+ RI II However, 11 is the current flowing through the resistor R1.

注入電流l1njがttはトランジスタQ3のコレクタ
電流と等しいとした場合、抵抗R1に流れる電流■1を
求めてみる。例として注入電流I・ がnj 2畝・電源電圧■ccの最低電圧を20vの場合を考え
る。トランジスタQ3のhFEを50とすると、トラン
ジスタQ3のベース電流は2mA 150 = 40μ
Aとなる。電流I、の値は40μAに比べて十分大きく
とる必要があり、例えば仮に100μ八とすると抵抗R
1の値は (■cc  1−8 ) /I−=(2,0−1,8)
/2 k−Ωとなる。
Assuming that the injection current l1nj tt is equal to the collector current of the transistor Q3, the current {circle around (1)} flowing through the resistor R1 will be determined. As an example, consider a case where the injection current I. is nj 2 ridges and the minimum voltage of the power supply voltage ■cc is 20V. If hFE of transistor Q3 is 50, the base current of transistor Q3 is 2mA 150 = 40μ
It becomes A. The value of the current I needs to be sufficiently larger than 40 μA; for example, if it is 100 μA, the resistance R
The value of 1 is (■cc 1-8) /I-=(2,0-1,8)
/2 k-Ω.

第2図の回路は上記のような定数の決め方により低い電
源電圧丑で動作可能であるが、次のような欠点がある。
Although the circuit shown in FIG. 2 can operate with a low power supply voltage by determining the constants as described above, it has the following drawbacks.

一つは100%角帰還のかかった差動増幅回路を構成し
ているため発振し易く、発振防止用のコンデン妖を必要
とするため、半導体重C化した場合大面積をとられるこ
とである。他の欠点としては、電源電圧範囲が広い場合
、電流11が大きく変るため、差動増幅回路のトランジ
スタQl  、Q2を流れる電流バランスが悪く、出力
電圧Voの安定度が良くない上に、定電流源Ioに大き
な電流を必要とする点である。例えば、前述の例の定数
の場合、電源電圧V。0が3になった場合、 11−3.吋””−= 600μA 2にΩ となり、電源電圧V。0が20vの場合に比べて6倍も
変化する。
One is that since it is a differential amplifier circuit with 100% angular feedback, it easily oscillates, and requires a capacitor to prevent oscillation, so it takes up a large area if it is made of semiconductor heavy C. . Another disadvantage is that when the power supply voltage range is wide, the current 11 changes greatly, so the current balance flowing through the transistors Ql and Q2 of the differential amplifier circuit is poor, the stability of the output voltage Vo is not good, and the constant current This is because the source Io requires a large current. For example, for the constant in the example above, the power supply voltage V. If 0 becomes 3, 11-3.吋””-=600μA 2Ω, and the power supply voltage is V. The change is six times greater than when 0 is 20V.

(発明の目的) 本発明は」二記のような欠点を除去するためになされた
もので、電源変動幅が大きく、シかも低電圧まで駆動さ
せることが必要な、例えば電池を電源とするIIL回路
において安定な注入電流源回路を提供するものである。
(Objective of the Invention) The present invention has been made in order to eliminate the drawbacks mentioned above. This provides a stable injection current source circuit in the circuit.

(発明の構成) 第3図は本発明の一実施例の構成を示す回路図である。(Structure of the invention) FIG. 3 is a circuit diagram showing the configuration of an embodiment of the present invention.

定電圧源V8イは、第1図の場合と同じくバンドギャッ
プリファレンス回路により構成された温度係数がほぼ零
の基準電圧源であり、電圧値は約12vである。
The constant voltage source V8a is a reference voltage source with a temperature coefficient of approximately zero, which is constructed of a bandgap reference circuit as in the case of FIG. 1, and has a voltage value of about 12V.

QluNPN)ランノスタで、ベースは定電圧源VRE
Fに、エミッタは抵抗R1に、コレクタはPNPトラン
ノスタQ2のベース及びコレクタと、PNPトランノス
タQ3のベースにそれぞれ接続されている。抵抗R1は
一端をNPN )ランジスタQ!のエミッタに、他端は
GNDに接続され、PNP )ランジスタQ2 及びQ
3はエミッタ、ベーーζが共通で、共通エミッタは電源
vccに、共通ベースはトランジスタQ2のコレクタと
共にNPN )ランジスタQ1のコレクタにそれぞれ接
続され、トランジスタQ3のコレクタはIIL回路網1
の注入電流端子に接続されている。
QluNPN) Lannostar, the base is a constant voltage source VRE
F, the emitter is connected to the resistor R1, the collector is connected to the base and collector of the PNP trannostar Q2, and the base of the PNP trannostar Q3, respectively. Resistor R1 has one end connected to NPN) transistor Q! , the other end is connected to GND, and the PNP) transistors Q2 and Q
3 has a common emitter and a common base ζ, the common emitter is connected to the power supply VCC, the common base is connected to the collector of the NPN transistor Q1 along with the collector of the transistor Q2, and the collector of the transistor Q3 is connected to the IIL network 1.
is connected to the injection current terminal of

(実施例の説明) トうンノスタQ1のエミッタとGND間に接続された抵
抗R,を流れる電流11は(”REF  ’nIi、1
)4、(但L VREI u )ランノスタQ】のベー
ス・エミッタ間電圧)となる。この電流はトランジスタ
Q2に流れ、カレントミラーを構成しているトランジス
タQ2 、Q3により、注入電流■injは抵抗R1を
流れる電流(VRgF +VBEI)/R1と等しくな
る。
(Explanation of Example) The current 11 flowing through the resistor R connected between the emitter of the Touno Star Q1 and GND is ("REF 'nIi, 1
) 4, (L VREI u ) the base-emitter voltage of Lannostar Q]. This current flows through the transistor Q2, and due to the transistors Q2 and Q3 forming a current mirror, the injection current ■inj becomes equal to the current (VRgF +VBEI)/R1 flowing through the resistor R1.

この回路の最低電源電圧は、定電圧源の電圧”REI’
を12vとすると次の式により求捷る。
The minimum power supply voltage of this circuit is the constant voltage source voltage “REI”
When is 12V, it is determined by the following formula.

VCCoVREF−VBE1+VCEI+VBE2≧1
.2−0.6オ0.6+0.6−1.8但し、VCK’
lはQlのコレクタ・エミ、り間電圧。
VCCoVREF-VBE1+VCEI+VBE2≧1
.. 2-0.6o0.6+0.6-1.8However, VCK'
l is the collector-emitter voltage of Ql.

VBE2はQ2のベース・エミッタ間電圧◇この様に第
3図の構成によれば、18vという低い電源電圧までI
IL回路網1を安定に動作させる事が可能である。さら
に温度特性に関しても、半導体ICでは抵抗の温度係数
が約+2000〜+3000 ppm 7℃であるため
、抵抗R1の温度係数トNPN )ランノスタQtの”
Bgの温度係数が打ち消し合い、基準電圧源の温度係数
が零である事と合わせて、注入電流の温度係数はほぼ零
となり極めて安定な注入電流源が構成できる。また素子
数も非常に少なく、帰還もかかっていないため、発振の
恐れがない等、極めて簡単で安定なIIL注入電流源で
あるといえる。
VBE2 is the voltage between the base and emitter of Q2 ◇ According to the configuration shown in Figure 3, I
It is possible to operate the IL circuit network 1 stably. Furthermore, regarding temperature characteristics, in semiconductor ICs, the temperature coefficient of resistance is approximately +2000 to +3000 ppm 7°C, so the temperature coefficient of resistor R1 (NPN) of Lannostar Qt is
The temperature coefficients of Bg cancel each other out, and together with the fact that the temperature coefficient of the reference voltage source is zero, the temperature coefficient of the injection current becomes almost zero, and an extremely stable injection current source can be constructed. Furthermore, since the number of elements is very small and there is no feedback, it can be said that it is an extremely simple and stable IIL injection current source with no fear of oscillation.

第4図は本発明の他の実施例である。第3図においてI
IL回路網が大規模となり大きな注入電流を必要とする
場合、PNPトランジスタの大電流でのhFgがあ捷り
大きくないため、トランジスタQ3のベース電流が大き
くなって、抵抗R1を流れる電流と注入電流の値が異な
ってくる。これを改善したのが第4図の構成である。
FIG. 4 shows another embodiment of the invention. In Figure 3, I
When the IL circuit network becomes large and requires a large injection current, the hFg of the PNP transistor at a large current is not large enough to alternating, so the base current of the transistor Q3 becomes large, and the current flowing through the resistor R1 and the injection current increase. The values of will be different. The configuration shown in FIG. 4 improves this.

第4図において、定電圧源■REF % )伊ンジスタ
Qi  、Q2  + Q3 、抵抗R1の部分は第3
図と同様である。NPNトランジスタQ4及びQ5は共
通エミッタ、共通ベースをもちカレントミラーを構成し
ており、その共通エミッタ/1GND K接続されてい
る。トランジスタQ4のコレクタはトランジスタ?Q 
4及びQ5の共通ベース及びPNP )ランジスタQ3
のコレクタと接続されている。トランジスタQ5のコレ
クタはPNPトランジスタQ6のコレクタ及ヒPNP)
ランノスタQ7のベースに接続されている。PNP )
ランジスタQ6及びQ8は共通エミッタ、共通ベースを
もち、カレントミラーを構成している。この共通エミッ
タは電源V。0に、共通ベースはPNP )ランノスタ
Q7のエミッタに接続されている。PNP )ランノス
タQ6のコレクタは、トランジスタQ11のコレクタと
トランジスタQ7のベースに接続されている。トラ、ン
ジスタQ8のコレクタは115回路網に吠電流を流し込
んでいる。トランジスタQ7のコレクタはGNDに接続
されている。
In Fig. 4, the constant voltage source (REF%), the resistor Qi, Q2 + Q3, and the resistor R1 are the third
It is similar to the figure. NPN transistors Q4 and Q5 have a common emitter and a common base and form a current mirror, and are connected to the common emitter/1GNDK. Is the collector of transistor Q4 a transistor? Q
4 and Q5 common base and PNP) transistor Q3
is connected to the collector. The collector of transistor Q5 is the collector of PNP transistor Q6 and the collector of PNP)
Connected to the base of Lannostar Q7. PNP)
Transistors Q6 and Q8 have a common emitter and a common base, and constitute a current mirror. This common emitter is the power supply V. 0, the common base is connected to the emitter of the lannostar Q7 (PNP). PNP) The collector of the lannostar Q6 is connected to the collector of the transistor Q11 and the base of the transistor Q7. The collector of transistor Q8 is injecting current into the 115 circuit network. The collector of transistor Q7 is connected to GND.

上記のような回路構成において、トランジスタQ1 ・
Q4 ・Q5 ・Q7のコレクタ電流をそれぞれI+ 
 lI4 115 117  として各電流の関係を求
めてみる。電流I、は第3図の場合で述べたように■l
−(”REF  VBEI )/ R1となる。PNP
 l−ランノスタQ2.Q3のhFEが十分大きくベー
ス電流が無視できる領域に11の値を設定したとするト
、トランジスタQ3のコレクタ電流けI、  と等しく
なシ、これがトランジスタQ4に流れるので■4−■l
となる。トランジスタQ4と。5はカレントミラーを構
成しているので15−14となる。
In the circuit configuration as described above, the transistor Q1 ・
The collector currents of Q4, Q5, and Q7 are respectively I+
Let's find the relationship between each current as lI4 115 117. As stated in the case of Fig. 3, the current I is
-(”REF VBEI)/R1.PNP
l-Lannostar Q2. If we set the value of 11 in the region where hFE of Q3 is sufficiently large and the base current can be ignored, then the collector current of transistor Q3 is equal to I, which flows through transistor Q4, so ■4-■l
becomes. With transistor Q4. Since 5 constitutes a current mirror, it becomes 15-14.

次に、注入電流l1njをI5のn倍としたいときPN
P トランジスタQ8は、Q6のn個分並列に接続すれ
ばよい。このときPNP トランジスタ。80ベース電
流が大きくなるが、トランジスタ。6及びQ8のベース
電流の総和は、トランジスタ。7のエミッタに流れ込む
。この値は、はぼI7に等しい。トランジスタQ7のベ
ース電流はI7を。7の電流増幅率で割ったものに等し
く、充分小さい値となる。このためトランジスタQ5の
コレクタ電流■5はトランジスタQ6のコレクタ電流ト
ホぼ等しく、それによって、Q6のn個分の電流が正確
にQ8のコレクタ電流つまり注入電流となる。
Next, when we want to make the injection current l1nj n times I5, PN
N P transistors Q8 may be connected in parallel with the number of transistors Q6. At this time, PNP transistor. 80 The base current increases, but the transistor. The sum of the base currents of 6 and Q8 is the transistor. Flows into the emitter of 7. This value is equal to I7. The base current of transistor Q7 is I7. It is equal to the value divided by the current amplification factor of 7, which is a sufficiently small value. Therefore, the collector current 5 of the transistor Q5 is almost equal to the collector current of the transistor Q6, and as a result, the current for n times of Q6 becomes exactly the collector current of Q8, that is, the injection current.

第4図の回路では、最低動作電源電圧は、第3図と同じ
約1.8 Vであシ、特に注入電流の多い大規模なII
L回路網を含む半導体ICの注入電流源として効果を発
揮するものである。さらにつけ加えるならば、第3図、
第4図共に電源電圧が高い場合の用途でも使用可能であ
る。
In the circuit shown in Figure 4, the minimum operating power supply voltage is approximately 1.8 V, the same as in Figure 3.
This is effective as an injection current source for a semiconductor IC including an L circuit network. In addition, Figure 3,
Both of the devices shown in FIG. 4 can also be used in applications where the power supply voltage is high.

(発明の効果) 以上述べたように、本発明によれば、極めて簡単な構成
で低電圧まで駆動させることかで′き、安定な注入電流
源回路を実現することができる利点がある。
(Effects of the Invention) As described above, the present invention has the advantage of being able to drive to a low voltage with an extremely simple configuration and realizing a stable injection current source circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のIIL注入電流源回路の構成を示す回路
図、第2図は第1図の回路に若干の修正を加えた従来の
回路図、第3図は本発明の一実施例の構成を示す回路図
、第4図は本発明の他の実施1・・IIL回路網、vR
オ・・・定電圧源、Vco・・・電源電圧、■。・・・
出力電圧、■。・・定電流源、Q1〜Q8・・トランジ
スタ。 第1図 り 第2図 第3図 第4図 II
FIG. 1 is a circuit diagram showing the configuration of a conventional IIL injection current source circuit, FIG. 2 is a conventional circuit diagram with slight modifications to the circuit in FIG. 1, and FIG. 3 is a circuit diagram of an embodiment of the present invention. A circuit diagram showing the configuration, FIG. 4 is another embodiment 1 of the present invention...IIL circuit network, vR
O... Constant voltage source, Vco... Power supply voltage, ■. ...
Output voltage, ■. ... Constant current source, Q1 to Q8... Transistor. Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. II

Claims (3)

【特許請求の範囲】[Claims] (1)定電圧源と、この定電圧源と並列に第1のNPN
 トランジスタのベース・エミッタ間ダイオードと抵抗
の直列回路を形成し、上2−11のNPNトランノスタ
のコレクタ電流を第2及び第3のPNPトランジスタが
構成するカレントミラー回路の基準電流として流し、そ
のカレントミラー回路の出力をIIL回路網の注入電流
端子と接続したことを特徴とする低電圧作動注入電流源
回路。
(1) A constant voltage source and a first NPN in parallel with this constant voltage source.
A series circuit of a diode and a resistor is formed between the base and emitter of the transistor, and the collector current of the NPN transnoster shown in 2-11 is passed as a reference current of the current mirror circuit constituted by the second and third PNP transistors, and the current mirror is A low voltage operated injection current source circuit characterized in that the output of the circuit is connected to the injection current terminal of an IIL network.
(2)  定電圧源をバンドギャップリファレンス回路
で構成したことを特徴とする特許請求の範囲第(1)項
記載の低電圧作動注入電流源回路。
(2) The low voltage operation injection current source circuit according to claim (1), wherein the constant voltage source is constituted by a bandgap reference circuit.
(3)第2及び第3のPNP )ランノスタで構成する
カレントミラー回路と、第4及び第5のNPNトランノ
スタで構成するカレントミラー回路と、第6及び第8の
PNP )ランジスタで構成するカレントミラー回路を
有し、その第8のPNP )ランジスタのコレクタを出
力としてIIL回路網の注入電流端子と接続したことを
特徴とする特許請求の範囲第(1)項記載の低電圧作動
注入電流源回路。
(3) 2nd and 3rd PNP) A current mirror circuit made up of a runnostar, a current mirror circuit made up of a 4th and 5th NPN trannostar, and a 6th and 8th PNP) A current mirror made up of a transistor. A low voltage operation injection current source circuit according to claim 1, characterized in that the collector of the eighth PNP transistor is connected as an output to the injection current terminal of the IIL network. .
JP19124982A 1982-10-30 1982-10-30 Supplying current source circuit working at low voltage Pending JPS5980023A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19124982A JPS5980023A (en) 1982-10-30 1982-10-30 Supplying current source circuit working at low voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19124982A JPS5980023A (en) 1982-10-30 1982-10-30 Supplying current source circuit working at low voltage

Publications (1)

Publication Number Publication Date
JPS5980023A true JPS5980023A (en) 1984-05-09

Family

ID=16271381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19124982A Pending JPS5980023A (en) 1982-10-30 1982-10-30 Supplying current source circuit working at low voltage

Country Status (1)

Country Link
JP (1) JPS5980023A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56160139A (en) * 1980-05-14 1981-12-09 Toshiba Corp I2l logical circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56160139A (en) * 1980-05-14 1981-12-09 Toshiba Corp I2l logical circuit

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