JPS5980018A - Phase detecting circuit - Google Patents

Abstract

PURPOSE:To always detect the maximum phase difference, by providing two counters which convert the phase difference between a clock to be measured and a reference clock into a pulse and then compare the pulse count values and switching these two counters by the value of comparison. CONSTITUTION:A reference clock applied to a terminal (a) and a clock to be measured which is applied to a terminal (b) are detected 1 and 2 respectively, and an FF3 is set and reset. Thus the FF3 opens an AND gate 4 for a period corresponding to the phase difference. While high frequency pulses sent from an oscillator 10 are counted by a counter 6 via the gate 4. In this case, the count value of a counter 7 is set at 0. Then the count values of counters 6 and 7 are compared with each other by a comparator 8. When the result of this comparison is positive, the next counting is switched to the counter 7 by a switch control circuit 9 with the counter 6 reset respectively. While if the result of comparison is negative, the circuit 6 controls the counter 6 to perform also the next counting and to reset the counter 6. Thus the counter 6 or 7 always stores the maximum phase difference of that time point.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) 1 Technical Field of the Invention The present invention relates to a circuit for detecting phase fluctuations of a clock having jitter.

(b), Prior Art and Problems Figure 1 is a block diagram showing an example of a conventional phase detection circuit. In the figure, 1 and 2 are both rise detection circuits, 3 is a flip-flop circuit, and 4 is a low frequency 5 is a peak value hold circuit, a is a reference clock input terminal, b is a measured clock input terminal, and C is a peak value output terminal.

The operation of the conventional phase detection circuit will be explained below with reference to FIG.

The rising edge detection circuits 1 and 2 have differential characteristics, and both the waveform of the reference clock applied to the a terminal and the waveform of the clock to be measured applied to the b terminal are made to rise steeply, causing a flip at the rising edge of the reference clock. Flop 3 is set and flips at the rising edge of the clock under test.
Flop 3 is reset. When the output waveform of the flip-flop 3 obtained in this manner is applied to the low-pass filter 4, the low-pass filter 4 can remove high frequency components and obtain a direct current corresponding to the phase difference. However, the circuit that detects the phase difference between locks like this one converts the phase difference with the reference clock into an analog value such as a DC voltage.
Since only the average value of the clock phase fluctuation is known, it is fine when the phase difference changes slowly, but cannot be followed when it changes a little quickly.

However, when transmitting data, the maximum value of the phase fluctuation is more important than the average value of the phase fluctuation.

For this reason, there has been a need to develop a phase detection circuit that digitally processes clock phase fluctuations, detects and records the maximum value of the phase fluctuations.

(C) 8 Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks of conventional analog phase detection circuits and to provide a digital phase detection circuit that detects and stores the maximum value of clock phase fluctuation. It is.

(d) 9 Structure of the Invention According to the present invention, the above-mentioned object includes: a detection circuit that detects a phase difference between a clock under test and a reference clock; a sampling circuit that pulses the output of the detection circuit; In the sample link circuit, two counters that count the sampled pulse as 1 are compared with the magnitude of the autopsy values of the two counters, and a signal of "'0" or "bi" is generated depending on the comparison result. This is achieved by providing a phase detection circuit characterized in that it has a comparison circuit that outputs an output, and a switching control circuit that switches between switch and counter and resets the two selected counters based on the output of the comparison circuit. Ru.

(e) 1 Embodiment of the Invention Figure 2 is a block diagram showing an embodiment of the invention.
．． 2 is a rise detection circuit, 3 is a flip-flop circuit, 4 is an ant gate, 5 is a switch, 6 is a counter A, 7 is a counter B, 8 is a comparison circuit, 9 is a switching control circuit, 10 is a frequency f It represents an oscillator, a reference clock is applied to the a terminal, and a measured clock is applied to the b terminal.

FIG. 3 is a diagram for explaining the operation of FIG. 2.

This will be explained in detail below with reference to FIG.

A reference clock is applied to the a terminal in Fig. 2, and b 61:A
The clock under test is applied to the child. Figure (11) in Figure 3,
Figure fb1 shows a reference clock and a clock to be measured, respectively.

The rise time of each clock is identified by a rise detection circuit 1.2, and the rise detection circuit 1 detects the flip-flop 3 at the rise time of the reference clock.
is set, and the rising edge detection circuit 2 resets the flip-flop 3 at the rising edge of the clock to be measured. As a result, the flip-flop 3 operates as shown in diagram fc1 of FIG. 3, and the pulse width represents the phase difference. Therefore, the flip-flop 3 opens the AND gates 1 to 4 for a time corresponding to the phase difference, and during that time the frequency r of the oscillator 10 increases.
The high frequency pulses enter the counter A via the AND gate 4 and are counted. At this time, the count value of counter B is set to zero. Next, the comparison circuit 8 compares the counts of counters A and B, and if the result A-B is positive, the switching control circuit 9
Therefore, the next counting is performed by counter B (as shown by the dotted line of switch 5), and at the same time, counter B is reset. On the other hand, if A-B is negative, the switching control circuit 9 causes the next count to be performed by the counter A, and at the same time, the counter A is reset.

As is clear from the following explanation, the maximum value of the phase difference up to that time is always stored in the counter A or B.

(f) 0 Effects of the Invention As explained in detail above, the present invention has the great effect that it is possible to measure phase fluctuations of a clock having jitter every moment and to accurately determine its maximum value. .

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of a conventional phase detection circuit, in which 1 and 2 are both rise detection circuits, 3 is a flip-flop circuit, 4 is a low-pass filter, and 5 is a peak value hold circuit. , a is a reference one input terminal, b is a clock input terminal to be measured, and C is a peak value output terminal. The second side is a block diagram showing one embodiment of the present invention, and 1
．． 2 is a rise detection circuit, 3 is a free knob flop circuit, and 4 is an AND game 1 to . 5 is a switch, 6 is a counter A, 7 is a counter B, 8 is a comparison circuit, 9 is a switching f+ff11 circuit, 10 is an oscillator with a frequency f,
a is a reference clock input terminal, b is a measured clock input terminal, and C is a peak value output terminal. FIG. 3 is a diagram for explaining the operation of FIG. 2.

Claims (1)

[Claims] a detection circuit that detects the phase difference between the clock under test and the reference clock; a sampling circuit that converts the output of the detection circuit into pulses; and two counters that count the pulses sampled in the sampling circuit; A comparator circuit that compares the counts of two counters and outputs a signal of "0" or "1'' according to the comparison result, and a switch that is switched by the output of the comparator circuit and a selected A phase detection circuit comprising a switching control circuit for resetting two counters.