JPS59761A - Picture processing system of plural processors - Google Patents

Abstract

PURPOSE:To improve the operating rate of a processor and to shorten the processing time, by sharing uniformly the number of coordinate to be calculated at the generation of a graph to each slave processor. CONSTITUTION:A multiplexer MPX switches a system control address SCA to a refresh memory RM and an access address of the slave processor SP. Processor modules PM1-PMn are programmed internally so that a continuous screen element is shared in order as to each raster on the screen and the operating processing such as the generation of a graph is executed at each of n-set of the screen elements. A master processor MP8 decodes a picture processing instruction inputted from an external circuit and gives a processing instruction in parallel to all the SPs. A system control circuit 13 generates a timing control signal such as supply of addresses to the RM under the control of the MP8.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a raster scan type graphic display system controlled by a plurality of processors, in which a screen element such as a pixel is associated with a processor, and an arrangement is made between the processors in order to improve the operating rate of each processor. This invention relates to an image processing method that performs the combination of .

2. Background of the Technology In a conventional raster scan type graphic display system using a plurality of processors, one display screen is divided into blocks, and the processing of each block is assigned to a separate processor to perform parallel processing. As a result, the load on the processors operating on each position of the generated figure becomes uneven, and the overall utilization rate of the entire processor decreases.Even if the number of processors is increased, the image processing The disadvantage is that the speed is not improved.

FIG. 1 schematically shows an example of the configuration of the conventional graphic display system. In the figure, 1 is a screen area of a graphic display, 2 is a graphic to be displayed, 3 is a master processor, and 4 to 7 are slave processors.

The screen area consists of four vertical screen blocks■.

It is divided into n, m, and (2) blocks, and graphic processing within each block is performed by four slave processors.

The tasks are divided among ■, ■, and ■. Mask processor 3 is! Slave processor schedule management,
Controls communication with external peripheral devices, etc.

The operating rate of each slave processor is determined by the amount of computation of the figure part included in the screen block it is in charge of, so for example, in the example shown, the operating rate of the slave processor ■ that processes the screen block ■ containing many nine figures is high and is on the order of 1. of the slave processor.

■Continues. However, slave processor (2) has no load to process at all.

In this way, shapes are unevenly distributed on one screen.

It is extremely normal for the amount of computation required to generate graphics to be uneven in normal graphic processing, so it is recommended to increase the number of parallel processing by increasing the number of slave processors.
Even if an attempt is made to improve the image processing speed, the result will not be as high as expected.

Object and Structure of the Invention An object of the present invention is to allocate screen elements in such a way that the load of processing one image is distributed as evenly as possible to a plurality of processors in order to solve the problems in the conventional method described above. The goal is to provide a method.

As a configuration for this purpose, the present invention provides a raster scan type graphic display system using a plurality of processors, in which screen elements adjacent to each other in the raster scan direction are controlled by different processors, and furthermore, a processor that controls the adjacent screen elements is provided. It is characterized by tighter coupling between processors than with other processors.

Embodiment of the Invention FIG. 2, 13m is an explanatory diagram conceptually showing the nine non-inventive systems.

The method of the present invention distributes processing to each of a plurality of processors for each one or more pixels arranged in one raster direction on one screen, as illustrated in FIG. 21.

Therefore, as illustrated in FIG. 3, if the image processing unit in the X direction is ΔX, each processor shares the X coordinate value that is shifted by ΔX, and even if the number of processors is four.

The graphic element calculation is executed every 4Δp.

As a result, the screen elements to be processed by each processor are finely and uniformly distributed over the entire nine screens, making it possible to equalize the image processing load of each processor.

FIG. 4 is a block diagram of a graphic display system according to a ninth embodiment of the present invention.

In the figure, 8 indicates a master processor, and 9 to 12 indicate processor modules PM2 to PM2. Further, 13 indicates a system control circuit, and 14 indicates a shift register. Each of PMs ■ to ■ consists of a slave processor, a multiplexer MPX, and a refresh memory. The MPX switches between the system control address and the slave processor's access address for refresh memory. The refresh memory is configured such that each bit corresponds to a pixel, and by reading this in synchronization with raster scanning, an image output is obtained. Also, each slave processor
Neighbors are connected by a daisy-chain interrupt loop.

The processor modules PM■~■ are configured to sequentially handle successive screen elements (for example, pixels) for each raster on the screen, and to perform graphic generation and other arithmetic processing for each screen element. is programmed internally.

The master processor 8 interprets image processing commands input from an external circuit, such as commands that give two coordinate values and connect them with a straight line, or commands that give a center and radius and draw a circle, etc. It issues processing instructions to the slave processors in parallel and sends control signals to the master system control circuit 13.

The system control circuit 13p generates various timing control signals for the system under the control of the master processor 8, including supplying a refresh address to the refresh memory and a shift clock to the shift register 14.

The shift register 14 functions as a parallel-to-serial converter for synthesizing the results of calculations performed by each processor module PM in parallel on sequential coordinate positions in the horizontal direction of nine screens as an image signal with consecutive coordinate positions. Function.

FIG. 5 shows an embodiment of the shift register 14.

The illustrated shift register has a capacity of 1 x m bits, and n
The calculation results (rlL data line outputs) performed by each of the processor modules on 9m screen elements are stored in m sets of n bits in parallel.

Output in series.

FIG. 6 shows another embodiment of the shift register 14. In this embodiment, in order to reduce the amount of use of shift registers capable of high-speed operation, the entire shift register is configured in two stages. In the figure, 14-0 is an n-bit high-speed operation shift register, and 14-1 to 14-n are shift registers 14.
This is a low-speed operation shift register that operates with a 17n-divided clock of -o operating clock. The m data line outputs of PM ■ to ■ are temporarily stored in parallel in the low-speed operation shift registers 14-1 to 14-n, and then data is simultaneously output in series from these shift registers. n
Bit by bit is stored in parallel in the high-speed operation shift register 14-0. The contents of shift register 14-0 are output in series, and then the next n bits are stored again from shift registers 14- to 14-n. By repeating these operations once, the same result as the circuit in Figure 5 can be obtained,
Le・ru. Also, artwork becomes easier.

FIG. 7 shows the internal configuration of the processor module, particularly the slave processor.

A bus control circuit 15 controls connection with a common bus. 16 and 17 are input/output ports.

It is used to combine interrupt signals through a daisy chain for exchanging calculation results between two adjacent processors. 18 is a CPU.

It executes commands such as calculating coordinates and controlling nine pixels given by the master processor. Reference numeral 19 denotes a memory in which CPU programs, constant tables, or work areas are placed.

20 is a bus control circuit.

Performs bus control when accessing refresh memory.

Interrupt control using a daisy chain is for performing priority interrupt processing between connected slave processors on both sides.

When drawing vertical or nearly horizontal diagonal lines, it functions effectively for controlling adjacent pixels to make the drawn line easier to see.

Effects of the Invention According to the present invention, the number of coordinates that must be calculated when generating 9 figures is distributed almost equally to each slave processor, so that the operating rate of the processor can be increased and the processing time can be shortened. ○Furthermore, when adjacent pixels correspond to adjacent processors, as in the present invention, the connection between adjacent processors by daisy chain increases the efficiency of exchanging control and calculation results with other processors, and improves throughput. The decline can be suppressed.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a conventional graphic display system using multiple processors. FIGS. 2 and 3 are explanatory diagrams of a graphic display system using a plurality of processors according to the present invention, and FIG. 4 is a configuration diagram of an embodiment system. FIG. 5 and FIG. 6 are respectively an embodiment circuit diagram of a shift register;
FIG. 7 is an internal configuration diagram of a processor module and a slave processor. In the figure, 1 is the screen, 2, 2/, 2'/ are figures, and 3
and 8 is the master processor, 4 to 7 and 9 to 1
2 is a slave processor, 13 is a system control circuit, and 14 is a shift register. Patent applicant Fujitsu Limited

Claims (1)

[Claims] A raster scan type graphic display system using a plurality of processors. An image processing method characterized in that screen elements adjacent in a raster scanning direction are controlled by different processors, and the processors controlling the adjacent screen elements are more tightly coupled to each other than to other processors.