JPS5975720A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5975720A JPS5975720A JP57187198A JP18719882A JPS5975720A JP S5975720 A JPS5975720 A JP S5975720A JP 57187198 A JP57187198 A JP 57187198A JP 18719882 A JP18719882 A JP 18719882A JP S5975720 A JPS5975720 A JP S5975720A
- Authority
- JP
- Japan
- Prior art keywords
- power source
- circuit section
- circuit part
- driven
- drive circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、２系統の可．詠ヲ用いる半２ｉＩ体装置の竜
踪の構成に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides two systems of possible. This article relates to the structure of a semi-2iI body device that uses Uiwo.
従来の２系統の電源を用いる様な半４体装置にふ・いて
は、例えば第１図に示す様に比較的低い車圧によって駆
動される＠理回路部４と比較的高い酸圧によってｇ動さ
れる駆動回路部５がらなる場合、前記論Ｊ』回路部４の
出力端子７をＲｊｌ記駆動回路笥Ｓ５の入力端子９に直
接に接続すると、駆動回路のへ力電圧は比較的低い車圧
でめる為ＭＩＳ構造ではチッグ内での駆動回路の占める
面積が大きくなり１チップ当りのコストが尚くなってし
１う欠点がめった。In the case of a conventional half-quad system that uses two power sources, for example, as shown in Fig. 1, the mechanical circuit section 4 is driven by relatively low vehicle pressure, and the g If the output terminal 7 of the circuit section 4 is directly connected to the input terminal 9 of the drive circuit section S5, the force voltage of the drive circuit is relatively low. Because it is pressed, the MIS structure has the disadvantage that the drive circuit occupies a large area within the chip, resulting in an increase in the cost per chip.
葦た、従来いわゆるレベルシフト回路を用いて前記駆動
回路部５の人力竃１圧全考慮する様に工夫しようとした
場合、２系統の電源全用いる為にはいわゆるＣＭＯＳ
構造ではよく知られている様に高逼位側を基準電位と
しなけオＬばならない。これは、一般にシリコンウェハ
基板としてＮ−基板が用いられる為であるが，この場合
例えは第２図に示す様に通常の電子回路システムでは正
論理を用いている為、低電位側を接地電位とするので、
論理回路部４の低酊位側でろるＶｓ ｓｉ接地すること
になり、また駆動回路ｎＢ ５ ノ［源ｉｒ：Ｉ ＶＤ
Ｄ−１Ｅ 間またはＶＳＳ−ＶＦｉｌｎ間に接続される
ことになる。前記駆動回路部５の電源をＶＤＤ−Ｖ［間
に接続した場合には、前記駆動回路部５の電源の基鵠屯
位を接地職位にすることができず好１しくない、チだ。If you try to take into account all the voltages of the drive circuit section 5 using a conventional so-called level shift circuit, in order to use all of the two power supply systems, it is necessary to use a so-called CMOS.
As is well known in the structure, the high voltage side must be used as the reference potential. This is because an N-substrate is generally used as a silicon wafer substrate, but in this case, as shown in Figure 2, normal electronic circuit systems use positive logic, so the low potential side is connected to the ground potential. Therefore,
The low voltage side of the logic circuit section 4 is grounded to Vs si, and the drive circuit nB 5 [source ir: I VD
It will be connected between D-1E or between VSS and VFiln. If the power source of the drive circuit section 5 is connected between VDD-V[, the base position of the power source of the drive circuit section 5 cannot be set to the ground position, which is undesirable.
ｖｓＳ−ｖＩ！ｉＥ間に前記駆動回路部５の電源全接続
した場合には、前記駆動回路部５の消費■流が前記論理
回路部４の電源１４にも流れることになり。vsS-vI! When all the power supplies of the drive circuit section 5 are connected between i and E, the consumption current of the drive circuit section 5 also flows to the power supply 14 of the logic circuit section 4.
前記電源１４に特別な考慮が必いになり、やはり好−ｆ
Ｌ＜ない。Special consideration must be given to the power supply 14, which also requires favorable
L<No.
本発明は、上記欠点を除去する為になされたもので、電
源設計上で特別な制約を加えることなく、１ｆＣ，、比
較的小さなチップ面積にて大きな駆動能力を有する半導
体装置を与えること全目的とする。The present invention was made in order to eliminate the above-mentioned drawbacks, and the overall purpose of the present invention is to provide a semiconductor device having a large drive capacity of 1 fC, with a relatively small chip area, without imposing any special restrictions on power supply design. shall be.
以下、本発明の実施例全第６図を用いて詳細に説明する
。 ＶＤＤ−ＶＳＥＩ間で駆動される論理回路部４の出
カフにＶＤＤ−ＶＫＥ間で駆動されるレベルシフト回路
部１０の入力１１が接続され、前記レベルシフト回路部
１０の出力１２にＶｓｓ−ＶｇＩＩｉ間で駆動される駆
動回路部６の人力８が接続されている。前記論理回路部
４はＶＤＤ−ＶＳＳ間に接続されている電源１４で駆動
され、また高車圧を９求され玉流消費の大きい前記駆動
回路部６は、ＶＳＳ−ＶｆＥｉ間に接続される電源１５
Ｖ？−よっで駆動される・そして、前記論理回路部４と
前記回路部５を結ぶ前記レベルシフト回路部１０は、Ｖ
ＤＤ−ＶＫＥ 間にある厘列に接続された前記電源１４
と前記電源１５によって駆動されるため、前記駆動回路
部５から見ると駆動人力回圧の最大値は、前記■源１４
の出力■：圧と前記電源１５の出力゛重圧の和となる。Hereinafter, embodiments of the present invention will be explained in detail using FIG. 6. The input 11 of the level shift circuit section 10 that is driven between VDD and VKE is connected to the output of the logic circuit section 4 that is driven between VDD and VSEI, and the output 12 of the level shift circuit section 10 is connected between Vss and VgIIi. The human power 8 of the drive circuit section 6 driven by the power source 8 is connected. The logic circuit section 4 is driven by a power supply 14 connected between VDD and VSS, and the drive circuit section 6, which requires high vehicle pressure and has high current consumption, is driven by a power supply 14 connected between VSS and VfEi. 15
V? - The level shift circuit section 10 connecting the logic circuit section 4 and the circuit section 5 is driven by V
The power supply 14 connected to the line between DD and VKE
and the power source 15, the maximum value of the driving manual turning pressure from the perspective of the drive circuit section 5 is the power source 14.
Output ■: is the sum of the pressure and the output of the power source 15 (heavy pressure).
また、前記１ノベルシフト回路１０における消費電流は
一般に大きくなく、前記電源１４〉よび前記電源１５の
設訂上特に問題はない。さらに、前記屯＃１４〉よび前
記電源１５は接地磁位に対して独立し−Ｃいる為、シス
テムの接池線′ｆｃ有効に利用できると共に電源設訂も
行いやすくなる。Further, the current consumption in the one-novel shift circuit 10 is generally not large, and there is no particular problem in the design of the power supply 14> and the power supply 15. Further, since the power source 15 and the power source 15 are independent of the ground magnetic potential, the grounding line 'fc of the system can be used effectively and the power source setting can be easily performed.
以上の如く本発明では、論理回路部全駆動する電源全Ｖ
ＤＤとＶＳＥＩ 間に接続し、駆動回路部を駆動する
電源全ＶＳＳとＶＫＥ間に接続し、前記論理回路部と前
記駆動回路部を結ぶレベルシフト回路をＶＤＤとＶＦＩ
Ｆｉ間で駆動される様に接続する構成とまたため、前記
駆動回路部に加える人力重圧を大きくとれ、前記駆動回
ＶｅＪ部の素子面積を小さくすることができ、’ｔ′ｆ
Ｃ，いわゆるＣＭＯ８半梼体素子で構成した場合にも容
易に設Ｈ↑することができる。As described above, in the present invention, the total voltage of the power supply for driving all the logic circuits is
A level shift circuit is connected between VDD and VSEI, connected between all the power supplies that drive the drive circuit section, VSS and VKE, and connects the logic circuit section and the drive circuit section between VDD and VFI.
Because of the configuration in which the drive circuit is connected between Fi, a large amount of manual pressure can be applied to the drive circuit section, the element area of the drive circuit VeJ section can be reduced, and 't'f
C, H↑ can be easily installed even when it is composed of a so-called CMO8 semi-hydraulic element.
またさらにこの半導体装置を使用するシステムを設Ｈ↑
する場合にも、電源に特別な配慮を加える必９がない特
の特徴を有するものである。Furthermore, a system using this semiconductor device will be set up.
It has special features that do not require special considerations for the power supply even when the power source is used.
第１図は、従来の２系統の屯臨全用いる半導体装置の回
路図、
第２図は、駆動回路の入力電圧に工夫を加えた従来の２
系統の電源を用いる半導体装置の回路図。
第３図は１本発明の実施例の回路図である。
４・・・・・・論理回路部
５・・・・・・駆動回路部
１０・・・・・・レベルシフト回路
１４・・・・・・論理回路部電源
１５・・・・・・駆動回路蛋源Figure 1 is a circuit diagram of a semiconductor device that uses two conventional circuits.
FIG. 2 is a circuit diagram of a semiconductor device using a grid power source. FIG. 3 is a circuit diagram of an embodiment of the present invention. 4...Logic circuit section 5...Drive circuit section 10...Level shift circuit 14...Logic circuit section power supply 15...Drive circuit Egg source
Claims (2)
、第２の電源の両端に接続される駆動回路部と。 ｉｆＪ記第１と第２の電源を直列に接続しｆＣ亀源回路
の両端に接続されるレベルシフト回路とから成っていて
、前記論理回路部の出力が前記レベルシフト回路に人力
されると共に、前記レベルシフト回路の出力が前１［−
駆動回路部に人力されていることを特徴とする半導体装
置。(1) A logic circuit section connected to both ends of the first power source, and a drive circuit section connected to both ends of the second power source. ifJ, the first and second power supplies are connected in series, and a level shift circuit is connected to both ends of the fC source circuit, and the output of the logic circuit section is inputted to the level shift circuit, and The output of the level shift circuit is 1[-
A semiconductor device characterized in that a drive circuit section is manually operated.
ルシフト回路の１部１ｆＣは全部が相補型Ｍ４Ｓ構造で
あることを特徴とする請求 項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the logic circuit section, the drive circuit section, and the first section 1fC of the level shift circuit all have a complementary M4S structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57187198A JPS5975720A (en) | 1982-10-25 | 1982-10-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57187198A JPS5975720A (en) | 1982-10-25 | 1982-10-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5975720A true JPS5975720A (en) | 1984-04-28 |
Family
ID=16201808
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57187198A Pending JPS5975720A (en) | 1982-10-25 | 1982-10-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5975720A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5128450A (en) * | 1974-07-01 | 1976-03-10 | Honeywell Inf Systems | |
| JPS566534A (en) * | 1979-06-29 | 1981-01-23 | Hitachi Ltd | Level converting circuit |
-
1982
- 1982-10-25 JP JP57187198A patent/JPS5975720A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5128450A (en) * | 1974-07-01 | 1976-03-10 | Honeywell Inf Systems | |
| JPS566534A (en) * | 1979-06-29 | 1981-01-23 | Hitachi Ltd | Level converting circuit |
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