JPS5975493A - Dynamic ram - Google Patents

Abstract

PURPOSE:To prevent malfunction and to attain high speed, by starting the bootstrap of a word line when a selecting level of the word line rises to a desired level to operate a sense amplifier in an optimum timing at all times. CONSTITUTION:The RAM is provided with plural memory cell arrays M-ARY comprising an information storage capacitor CM and an address selecting MOSFET QM, plural dummy cell arrays D-ARY forming a reference voltage at readout from a memory cell, a word line WL and a dumy word line DW formed with conductive polysilicon wiring layer, and a data line DL. Then, the signal level at other end of the dummy word line DWL is received at a detecting circuit LV and when the level reaches a prescribed level, a word line selecting timing signal generating circuit phix-G having a word line bootstrap circuit is started in response to the detected output and the word line selecting signal level phix is boosted to a voltage being a power supply voltage or over.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention comprises a MOSFET (insulated gate field effect transistor) and a dynamic type transistor (AM).
(Random access memory) KIN.

Advances in semiconductor integrated circuit technology have led to miniaturization of elements and wiring formed on semiconductor substrates, leading to the development of dynamic RAM.
The storage capacity of the odor ℃ is being increased.

In dynamic type 1 (AM), 1 bit of information is stored in the form of an information storage capacitor with or without charge.
This is done by turning on the O8FET, connecting the storage capacitor to the data line, and sensing how the potential of the data line changes depending on the amount of charge stored in the storage capacitor. As mentioned above, since the device size cannot be miniaturized, the amount of charge stored in the capacitor becomes smaller or smaller. First, the readout level becomes smaller and smaller.

Therefore, in order to completely transfer charge between the storage capacitor and the stray capacitance of the data line, in other words, to realize full read and full write to the storage capacitor 9, the gate of the address selection M08 F g T The selection level of the connected word line is set to a level Kl, X, which is higher than the power supply voltage, and the address selection MOS F Fi
It is known to provide a word line selection circuit with a word line bootstrap circuit to prevent level loss due to the threshold voltage of T.

The conventional bootstrap circuit waits a fixed delay time after the word line selection operation, and then the activation 4b is performed.

However, when the word line is constructed of a wiring layer containing conductive +1 polysilicon, its resistance value is larger than that of aluminum spread legs, and the manufacturing variation in the resistance 1 is large, so it is difficult to activate the word line bootstrap circuit. Timing constraints (Ill is 9 (it-). In other words, on the address selection circuit side (adequate return) of the word line, it quickly rises to a predetermined selection level according to the selection signal level, but on the far end, This is because the rise is delayed by °C according to the time constant due to the resistance value and stray capacitance value in the word line.The rise to the selection level at the far end is due to the variation in the resistance value of the word line. There is also a wide variation in the influence of

If the bootstrap circuit is activated before the selection level at the far end of the word line has not sufficiently risen due to the delay time set above, the result will be equivalent to insufficient precharge level to the bootstrap capacitance. Therefore, the desired bootstrap effect cannot be obtained. As a result, full read and full write of the above storage capacitor are impaired (dynamic type)! , the operating margin of AM deteriorates, leading to problems such as erroneous reading or poor product yield.

An object of the present invention is to provide a dynamic RAM that can control a word line bootstrap circuit with high precision.

Another object of the present invention is to provide a dynamic type (AM) with improved operating margin.

Further objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 shows a block diagram of one embodiment of the invention.

FIG. 1 shows 1, but not limited to, approximately 256 bit memory cells each having 256 columns (rows) x 256 rows (
column) = 4 memory arrays M-ARYI to M-A) with a storage capacity of 65536 bits (approximately 64 bits)
A diagram showing the configuration of a dynamic RAM circuit arranged in LY4 is shown.

The main blocks in this figure are drawn according to their actual geometric arrangement, and each block is formed on a single semiconductor substrate, such as a silicon substrate, by well-known semiconductor integrated circuit technology.

The row address signal selection line (word line) of each memory array M-AH, Yl to M-A 几Y4 is connected to the address signal A.
. The 256 decoder output signals obtained based on ~A are closed. At this time, shorten the wiring length of the word line (
In order to reduce the propagation delay time of signal transmission on the word line, a total of two row decoders l(
, -D(3R1 to Rolo decoder R-DOR2 are each arranged between two memory arrays.

Column decoders 0-'DORI receive address signals A, .

128 decoded output signals are provided based on ~A16. This column selection decode output signal is common to the left and right memory arrays and adjacent columns in each memory array, that is, to a total of four columns.

Column decoders 0-DO2 are provided to select common data @ODL of each of the memory arrays M-A)LYI to M-A-Y4, and address signals A and A are assigned to them. For example, A8 is assigned to select left and right memory arrays, and AI is assigned to select upper and lower memory arrays.

The φyi signal generating circuit φA'SG decodes the two combinations based on the address signals A and 7, and the color 2 switch selector that switches between the adjacent columns based on the output signal φyolφ and 1 is used for each combination. It is provided in column two-switch circuits OWI to OW4.

In this way, the decoder for selecting the column of each memory array is divided into two stages: the column decoders 0-DOK1 and the column switch selector of the column switch circuit CW. The purpose of dividing the decoder into two stages is, first, to prevent unnecessary blank areas from occurring within the IC chip.

That is, the vertical arrangement interval (pitch) of the NOR gates, which have a relatively large area and carry the pair of left and right output signal lines of the column decoder 0-1) C1l, is made to match the column arrangement pitch of the memory cells. That is, by dividing the decoder into two stages, the number of transistors constituting the NOR gate can be reduced, and the area occupied by it can be reduced.

The second aim of dividing the decoder into two stages is to reduce the number of N0LL gates connected to one address signal line, thereby reducing the load on one address signal line by l-7 and increasing the switching speed. The aim is to improve

Row address buffer) (-A, DB B is nine external address signals A that are multiplexed and output one by one.

.about.A, are taken in by an internal timing signal .phi.ar generated in accordance with the address strobe signal kLk8, and are applied to each of the nine types of complementary address signals -2''-''.

Column address buffer 0-ADH receives nine external address signals A, ~A, which are multiplexed and input.
11 are taken in by an internal timing signal φaC generated in accordance with the address strobe signal OA8, and processed into nine complementary address codes 1 to 3, respectively.

In order to achieve high integration of the IC chip, in this embodiment, the internal timing signal φar'φ is sent through the multiplexer MPX which operates in response to the internal timing signal φar'φ to the common address signal line in time series. . Therefore, the complementary address signals ~a, and a, ~
Al? remains multiplexed.

That is, in the center of the figure, nine types of complementary address signal lines (column/row address lines 0R-ADL) run vertically (actually, the column decoders 0-D Oit
1) r, these address signal lines are commonly used for the row selection address signals aQ to a8 and the column selection phase address signals c to a0, so if they are provided independently. The number of wiring lines and the area occupied can be reduced by half compared to the conventional method.

The above column/row address line 01(,-Al)L&-!
,, near between the first and second columns of the memory array, are branched in both left and right directions via a changeover switch SW, and row decoders R-DOI (,1 to R-DOO20
Connected.

The above-mentioned changeover switch SW receives a complementary row address signal a.
. In this embodiment, the timing signal φ3.-a7 is passed through only. controlled by Furthermore, since the operation of the column decoder O-D 0141 itself is controlled by the column system timing signal φdf (column decoder control signal), the multiplexed complementary column address signals a, ~a17 are controlled by the complementary address signal a. . −
It is classified as 36.

00 N T -G is address strobe signal) (A
s.

In response to external signals such as OA8, main timing signals,
For example, the timing signal φact shown in the same figure
φar' φdf= φa and FIG. 3, which will be described later.

This is the timing signal generation circuit shown in FIGS. 4 and 6.

φ, -G are word line selection timing signal generation circuits, which output timing signals φ, to the above-mentioned respective row decoders) L-DOH, 1, l(, -DOH2). This timing signal φ8 is sent to the above-mentioned respective row decoders) Row decoder R-DOB,
1. The wiring for transmitting data to the R-DOH2 is formed of aluminum laminate wiring in order to reduce the delay time due to wiring resistance, and is formed approximately in the center of the figure.

φpa-G is a sense amplifier timing signal generation circuit that generates timing signals φ and a for activating the sense amplifiers SAI~4. Although not particularly limited, in order to reduce the delay time due to wiring resistance, φp
Timing signal φ is sent from a-G to sense amplifier SAI~4.
The wiring for transmitting p3 is formed by aluminum wiring.

In this embodiment, a level detection circuit LV is provided for simulating the word line selection operation. This level detection circuit LV is, for example, a memory array M-
A) (, Yl dummy word line DWL, provided on the far end side of DWL, in other words, on the opposite side of the dummy word line connected to the output terminal of the row decoder 几DORI. In other words, in the figure, the memory array ~1 The level detection circuit LV is provided above .-AH, Yl.

Next, the circuit operation in the address setting process of the above-mentioned dynamic type (AM) will be explained with reference to the timing diagram of FIG.

In accordance with the change of the address strobe signal) LAS to the low level, the timing signal S φar rises to the no-y level, causing the address buffer 1 (, -ADB
operates, and external address signal A is output. Nine types of complementary address signals ao to ag corresponding to ~AII are formed, and are sent to the row decoder l(, -DC)Ll through the multiplexer MPX and changeover switch SW by the high level of the timing 1H signal φar.

2 can be conveyed.

Next, as the word line selection timing signal φ8 rises to high level, the two row decoders
The word line selection signal formed by D'OR is transmitted to the word line WL of the memory array, and word line selection is performed.

Then, prior to the input of the next column address signals A, .about.A17, the timing signal φar is set to a low level. Further, after waiting for the word line selection operation, the timing signals φ and a become high level, and the sense amplifier SAI
.about.4 becomes active and amplifies the stored information read from the selected memory cell to the data line I)L.

Next, in accordance with the change of the address strobe signal OAS to the low level, the timing signal φdf goes to NO1, and the parfait switch MO8FET of the column decoder 0-DO)1.1 is turned on, and the decoding operation is performed according to the °C address signal. is preparing for. Then, after a little delay, the timing signal φaC rises to level 1,
Address buffer name -ADH operates to form nine types of complementary address signals a, ~a+'r corresponding to external address signals A, ~A17, and the above timing signal φ8c.
The high level of is transmitted to the column decoder 0-DOR through the multiplexer MPX. At this time, the timing signal φar has already become low level, and the multiplexer Ml)X is connected to the column address buffer 0-
Since the switch is switched to the ADB side and the changeover switch SW is off, the complementary address signals as to any are not applied to the row decoder l (, -DC) LK, and the human power of the row decoder L-DOR is as follows: The above row address signal a. -a7 is retained.

Next, when the column switch control signal φ rises to a high level, the column decoder 0-DOR2 and φ, i signal generation circuit 8G are activated.

At this time, the first complementary address signal a corresponding to address signal A8 is already applied to the column when the timing signal φar becomes high level, and the address signal 2 is already applied to the column when the timing signal φaC becomes high level. Decoder 0-DC! It is taken into 几2, and Atois signal 2 is φ
, 11g generating circuit φyi-8G.

Therefore, when the column switch control signal φ, rises to high level, almost at the same time, φ, I signal generation circuit φ, -8G baccalum switch jJ (3W 1~
Column selection timing signal φ, to 0W40 column switch selector. .

Sends φ,1.

In this way, each memory array M-ARY1 to M-A
A pair of data lines DL in RY4 are connected to each common data line pair O.
Continued to DL.

One pair of them is selected by the column decoder 0-DOI-L2 and connected to the input terminal of the data output bassoon A D (JB) and the output terminal of the data output bassoon A D (JB).

FIG. 6 shows the memory array M-AI (, Yl, sense amplifier SA1. row decoder R-1) OI-4.
1.

2 is a schematic diagram of a level detection circuit LV, a word line selection timing signal generation circuit φ, -8G, and a sense amplifier timing signal generation circuit φ, a-G. FIG.

In this embodiment, the memory cells are arranged in a so-called two-point manner, although this is not particularly limited.

The memory cell is constituted by an information storage capacitor CM and an address selection MO8FE'l'QM. Also, when reading information from a memory cell, the sense amplifier 5
The dummy cells that provide the °C reference voltage for AI-n are MO8FETQd for selection and MO8li for discharge.
``ETQdo'' and a constant capacitor CD whose capacitance is approximately half that of the information recorder CM.

A dummy cell is connected to a pair of data lines in order to apply a reference voltage to the sense amplifier via the other data line once a memory cell coupled to the pair of data lines is selected. C word aWLn provided with 712 dummy cells and a pair of dummy word line skins.

I) Although the WL is not particularly limited, in this embodiment, in order to reduce the delay time due to wiring resistance, the WL is structured as described below.

That is, the word line and the dummy word line are composed of a conductive polysilicon layer and a metal silicide formed thereon, for example, a compound of a metal such as molybdenum and silicon.

The pair of dummy words DWL, DWL are electrically coupled to the level detection circuit LV.

By doing this, the level detection circuit LV is always supplied with a signal from the row decoder (each issue for selecting a dummy cell) when a memory cell is selected.

As will be explained in detail later, the word line selection timing signal generation circuit φknee G and the sense amplifier timing signal generation circuit φpa-G receive the output signal from the level detection circuit and output the timing signals φ and φ, respectively.
generate a.

FIG. 3 shows a circuit diagram of an embodiment of the word line selection timing signal generation circuit φ, -G. In the explanation below, M08Fl13T is an n-channel MO8F
ET is used, and the MOSFET with the bone mark is a MOS with a lower threshold voltage than the ET.
It is FET.

Row related timing signal φ83. Power supply voltage side MO
8FETQ, and internal address strobe signal 1 (
, suitable ground potential (111M OS F E
TQ.

, MO8FE'l'Q4 receives its output signal, and internal address strobe signal 1 (
, AS2, the precharge MO8Fl CO'rQ3 receives the timing signal φ83. construct a delay circuit. The drain output of this MO8FETQ is the ground potential side output M U S F F,T QCs,Q+41
It will be stamped on the gate.

The timing signal φ88. 408FF, TQ.

through the capacitor 0. supplied to one end of the This M.O.
Gate of 8FET capacitor C1 and power supply voltage V. 0, a precharge M 08
Between the drain of F'ETQ4, that goo)FCN
, Gentunsho V. A MO8FETQ to which 0 is applied is provided.

10,000, power supply voltage 41111 output MO8FBTQ, □, Q
, 2, the gates of the capacitors 0. connected to one end of the This MO8FETQ, □ and the above N U S F E
The other end of the capacitor C1 is connected to the connection point with '11'Q +s. Further, a power supply voltage ■ is applied to the gate between one end of the capacitor C1 and the timing signal φxb. M O8F” E T Q s with C applied
and an fviO8FETQ whose gates are marked with timing signals φ,' are provided in series. This MOS 1" ETQ8 is activated when one end of the capacitor 0.0 is brought to a high voltage by its bootstrap operation (C
The breakdown voltage of MO8FgTQO should be increased. That is, in the dynamic RAM of this embodiment, in order to increase the storage capacity as described above, the MOSFET is
Since ETs are miniaturized and formed, and the withstand voltage is lowered, such circuitry measures are taken. This will be explained later in the table below. MO8I where 0 is applied again! ″
The same reason applies to E T Ql4-Qle, etc.

Well, by miniaturizing the MO8Fl'iT mentioned above, M O5
If FETQ is operated bidirectionally, in other words, if MO8FETQi is used for the precharge operation of Ivl08FETQ7 as in the conventional circuit, the conguctance characteristic due to hot carriers will deteriorate again. Therefore, in this embodiment, the precharge M OS k' E
T Qe is provided. This MO8FBTQe turns on faster than the signal passed through MO8FETQ, so it is passed through MO8FETQ again. A precharge operation is performed to the above MO8F, and the above MO8F
ETQ? (Can be done. MO8FETQ like this)
6 is also provided for the same reason in the level detection circuit LV in Figure 4, which will be described later.

Also, between the other end of the capacitor O and the internal timing signal, there is an M08FETQ which receives the timing signal φ8' for a reset operation. There are also

Also, the above M O8F E T Qlz and M(IIF
Word line selection timing signal φ8 is formed from the connection point with ETQI4. Further, one end of the bootstrap capacitor OB is connected to this output terminal for the bootstrap operation.

The timing code φ86. is connected to the other end of this bootstrap capacitor OB. The above-mentioned timing signal φ8' and timing φxb are connected to the level detection circuit LV, which will be explained next.
are formed respectively by

FIG. 4 shows a circuit diagram of an embodiment of the level detection circuit LV.

The level detection circuit LV is roughly divided into a level detection section that detects the level at the far end of the dummy word lines DWL, DWL, a timing generation circuit that receives the output and forms a timing signal φ', and a timing signal φ, ' is received as the timing signal φ for the above bootstrap operation.
and a timing generation circuit forming xb.

The level detection section above uses the power supply voltage ■. . A plurality of MO8" ETs are provided on the side and are connected in series, although there is no particular limitation.
E T (Lo, Qt
, and 1, mtt et al. MO8FETQ, , Q2. (r)7
-S [commonly provided reset MOSF” E
It consists of TQ22. M O8 in the above series configuration
F” E T Qls + Ql.

and M08FETQ,. , Q2. At the gate of
The level at the far end of each dummy word line DWL, DWI is commonly supplied. In addition, the above M Os F E TQ
, 2 has the internal address strobe described above.

Signal RA81 is applied. M in the above series form
OS FE T Q +s or Q21 and MO8FE
TQ, 227:'Q, a constitutes a delay (b) path of the timing signal generating circuit (φ8') as described below.

This delay circuit is configured to raise the timing signal φ' at a desired time 1 m after the potential at the far end of the selected dummy word line among the pair of dummy word lines rises to a desired value. Use 1~・ru.

In other words, the time from when the potential at the far end of the dummy word line reaches a desired value to when the timing signal φ8' rises is mainly determined by this delay circuit. Specifically, the constants of MOS F' gT Ql; 1 to Qh4 are set so as to obtain an appropriate delay time for the timing signal φt to rise.

This level detection output is transmitted to the next timing generation circuit (φ). This timing generation circuit (φe′)
The basic circuit configuration is the same as the circuit of the 31st embodiment. However, in the timing generation circuit (φ,'), compared to the circuit shown in FIG. φxsp is delayed by a resistor, and internal address strobe signal RA81 is used as a reset signal for capacitor C2.
(・In addition, since the output level of the u1 timing signal φ8' can be set to the power supply voltage V.0 level, the bootstrap capacitance dOB and the MOS FET for % breakdown voltage are reduced. What is different is that it is unnecessary.

The output signal φ8' of this timing generation circuit is the third
It is used as the timing signal φ8' in the figure, and
It is used as start-up number 4B of the next timing generation circuit (φxb).

The circuit configuration of this timing generation circuit (φ8') also uses a circuit similar to that shown in FIG. 3 and the timing generation circuit (φ8') described above, so a detailed explanation thereof will be omitted.

The timing generating circuit (φxb) of this embodiment is also used as a starting signal for the bootstrap operation, which is obtained by delaying and inverting the timing signal φa'. Further, a timing signal φxb' for activating the sense amplifier 8A is formed by separately provided output MO8FETQ, Qll+. The delay circuit (sense amplifier timing signal generation circuit φ-G) receiving this timing signal φi generates the timing signal φ,3 which activates the a sense amplifier 8A.

In this way, the timing signal φxb as one word for starting the bootstrap operation and the timing signal φxb' for activating the sense amplifier are separated into separate circuits, that is, MOS F' ET Q4! l
, Q+II and MOSFETQ,it,Qs. As a result, the negative i'uj of each circuit becomes small. In this first step, M of each circuit, OS l! ”
The size of ET may be small. It is also possible to increase the operating speed of each (@path).

The operation of the circuits shown in FIGS. 3 and 4 will be explained with reference to the timing diagram shown in FIG. 5.

Row address strobe 1g RA supplied from outside i
As S falls to low level, internal address strobes (%) LAS1 and RAS2 fall to low level. Due to the fall of the low level -\ of this internal address strobe signal RASI, there is a slight delay.
The timing signal φX3p rises to high level.

In the circuit of FIG. 3, this timing signal φxsp'
℃, MO8F”g before reaching the high level of
MOSFETQ is installed at the gate of TQ.

Churn-up has already been done through ℃, so MO
SFETQ is also turned on. I got angry again,
The above timing signal φ85. As the voltage rises to the NO level, the capacitor C1 is charged up and the MOSFETQ, .

Q10 is turned off. At this point, MOSFETQ
Due to the self-bootstrap effect due to the gate capacitance between the channel and the gate of 7, precharging is performed such that the loss tc<capacitor C. At this time, MU8. )'ETQ+, Q4 through which the inverted signal of the timing signal φ is delayed and transmitted to the gate of Msp081"'ETQ+s-Q10, so these MOSFET Q u *
Q+5 is also turned on. Therefore, its output timing signal φ is MOS FET Q1
It is at a low level according to the conductance ratio between 0 and MUSFBTQ+4°Qn.

As soon as the drain output of M 08 F g T Q□ falls to low level, M 08
FETQ+s+ Q and Ill are both turned off, and through MOSFETQs, -CMO8FE
Since the gate of TQ is also set to low level, this MO8
FETQy is also turned off. As a result, the capacitor 0. The timing signal φ5. It also prevents the flow from flowing back to the side. Therefore, the gate voltage of MO8FETQ, , Q, 2 is the power supply voltage V. . Since the word line selection timing signal φ, which is the output signal, is set to a high level above the power supply voltage V.

Rise to 0.

Furthermore, in the circuit of FIG. 4, the timing signal φ
Before sp rises to high level, M OSF ET Q 2t and H M OsF
Note that charge-up has already been done through ET Q, 2, MUSFBTQ2A and MO8FETQ41, MOS FET Q 2? and U
MO8FBTQ,2 is turned on. Therefore, as the timing signal φ rises to the high level, the MO8FETQ2. The capacitor c2 is charged up through the MO8FgT Qso
, Qs+ are turned on. However, due to the resistor, the timing signal φxsp is delayed and rises slowly. At this time, M08FETQ2. channel,
Due to the self-bootstrap effect due to the gate capacitance between the gates, precharging of the capacitor with no level loss is performed.

Therefore, the output signal φ8' is M U S F
ET Q+n is set to a low level according to the conductance ratio with QCs. Note that in order to reduce the current consumption, the conductance of these MO8FETQ, . . . , Q is set to a relatively small value.

Then, as shown by the broken line in FIG. 5, MO8FETQ receives the selection level of the far end of the dummy word line that rises slowly
18- Q10 or M O8F ET Q 211
.

When any of Q21 is turned on, MO8FE
TQ, , is turned on. This MO8FETQts
When the drain output of MO falls to low level,
8FETQu and Qsa are both turned off, and MOS k is turned off by turning off MO8FBTQ2!1.
'ET Qh? When the gate of MO8FETQ27 is also set to low level, MO8FETQ27 is also turned off.

This prevents the bootstrap voltage formed by the capacitor 02 from flowing back through the MO8FE'l"Q27 and toward the timing signal φxsp. Therefore, the MO8F"gTQ*. , the gate voltage of Q31 is the power supply voltage V. Since the timing signal φ8', which is the output signal, is set to a high level higher than 0, the timing signal φ8' is a power supply type Ifv.
Stand up to cc. By rising this timing signal φ8' to high level, MO8FETQa in FIG.
, Q+. is turned on, and the next timing generation circuit is activated.

In accordance with the rise of the timing signal φ8' to the high level, MO8F B T is again turned on.
Capacitor O9 is charged up through Q42, and MO8FETs Q4fl to Q4g are turned on. At this time, M (J S F ETQA
Due to the self-bootstrap effect caused by the gate stitching between the channel and gate of T, the capacitor C is precharged without loss of level. At this time, MO
The inverted signal of the timing signal φ8' through 8k''B '1' Qse -Qs is delayed'''CMO8FBTQ4
．． ~Qs+ gate, so these M 0
8 FET Q4*~Q51 is also in the on state 7t"
'(The output timing signal φ
xh, φxb' are M 08 k' E T Q4?
(Q48) and M(JS F E, 'l' Qsa (
(=J!+) is at a low level according to the conductance ratio.

Then, when the timing signal obtained from the drain of C, M 08 FET Q, go is delayed and falls to low level, MOS FET Q 40~Q5
1 are both turned off and M O8F' E
Through T Q4n M O:S k” gT Q B
This M O5F gate is also set to the lower level.
ET Q 42 is also turned off. By this first step, the bootstrap voltage l formed by the capacitor 03 is
Upper or M O8F ETQ4. ℃ timing signal φ
This prevents the flow from flowing back to the 8' side.
OS FET Q46-Q4. The gate voltage is a power supply type JEV. 0, the timing signal φ8. is the power supply voltage ■. .

stand up until

Incidentally, since the timing signal φ oil is set to a low level before the timing signal φxb rises to a high level, the MOS that is already in the on state in FIG.
F, ET Qo and M OSF ET Q! 1 to set the gate voltage of -CMO8FETQo-Q+z to low level and turn it off. Also, M (J8F E
℃ capacitor C1 is reset through T Q +n.

Once, the timing signal φxb rises to high level 1, drives the bootstrap capacitor -IOB, and sets the word line selection timing signal φ8 to the power supply voltage V. . When raising to a high level above, MO8FETQo,Q
Since +2 is turned off, the bootstrap voltage does not leak to the power supply voltage Vce side.

In addition, a timing signal φxb/cormorant formed in the same manner as above, a predetermined delay circuit (sense amplifier timing signal generation circuit φpa-G: not shown), and a circuit configuration similar to the timing signal generation circuit (φ8.) described above, for example. The timing signal φ activates the sense amplifier 8A through the delay circuit of
, a.

In this embodiment, the selection level at the far end of the word line is seamulated using a similar dummy word line t2. However, in the past, the word line bootstrap operation can be started at the optimum timing according to the selection state of the word line, in other words, as soon as the selection level of the word line rises to a desired level. The bootstrap voltage of one word line can be sufficiently increased. That is, the parasitic capacitance coupled to the selected word line and dummy word line, respectively, is charged by the timing signal φ and fluctuates (decoding) L.
-Do) When the potential on the far end side of the word line and dummy word line reaches the desired value with respect to L, the word line bootstrap operation is activated, so Furthermore, since the word line and the dummy word line are formed at the same time, even if there is variation in the rise of the selection level due to the above-mentioned variation in the resistance value of the word line, Since the selection level at the far end of the word line is simulated using a similar dummy word line, it is possible to follow this and activate the bootstrap operation.This makes it possible to prevent malfunctions due to variations in manufacturing conditions, etc. It is possible to obtain a dynamic RAM that is difficult to use.

In addition, since the word line bootstrap operation timing can be controlled with high precision, there is no need to take into account variations in the rise of the word line to the selection level and set a time margin to absorb it. It is also possible to improve the operating speed.

Further, since the operation timing of the sense amplifier 8A is also determined based on the simulation result of the selection level at the far end of the word line, the sense amplifier 8A can be operated at the optimum timing according to the word depth bootstrap operation. That is, the sense amplifier can always be operated at a desired time after starting the word line bootstrap operation. Therefore, the sense amplifier can be operated when the potential difference between a pair of data lines becomes sufficient to operate the Kerr sense amplifier according to the information stored in the memory cell. Therefore, it is possible to always operate the sense amplifier at the optimum timing, it is possible to make malfunctions less likely to occur, and it is possible to make the sense amplifier more reliable.

As mentioned above, it is possible to raise the bootstrap rough voltage of the word line to a sufficiently high level, making it possible to fully read and write the memory cell. Since it is possible to compensate for the decrease in the amount of accumulated charge in the memory cell due to the increase in memory cell density, it is possible to improve the operation 1'-gin and also to increase the shield manufacturing yield. can be operated at the optimum timing, so it is possible to fully read or write memory cells with WQ.
Moreover, memory speed can be increased.

The present invention is limited to the above embodiments.

The layout configuration of the memory array and the layout configuration of its peripheral circuits can take various embodiments.

Further, the specific circuit configuration thereof may be of any type as long as it performs the same operation as the circuit of the above embodiment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram for explaining the address setting operation, and FIG. 3 is a block diagram showing an embodiment of a word line selection timing generation circuit. 4 is a circuit diagram showing an embodiment of the level detection circuit; FIG. 5 is a complete timing diagram illustrating the operation of the embodiment circuit of FIGS. 3 and 4; FIG. 1 is a schematic diagram of a memory array and its peripheral circuits. M-ARYI~4...Memory array, SAI~4...
・Sense amplifier, p-ARYI~4...Dummy cell array, R-ADB...Row atomic buffer, C-A
DB...Column address buffer, a-pctt...
・Row decoder, 0-1) OR...column decoder,
08W1-4...Column switch, MPX...Multiplexer, φ, -8G...φyi language and era generation circuit IJ 1) IB...Data output buffer, L) OB...Data output buffer , SW...changeover switch, φ,
-G...Word line selection timing signal generation circuit, LV
. . . Level detection circuit, φ, a-G . . . Sense amplifier timing signal generation circuit. Agent Patent attorney Usui 1) Toshiyuki ・11.7 so (-J Fig. 1 gss cAs Fig. 2 φ7L] Fig. 3 Fig. 4 Fig. 5

Claims (1)

[Claims] 1. Information storage capacitor and address selection MO8FET
a plurality of memory cells, a plurality of dummy cells that form a reference voltage when reading from the memory cells, and input/output terminals of the plurality of memory cells and one dummy cell arranged in the same row, respectively. A plurality of connected data lines, a word line formed of a wiring layer containing conductive polysilicon, and a dummy cell connected to the gate of an address selection MO8FET of a memory cell arranged in the same column, and a dummy cell arranged in the same column. a memory array including a dummy word line connected to the gate of an address selection MO8FET and formed of a wiring layer containing conductive polysilicon; and a word supplying a selection signal to one end of the word line and the dummy word line. lfB selection and selection circuit, a level detection circuit that receives the signal level of the other store on the dummy word line and detects that the level has reached a predetermined level, and is activated upon receiving the detection output of this level detection circuit, A dynamic RAM 02 characterized in that it includes a word line bootstrap circuit that boosts the word line selection signal level above the power supply voltage.The level detection circuit detects the signal level at the other end of the dummy word line, A plurality of M having relatively small conductance characteristics commonly received at the gate of the gate and arranged in series.
Dynamic type AM03 according to claim 1, comprising an OSFET, one end of the series MOSFET is connected to a power supply voltage terminal, and a level detection output is obtained from the other end. Dynamic FI) LAM0 according to claim 1 or 2, characterized in that the output signal of the level detection circuit is delayed and also used as an activation pulse of the sense amplifier.