JPS597344A - Liquid crystal dispaly device of active matrix type - Google Patents

Liquid crystal dispaly device of active matrix type

Info

Publication number
JPS597344A
JPS597344A JP57114969A JP11496982A JPS597344A JP S597344 A JPS597344 A JP S597344A JP 57114969 A JP57114969 A JP 57114969A JP 11496982 A JP11496982 A JP 11496982A JP S597344 A JPS597344 A JP S597344A
Authority
JP
Japan
Prior art keywords
liquid crystal
display device
crystal display
thin film
active matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57114969A
Other languages
Japanese (ja)
Other versions
JPH06100745B2 (en
Inventor
Toshiyuki Misawa
利之 三澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP11496982A priority Critical patent/JPH06100745B2/en
Publication of JPS597344A publication Critical patent/JPS597344A/en
Publication of JPH06100745B2 publication Critical patent/JPH06100745B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136213Storage capacitors associated with the pixel electrode

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  • Physics & Mathematics (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To eliminate the adverse influence of the parasitic capacity of the thin film transistors provided at the points of intersection between gate lines and data lines and to obtain a liquid crystal display device having high reliablity, by maintaining said parasitic capacity at a specified ratio or below to the sum of the capacity values of a capacitor for charge holding and a liquid crystal. CONSTITUTION:A gate line 416, a data line 419, a common electrode 417, a liquid crystal driving electrode 420, thin film transistors (TRs) 412-414, contact holes 421-422, and a capacitor 423 for charge holding shown by obliquelines are formed on a liquid crystal display device of a matrix type. The parasitic capacity of the TRs 412-414 is maintained at a prescribed ratio or below to the sum of the capacitor for charge holding and the liquid crystal in order to prohibit lighting of the liquid crystal when the data signal is zero. The liquid crystal display device having reliability is thus obtd.

Description

【発明の詳細な説明】 本発明は、シリコン薄膜による薄膜トランジスタを用い
てアクティブマトリクス基板を構成したアクティブマト
リクス型液晶表示装置〜に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an active matrix liquid crystal display device in which an active matrix substrate is constructed using thin film transistors made of silicon thin films.

第1図1b+にアクティブマ) IJクス型液晶表示装
置のブロック図を示す。同図において、101〜104
はゲート線、105〜107 rj:データ線、108
〜110等は画素である。また、111はゲート線駆動
装置、112はデータ線駆動装置である。第1図1b+
は108〜110等の画素の構成を示す図である。第1
図1b1において、】13はゲート線、114はデータ
線、115はスイッチンク用トランジスタ、118,1
19はトランジスタ115の寄生容量、116は液晶、
120は液晶駆動電極、117は液晶116の共通電極
である。第1図Cα)のアクティブマトリクス型液晶表
示装置を用いて画像表示を行う場合、通常、ゲー(線1
01,102,103゜。。に(l−1:第1図1cl
の121.122,123のごとき信号が印加され、一
方、データ線105,106゜、。にはデータ信号12
4が各々の画素位置に応じて時分割サンプリングされて
印加される。即ち各画素は点順次駆動される。第1図f
clにおいて125は画素の共通電極電位であり、この
とき液晶表示体セル116は交流駆動されている。
FIG. 1b shows a block diagram of an active matrix IJ type liquid crystal display device. In the same figure, 101 to 104
is gate line, 105-107 rj: data line, 108
~110 etc. are pixels. Further, 111 is a gate line driving device, and 112 is a data line driving device. Figure 1 1b+
is a diagram showing the configuration of pixels 108 to 110, etc.; 1st
In FIG. 1b1, ] 13 is a gate line, 114 is a data line, 115 is a switching transistor, 118, 1
19 is the parasitic capacitance of the transistor 115, 116 is the liquid crystal,
120 is a liquid crystal drive electrode, and 117 is a common electrode for the liquid crystal 116. When displaying an image using the active matrix liquid crystal display device shown in Fig. 1 Cα), the game (line 1
01, 102, 103°. . (l-1: Figure 1 1cl
Signals such as 121, 122, 123 are applied to data lines 105, 106°, and so on. has data signal 12
4 is time-divisionally sampled and applied according to each pixel position. That is, each pixel is driven point-sequentially. Figure 1 f
In cl, 125 is the common electrode potential of the pixel, and at this time, the liquid crystal display cell 116 is being driven with alternating current.

第1図+(11のアクティブマ)・リクス型液晶表示装
置は、ゲー来、単結晶シリコン基イJy、上に形成され
ており、スイッチング用トランジスタ115は単結晶M
 (’I 8 トランジスタで形成されてし)だ。第2
図1b+は従来の準結晶シリコン基板上に形成された画
素の構成を示す図である。第2図(α)において113
νまゲート線、114はデータ線、J16は液晶、11
7は共通電極、201は単結晶MO8)ランジスタ、2
02は電荷保持用キャパシタ、203は単結晶シリコン
基板、204,205はM’OSトランジスタの寄生容
量をそれぞれ示す。
The (11 active polymer) type liquid crystal display device in FIG.
(It is formed by 'I 8 transistor). Second
FIG. 1b+ is a diagram showing the structure of a pixel formed on a conventional quasi-crystalline silicon substrate. 113 in Figure 2 (α)
ν gate line, 114 data line, J16 liquid crystal, 11
7 is a common electrode, 201 is a single crystal MO8) transistor, 2
02 is a charge holding capacitor, 203 is a single crystal silicon substrate, and 204 and 205 are parasitic capacitances of M'OS transistors.

液晶116の容量値をCLC! 、電荷保持用キャパシ
タ202の容量値をCH116生容量205の容量値を
C81rゲート線駆動信号の振幅をVaとすると、ゲー
ト線駆動信号がハイ→ローと立ち下がる時に、第2図f
(L+の液晶駆動電極206の電位は、だけ低下させら
り、る。
CLC the capacitance value of liquid crystal 116! , the capacitance value of the charge holding capacitor 202 is CH116, the capacitance value of the raw capacitance 205 is C81r, and the amplitude of the gate line drive signal is Va, then when the gate line drive signal falls from high to low, as shown in FIG.
(The potential of the L+ liquid crystal drive electrode 206 is lowered by .

面積が20000〜30000μ7222  である副
索において、にLC! 、 C;Hlの値はそれぞれC
L(! = 0.1〜帆2PF。
In the accessory cord whose area is 20,000 to 30,000 μ7222, LC! , C; The value of Hl is C
L(! = 0.1~Sail 2PF.

CH1=4〜IQPFであシ、単結晶シリコンM (l
 8 トランジスタに対する駆動電圧VaはVo = 
l(1〜+5Vである。従って、従来のシリコン基板上
に形成したアクティブマトリクス型液晶表示装置では寄
生容量C81が液晶容1dcLcと同等又はそit以上
であっても△V、は十分小さく抑えられていた。ところ
で、シリコン基板上に形成されたアクティブマトリクス
型液晶表示装置は、 「11シリコン基板の面積に限度があるため、得られる
表示装置の寸法にも制限が加えられる。即ち大型化が困
難である。
CH1=4~IQPF, single crystal silicon M (l
8 The driving voltage Va for the transistor is Vo =
l (1 to +5 V. Therefore, in a conventional active matrix liquid crystal display device formed on a silicon substrate, even if the parasitic capacitance C81 is equal to or more than the liquid crystal capacitance 1dcLc, ΔV can be kept sufficiently small. By the way, active matrix liquid crystal display devices formed on silicon substrates are difficult to increase in size due to the limited area of the silicon substrate. It is.

(2′Iシリコン基板の単価が高いため、得られる表示
装置の製造コストが高くなる。その上、将来、製造工程
が簡単化される可能性は小さく、製造コストの低下は望
めない。
(Since the unit price of the 2'I silicon substrate is high, the manufacturing cost of the resulting display device increases. Furthermore, there is little possibility that the manufacturing process will be simplified in the future, and no reduction in manufacturing cost can be expected.

13+シリコン基板が不透明であるため、透過形の液晶
表示装置を作ることができず、表示のコントラストが悪
い。
Since the 13+ silicon substrate is opaque, it is impossible to make a transmissive liquid crystal display device, and the display contrast is poor.

等の欠点を有する。とれらの欠点を改善し、安価で、寸
法が大きく、表示性能の優れたアクティブマ) IJク
ス型液晶表示装簡を得るため、最近、薄膜トランジスタ
をスイッチング用トランジスタとして用い、透明基板上
にiIT:i素を形成[7たマトリクス型液晶表示装置
σの開発が進められている。薄膜トランジスタを用いた
マトリクス型液晶表示装置の画素の4771成図を第2
図1b+に示す。2112図Cb1において、]、 I
 3はゲート線、114はデータ線、116なま液晶、
117は共通’flイ1極、211は光膜トランジスタ
、212は電荷保持用キャノ々シク、213にL共通市
;極又は隣接する画素のゲート線に接続される端子、2
14及びj15は薄膜トランジスタ211の寄生容i、
216&よ液晶を、駆動する電極をそり、それ示す。第
2図1b+において、液晶116の容量値をCLO、電
荷保持用キャノくシタ212の容量値をan、、′#生
容量215の容量値を自2 、ゲート線駆動信号の振幅
をVGとすると、ゲート線駆動信号立ち下がり時におけ
る第2図1b+の液晶駆動電極216の電位低下tit
、” (:、C2 △V2−−−−−−−−−−−−−−−−・vGoo、
(21CIhC4−CH24−C,C2 となる。
It has the following disadvantages. Recently, in order to improve these drawbacks and obtain an IJ type liquid crystal display device that is inexpensive, large in size, and has excellent display performance, thin film transistors have been used as switching transistors and IITs have been fabricated on transparent substrates. Development of a matrix-type liquid crystal display device σ that forms an i-element is progressing. The second 4771 diagram of a pixel of a matrix type liquid crystal display device using thin film transistors is shown below.
Shown in Figure 1b+. 2112 In Figure Cb1, ], I
3 is a gate line, 114 is a data line, 116 is a raw liquid crystal,
117 is a common terminal, 211 is a photo-film transistor, 212 is a charge holding capacitor, 213 is an L common terminal; a terminal connected to a pole or a gate line of an adjacent pixel;
14 and j15 are the parasitic capacitance i of the thin film transistor 211,
216 & 2. The electrodes that drive the liquid crystal are shaved and shown. In FIG. 2 1b+, let CLO be the capacitance value of the liquid crystal 116, an be the capacitance value of the charge holding capacitor 212, an, 2 be the capacitance value of the raw capacitor 215, and let VG be the amplitude of the gate line drive signal. , the potential drop tit of the liquid crystal drive electrode 216 in FIG. 2 1b+ at the falling edge of the gate line drive signal.
,” (:, C2 △V2−−−−−−−−−−−−−−−・vGoo,
(21CIhC4-CH24-C,C2.

透明基板上にN膜トランジスタ列を形成1.たマトリク
ス型液晶表示装置は透過形で用いられることが前提とな
るため、光を透過しないシリコン薄膜を用いて作られる
電荷保持用キャパシタはその面積ができる限シ小さいこ
とが望ましい。従って、式12+において、CH2の値
はI:LOと同等又はそh以下に設定されるのが通常で
ある。第3図Cal 、 Ibl f用いて、ΔV2が
液晶表示及び液晶表示体に及ぼす悪影響を説明する。第
3図1711において、301は、第4図1(Zlの1
14に印加されているデータ信号であシ、い丑データ信
号はゼロである。)302は、第4図falの113に
印加されているゲート線駆動信号であり、その周期はT
、振幅はvOである。このとき、第2図1b+の液晶駆
動電極216の電位は第3図fcxlの303のように
変化する。即ち、ゲート線駆動信号302の立ち下がり
と同時に216の電位は共通電極電位304から△V2
だけ低下し、次にゲート線駆動信号が7・イとなってデ
ータの書き込みが行われる寸で保持される。ただし、こ
の間液晶116のリーク市、流により216の電位は共
通電極電位304に近ずくように変化する。結局、液晶
116には一定の実効電圧V[が加わることに々す、V
Eが液晶のしきい値電圧以上であれば、データがゼロで
あるにもかかわらず画素が点灯することになる。VLC
,の値は、△v2が大きい程犬きく、丑だ、△V2は式
+21で力えられるため寄生容量C82が大きい程大き
い。第2図1b+にもう一つの例を示す。第2図1b+
において、305はデータ線114に印加されるデータ
信号であり、共通電極電位306に関して上下対称な交
流信号である。307はゲート線駆動信号であり、その
周期はT、振幅はVGである。308は、液晶駆動電極
電位の変化を示しており、309は共通電極電位である
。ゲート線駆動信号307が)・イとなった時点でその
時のデータ信号が液晶駆動電極216Vc書き込まれる
。その後、−ゲート線駆動信号307が立ち下がると同
時に液晶側動電wL216の電位は△V2だけ低下し、
再びゲート線駆動信号がハイとなってデータの書き込み
が行われる寸で電位を保持する。ただし、この保持期間
中液晶116及び薄膜トランジスタ2】】のリーク電、
流により、液晶駆動電極216に貯えられた電荷は徐々
に放電される。第3図1b+において、308の波形は
、共通電極′「b−位309に関してその上下で面積は
等しくなく、共通電極電位よりvOだけ電圧の低い電位
310に関してその上下で面積が等しい。即ち、308
は完全な交流波形でなく、−vOだけ直流分が重畳され
た波形となっている。このため、第2図1b+の液晶1
16に直流電圧vOが印加され続けることとなり、液晶
の寿命は著しく劣下させられる。
Forming an N-film transistor array on a transparent substrate 1. Since the matrix type liquid crystal display device is assumed to be used in a transmission type, it is desirable that the area of the charge retention capacitor made using a silicon thin film that does not transmit light is as small as possible. Therefore, in equation 12+, the value of CH2 is usually set equal to or less than I:LO. The adverse effect of ΔV2 on a liquid crystal display and a liquid crystal display body will be explained using FIG. 3 Cal and Ibl f. In FIG. 3 1711, 301 is 1711 in FIG.
The data signal applied to 14 is zero. ) 302 is a gate line drive signal applied to 113 in fal in FIG. 4, and its period is T.
, the amplitude is vO. At this time, the potential of the liquid crystal driving electrode 216 in FIG. 2b+ changes as shown in 303 in FIG. 3 fcxl. That is, at the same time as the gate line drive signal 302 falls, the potential of the gate line 216 changes from the common electrode potential 304 to △V2.
Then, the gate line drive signal becomes 7.a and is held at the point where data writing is performed. However, during this time, the potential of the liquid crystal 216 changes to approach the common electrode potential 304 due to leakage and flow of the liquid crystal 116. In the end, a constant effective voltage V[ is applied to the liquid crystal 116, V
If E is equal to or higher than the threshold voltage of the liquid crystal, the pixel will turn on even though the data is zero. VLC
The value of , becomes larger as △v2 becomes larger. Since △V2 is determined by the formula +21, the larger the parasitic capacitance C82 is, the larger it becomes. Another example is shown in FIG. 2 1b+. Figure 2 1b+
, 305 is a data signal applied to the data line 114, which is an AC signal that is vertically symmetrical with respect to the common electrode potential 306. A gate line drive signal 307 has a period of T and an amplitude of VG. 308 indicates a change in the liquid crystal drive electrode potential, and 309 is a common electrode potential. When the gate line drive signal 307 becomes ).a, the data signal at that time is written into the liquid crystal drive electrode 216Vc. After that, at the same time as the -gate line drive signal 307 falls, the potential of the liquid crystal side electrodynamic wL216 decreases by ΔV2,
The potential is held until the gate line drive signal becomes high again and data is written. However, during this holding period, the leakage current of the liquid crystal 116 and the thin film transistor 2]
Due to the current, the charges stored in the liquid crystal drive electrode 216 are gradually discharged. In FIG. 3, 1b+, the waveform 308 has an unequal area above and below the common electrode 309, and an equal area above and below the common electrode 310, which is lower than the common electrode potential by vO.
is not a complete AC waveform, but a waveform in which a DC component is superimposed by −vO. For this reason, the liquid crystal 1 in FIG. 2 1b+
Since the DC voltage vO continues to be applied to the liquid crystal 16, the life of the liquid crystal is significantly shortened.

本発明は上述の欠点を改善するものであり、その目的は
、薄膜トランジスタのゲー ト・ソース間及びゲート・
ドレイン間に存在する寄生容量が液晶表示装置の表示性
能に与える悪影響を除き、高信頼性を有するアクティブ
マトリクス型液晶表示装置を提供することにある。寸だ
、本発明の要旨は、第2図1711において、寄生容量
214−及び215の容量値が、電荷保持用キャパシタ
212及び液晶116の容品、値の和、即ち一画素分の
画素容lt1.値に対して一定の比率以下になるように
アクティブマトリクス型液晶表示装置を作ることにある
The present invention aims to improve the above-mentioned drawbacks, and its purpose is to improve the gate-source and gate-source connections of thin film transistors.
It is an object of the present invention to provide an active matrix type liquid crystal display device having high reliability by eliminating the adverse effect that parasitic capacitance existing between drains has on the display performance of the liquid crystal display device. The gist of the present invention is that in FIG. 2 1711, the capacitance value of the parasitic capacitances 214- and 215 is the sum of the capacitance values of the charge holding capacitor 212 and the liquid crystal 116, that is, the pixel capacitance for one pixel lt1. .. The objective is to manufacture an active matrix type liquid crystal display device so that the value is below a certain ratio.

以下、本発明の詳細な説明する。第4しICa、+ 、
 l/11に本発明の実施例を示す。第4図1alは透
明基板上にれル膜トランジスタを形成したマトリクス型
液晶表示装置の一画素を上から見た図である。同図にお
いて、416はゲートヤ丁!、41.9幻、データ線、
417は共通電極又は隣接する画素のデータ線、42 
onrg 晶λ1AilijJ’Fiek 、 4 1
 2 〜4 1 4 1d’lW 刀体 トランジスタ
、421〜422 ifコンタクトホールである。42
3の斜線部分に電荷保持用キャパシタ示形成される。第
4図1b+は第4図1(L+の断面図であり同一記号の
ものは同じものを示す。第2図1b+において、411
は透明基板(ガラス基板等)、412〜414は第]の
シリコン薄膜層、415はゲート酸化膜、416,41
7は第2のシリコン薄膜層、418は層間絶縁膜、41
9はアルミニウム合金等による配線層、420はI T
 n等による透明雷、極をそノ1、それ示す。同図にも
・いて、412.414は”、%9′膜トランジスタの
ソース・ドレイン、416はゲートであり、419はデ
ータ線である。また、420及び417の間にηtりI
保持用キャパシタが形成さlしている。第3図141に
おいて液晶に印加される電圧波形303の実効値VEと
△V2との関係は次式で力えられる。
The present invention will be explained in detail below. 4th ICa, +,
An example of the present invention is shown in 1/11. FIG. 4 1al is a top view of one pixel of a matrix type liquid crystal display device in which a layer film transistor is formed on a transparent substrate. In the same figure, 416 is Gateyacho! , 41.9 phantom, data line,
417 is a common electrode or a data line of an adjacent pixel, 42
onrg Akira λ1AilijJ'Fiek, 4 1
2 to 4 1 4 1d'lW blade transistor, 421 to 422 if contact hole. 42
A charge holding capacitor is formed in the shaded area 3. Figure 4 1b+ is a sectional view of Figure 4 1 (L+, and the same symbols indicate the same things. In Figure 2 1b+, 411
412 to 414 are silicon thin film layers; 415 is a gate oxide film; 416 and 41 are transparent substrates (glass substrates, etc.);
7 is a second silicon thin film layer, 418 is an interlayer insulating film, 41
9 is a wiring layer made of aluminum alloy, etc.; 420 is an I.T.
Transparent lightning due to n, etc., shows the pole part 1. Also in the same figure, 412 and 414 are the source and drain of the %9' film transistor, 416 is the gate, and 419 is the data line.
A holding capacitor is formed. In FIG. 3 141, the relationship between the effective value VE of the voltage waveform 303 applied to the liquid crystal and ΔV2 is expressed by the following equation.

VFJ=に@△V2    ・・・(3)ただし、0(
K(]。データ信号がゼロであるときに液晶が点灯しな
い条件は、液晶のしきい値電圧をVT)Iとすると、次
式で力えられる。
VFJ=@△V2...(3) However, 0(
K(]. The condition under which the liquid crystal does not turn on when the data signal is zero is given by the following equation, where the threshold voltage of the liquid crystal is VT)I.

V E (VTH* * −(41 式+21 、 +31 、141よシ、データ信号がゼ
ロのときに液晶が点灯しない条件は次のとうシである。
V E (VTH * * - (41 Equations +21, +31, 141) The conditions under which the liquid crystal does not light up when the data signal is zero are as follows.

ただし、Cs2. CLC,CI(2はそれぞれ第2図
1/+1における寄生容量215.液晶116.電荷保
持用キヤパソタ212の容量値である。第5図はツイス
テドネマチソク型液晶の電圧−コントラスト曲線の一例
であシ、横11i1+が液晶に印加される電圧の実効伜
、縦1QI+がコントラストである。こントラストは、
Jのとき黒、0のとき白を示す。同図でコントラストが
0.1となる501が液晶のしきい値電圧である。とこ
ろで、MCl5)ランジスタのゲート・ソース間W )
、1.、 CG S+ゲート・ドレイン間容噌:COD
は、ゲート・ソース間電圧VG、g 、ゲート・ドレイ
ン間電圧VODの関数として次式で力えられることが知
られている。(RL A R1! ?J Z l! 7
71 eVOL r 321ケCA1971参照〕 ただし、CowはMob )ランジスタの/−ト電極下
の酸化膜の船客1ff4、”TけMOS)ランジスタの
しきい値電圧である。薄膜トランジスタについても1(
il 、 +71と大体同様な関係式が成シ立つものと
考えられる。第2図f/+lておいて、薄膜トランジス
タ211全通して液晶駆動電極へのデータの書き込みが
終了1〜た時点では、ソース・ドレイン間電圧はゼロと
なり VGs== VGD       * * d81の関
係が成立している。従って、弐F61 、 +71 、
 +81より、このときゲート・ソース間寄生容量及び
ゲーox ト・ドレイン間寄生容量は共にTとなる。従ってデータ
信号がゼロのときに液晶が点灯しないための条件式+5
1は次のように書き換えられる。
However, Cs2. CLC and CI (2 are the capacitance values of the parasitic capacitance 215, liquid crystal 116, and charge holding capacitor 212 in FIG. 2 1/+1, respectively. FIG. The horizontal 11i1+ is the effective voltage applied to the liquid crystal, and the vertical 1QI+ is the contrast.The contrast is
J indicates black, and 0 indicates white. In the figure, 501, at which the contrast is 0.1, is the threshold voltage of the liquid crystal. By the way, MCl5) between the gate and source of transistor W)
, 1. , CG S+Gate-drain capacity: COD
is known to be expressed by the following equation as a function of the gate-source voltage VG,g and the gate-drain voltage VOD. (RL A R1! ?J Z l! 7
71 eVOL r 321ke CA1971] However, Cow is the threshold voltage of the oxide film under the / - gate electrode of the MOB) transistor.
It is considered that a relational expression roughly similar to il, +71 holds true. At f/+l in FIG. 2, at the point in time when data has been written to the liquid crystal drive electrode through the entire thin film transistor 211, the source-drain voltage becomes zero and the relationship VGs==VGD * * d81 is established. are doing. Therefore, 2F61, +71,
+81, in this case both the gate-source parasitic capacitance and the gate-drain parasitic capacitance are T. Therefore, the conditional expression for the LCD not to light up when the data signal is zero +5
1 can be rewritten as follows.

ただj、、Coxは薄膜トランジスタのゲート酸化膜容
量であり、ゲート長′f:L、ゲート幅f:W、酸化膜
厚をTQC、酸化膜の比誘電率をε、真空の銹電率をC
0とすれば次式で与えられる。
However, j, Cox is the gate oxide film capacitance of the thin film transistor, gate length 'f: L, gate width f: W, oxide film thickness is TQC, dielectric constant of the oxide film is ε, and vacuum electric constant is C
If it is set to 0, it is given by the following formula.

薄膜トランジスタによるアクティブマトリクス型液晶表
示装置を製造する際、用いる液晶のしきい値電圧VTH
、ゲート線駆動信号の振幅VGが与えられたとき、式(
91の条件を満たすようにCox 、 CLO、CH2
を設定することにより表示性能が優れたアクティブマl
−IJクス型液晶表示装置が得られる。
Threshold voltage VTH of the liquid crystal used when manufacturing an active matrix type liquid crystal display device using thin film transistors
, when the amplitude VG of the gate line drive signal is given, the formula (
Cox, CLO, CH2 to satisfy the conditions of 91
An active marker with excellent display performance can be created by setting
- An IJ box type liquid crystal display device is obtained.

また、このようにして製造されたアクティブマトリクス
型液晶表示装愼においては、動作中液晶を劣下させるよ
うな直流電圧が液晶に加えられることはない。具体例を
挙げてみよう。いま、ゲート線駆動信号の振幅VGが2
0V、液晶のしきい値電圧VTRが2v、液晶固有の時
定数から決まる値Kが0.7.液晶容量eLoが帆2P
F、電荷保持用容+#CH。
Further, in the active matrix type liquid crystal display device manufactured in this manner, a direct current voltage that would degrade the liquid crystal is not applied to the liquid crystal during operation. Let's take a concrete example. Now, the amplitude VG of the gate line drive signal is 2.
0V, the threshold voltage VTR of the liquid crystal is 2V, and the value K determined from the time constant unique to the liquid crystal is 0.7. LCD capacity eLo sails 2P
F, charge retention capacity +#CH.

が002PF”であるものとすれば、薄膜トランジスタ
のゲート酸化膜容重、Cox 1l−1、Cox (0
,0667PF’でなくてはならない。ゲート酸化膜の
比誘電率εを3.9 、 :N空のg’a率ε0を8.
86 X lil ’ F/cy++ 、ゲート酸化膜
厚tax f 2000A 、スイッチング用薄膜トラ
ンジスタのゲート長をTJ11t7L Hゲート幅をw
ttmとする。このとき、Coz=LXWX6.92X
IIl  (O00667よりL X W < 386
μm2となるように薄膜トランジスタの寸法り、Wを定
めれば、薄膜トランジスタの寄生容量によって、データ
信号ゼロのときに液晶が点灯するという弊害が生ずるこ
とはない。
is 002PF'', then the gate oxide film weight of the thin film transistor, Cox 1l-1, Cox (0
,0667PF'. The dielectric constant ε of the gate oxide film is 3.9, and the g'a ratio ε0 of the :N vacancy is 8.
86
ttm. At this time, Coz=LXWX6.92X
IIl (from O00667 L X W < 386
If the dimensions of the thin film transistor and W are determined to be μm2, the parasitic capacitance of the thin film transistor will not cause the problem that the liquid crystal turns on when the data signal is zero.

また、液晶が劣化するような直流電圧が液晶に印加され
ることはない。
Furthermore, a direct current voltage that would degrade the liquid crystal is not applied to the liquid crystal.

以上述べたごとぐ、条件式19)を満足するようにアク
ティブマトリクス型液晶表示装置を役割することにより
、表示品質が優れ、信頼性の高いアクティブマトリクス
型液晶表示装置が得られる。
As described above, by making the active matrix liquid crystal display device satisfy conditional expression 19), an active matrix liquid crystal display device with excellent display quality and high reliability can be obtained.

【図面の簡単な説明】 第1図IQ、+ 、 fb+ 、 lC1はアクティブ
マトリクス型液晶表示装置の概要を説明するだめの図。 第2図(czlは、浄結晶ンリコン基板」二に設けたア
クティブマトリクス型液晶表示装置の−・・画素を示し
た図。 第2図1b1は、透明基板上に設けたアクティブマトリ
クス型液晶表示装置の一画素を示した図。 第3図(αl 、 fb+は、従来のアクティブマトリ
クス型液晶表示装置の欠点を説明するだめの図。 第4図(αl 、 fb+は、本発明を適用したアクテ
ィブマトリクス型液晶表示装置の一音ISを7iモした
図1゜第5図は、液晶の電圧−コントラストの関係を示
した図。 以   上 出願人 株式金利h11!訪精工舎 」 (トン 第21! jθ/ θ13′(幻 (久) 4+1)(b7 第4図 コ〉トラスト −2(
[Brief Description of the Drawings] FIG. 1 IQ, +, fb+, lC1 is a diagram for explaining the outline of an active matrix liquid crystal display device. Figure 2 (czl is a diagram showing the pixels of an active matrix liquid crystal display device provided on a transparent substrate). Figure 2 1b1 is a diagram showing the active matrix liquid crystal display device provided on a transparent substrate. Figure 3 (αl, fb+ is a diagram for explaining the shortcomings of the conventional active matrix liquid crystal display device. Figure 1 is a 7i model of the one-note IS of a type liquid crystal display device. Figure 5 is a diagram showing the relationship between voltage and contrast of a liquid crystal. / θ13' (Illusion (Kyu) 4+1) (b7 Figure 4) Trust -2 (

Claims (1)

【特許請求の範囲】[Claims] 複数本のゲート線及び該ゲート線と直交する複数本のデ
ータ線を備え、その各交点に薄膜トランジスタを形成す
ると共に、前記各々の薄膜トランジスタに透明な沿晶駆
動電極を接続して成る第一の基板と、該第−の基板に対
向する第二の基板と、の間に液晶を介設して成るアクテ
ィブマトリクス型液晶表示装置において、前記液晶駆動
電極に振幅零のデータ信号を読み込んだ時に液晶に印加
される電圧の実効値が該液晶のしきい値電圧未満となる
ように、薄膜トランジスタの寄生容量、電荷保持用容敏
及び液晶容量の容量値に制限を設けたととを特徴とする
アクティブマトリクス型液晶表示装置。
A first substrate comprising a plurality of gate lines and a plurality of data lines orthogonal to the gate lines, a thin film transistor being formed at each intersection of the gate lines, and a transparent crystalline driving electrode connected to each of the thin film transistors. and a second substrate facing the second substrate, and in an active matrix liquid crystal display device, when a data signal of zero amplitude is read into the liquid crystal drive electrode, the liquid crystal is An active matrix type, characterized in that the parasitic capacitance of the thin film transistor, the capacity for charge retention, and the capacitance value of the liquid crystal capacitor are limited so that the effective value of the applied voltage is less than the threshold voltage of the liquid crystal. LCD display device.
JP11496982A 1982-07-02 1982-07-02 Active matrix liquid crystal display device Expired - Lifetime JPH06100745B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11496982A JPH06100745B2 (en) 1982-07-02 1982-07-02 Active matrix liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11496982A JPH06100745B2 (en) 1982-07-02 1982-07-02 Active matrix liquid crystal display device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP7247637A Division JP2554998B2 (en) 1995-09-26 1995-09-26 Driving method of active matrix type liquid crystal display device

Publications (2)

Publication Number Publication Date
JPS597344A true JPS597344A (en) 1984-01-14
JPH06100745B2 JPH06100745B2 (en) 1994-12-12

Family

ID=14651107

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH06100745B2 (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119329A (en) * 1982-12-27 1984-07-10 Toshiba Corp Liquid crystal display device
JPS60163091A (en) * 1984-02-03 1985-08-24 セイコーエプソン株式会社 Liquid crystal display body
JPS60207116A (en) * 1984-03-31 1985-10-18 Toshiba Corp Display electrode array
JPS61171083U (en) * 1985-04-09 1986-10-23
JPS6211829A (en) * 1985-03-28 1987-01-20 Toshiba Corp Active matrix type liquid crystal display device
JPS63216030A (en) * 1987-03-05 1988-09-08 Asahi Glass Co Ltd Active matrix liquid crystal display device
EP0379249A2 (en) * 1989-01-18 1990-07-25 Philips Electronics Uk Limited Active matrix-addressed display devices
WO1990008340A1 (en) * 1989-01-10 1990-07-26 David Sarnoff Research Center, Inc. High-density liquid-crystal active dot-matrix display structure
EP0399846A2 (en) * 1989-05-26 1990-11-28 Sharp Kabushiki Kaisha An active-matrix display device and a method for the production of the same
JPH02291520A (en) * 1989-05-02 1990-12-03 Toshiba Corp Liquid crystal display device
US5305128A (en) * 1989-12-22 1994-04-19 North American Philips Corporation Active matrix electro-optic display device with storage capacitors and projection color apparatus employing same
US6235546B1 (en) 1989-12-22 2001-05-22 North American Philips Corporation Method of forming an active matrix electro-optic display device with storage capacitors

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SID82DIGEST=1982 *

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0463378B2 (en) * 1982-12-27 1992-10-09 Tokyo Shibaura Electric Co
JPS59119329A (en) * 1982-12-27 1984-07-10 Toshiba Corp Liquid crystal display device
JPS60163091A (en) * 1984-02-03 1985-08-24 セイコーエプソン株式会社 Liquid crystal display body
JPS60207116A (en) * 1984-03-31 1985-10-18 Toshiba Corp Display electrode array
JPH0568688B2 (en) * 1984-03-31 1993-09-29 Tokyo Shibaura Electric Co
JPS6211829A (en) * 1985-03-28 1987-01-20 Toshiba Corp Active matrix type liquid crystal display device
US4789223A (en) * 1985-03-28 1988-12-06 Kabushiki Kaisha Toshiba Matrix-addressed liquid crystal display device with compensation for potential shift of pixel electrodes
JPH0476458B2 (en) * 1985-03-28 1992-12-03 Tokyo Shibaura Electric Co
JPS61171083U (en) * 1985-04-09 1986-10-23
JPS63216030A (en) * 1987-03-05 1988-09-08 Asahi Glass Co Ltd Active matrix liquid crystal display device
JPH0827464B2 (en) * 1987-03-05 1996-03-21 旭硝子株式会社 Active matrix LCD display
US4968119A (en) * 1989-01-10 1990-11-06 David Sarnoff Research Center, Inc. High-density liquid-crystal active dot-matrix display structure
WO1990008340A1 (en) * 1989-01-10 1990-07-26 David Sarnoff Research Center, Inc. High-density liquid-crystal active dot-matrix display structure
US5132677A (en) * 1989-01-18 1992-07-21 U.S. Philips Corporation Active matrix-addressed display devices
EP0379249A2 (en) * 1989-01-18 1990-07-25 Philips Electronics Uk Limited Active matrix-addressed display devices
JPH02291520A (en) * 1989-05-02 1990-12-03 Toshiba Corp Liquid crystal display device
EP0399846A2 (en) * 1989-05-26 1990-11-28 Sharp Kabushiki Kaisha An active-matrix display device and a method for the production of the same
US5162901A (en) * 1989-05-26 1992-11-10 Sharp Kabushiki Kaisha Active-matrix display device with added capacitance electrode wire and secondary wire connected thereto
US5305128A (en) * 1989-12-22 1994-04-19 North American Philips Corporation Active matrix electro-optic display device with storage capacitors and projection color apparatus employing same
US5929463A (en) * 1989-12-22 1999-07-27 North American Philips Corporation Active matrix electro-optic display device with storage capacitors and projection color apparatus employing same
US6235546B1 (en) 1989-12-22 2001-05-22 North American Philips Corporation Method of forming an active matrix electro-optic display device with storage capacitors

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