JPS5972170A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the element breakdown due to current concentration generating on a partial region of an anode base layer of the titled semiconductor device when a turn-ON position is given thereon by a method wherein, when an anode base layer is going to be provided, said anode base layer is formed in such a manner that the ON- voltage drop at a part of the region aligned on a signal application region is increased. CONSTITUTION:A thyristor has the first - fourth semiconductor layer 3-5 and 9 within its substrate. A main electrode 6 is provided on the main surface of the layer 3, a recessed part 3a is formed on the other surface of said layer 3 at the position aligned to a signal region, and a ringlike protruded part 3b is formed on the circumference of the recessed part 3a. Also, on one surface of a layer 4, a protruded part 4a is formed against the recessed part 3a, and a ringlike recessed part 4b is formed against the protruded part 3b. As a result, the values of ON voltage drop of the above two parts 4a and 4b when a turn-ON operation is performed or the main current is applied vary with each other are varied with each other. Accordingly, when a dv/dt turn-ON and the turn- ON by forward overvoltage are generated, a conductive condition is generated in ring shape along the B point as shown in the diagram, thereby enabling to eliminate the possibility of generation of the element breakdown due to current concentration.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a semiconductor device called a thyristor, and more specifically, the present invention relates to a semiconductor device called a thyristor.
The present invention relates to a so-called self-starting or self-protecting thyristor which switches without destruction even when V/dt) is applied.

[Technical background of the invention]

As is well known, Cyrisk conducts when an excessive anode voltage is applied or when a steep reverse voltage rising above the critical OFF voltage rise rate is applied, but in this case, the process of transition from the OFF state to the ON state Since the conduction area spreads slowly, local concentration of anode current tends to occur, which tends to cause destruction of the device.

Therefore, in power converters using Thyrisk, an external protection circuit is inserted in parallel to prevent excessive forward voltage or steep rising reverse voltage exceeding the critical off-voltage rise rate from being applied to the thyristor. It's here.

Regarding some silicon risks, there are devices with a short emic structure that have a large dv/dt withstand capacity, and FI gates (FI gates) that can protect the device from destruction by rapidly expanding the conduction area of the device even during dv/dt turn-on.
Elements with a dIn1tiate Gate) structure, a reproducing gate structure, and an amplification gate structure are being used.

Furthermore, devices have been developed in which the FI gate structure and the amplification gate structure are improved so that the device itself has a protection function that conventionally relied on an external protection circuit. This improved element is called a self-protection type cyrisk or a self-ignition type thyrisk, and it also breaks down when a forward overvoltage is applied or a steep rising reverse voltage exceeding the critical off-voltage rise rate is applied. It has the characteristic of turning on without any

However, the self-protection type Cyrisk or improved Cyrisk that has been published so far has the following drawbacks and is not completely satisfactory.

[Problems with background technology]

Conventional patent publications and patent publications related to CyRisk equipped with self-protection functions or similar functions include the following, for example. (i) Special Public Interest Publication No. 45-13252
No. Publication, (ii) Special Publication No. 50-8315, (ii)
i) JP-A-50-147681, (iv) JP-A-56-43663, (V) JP-A-54-6088
1 Publication, (vi) Special Publication No. 56-41180, (
vii) Special Publication No. 56-4.3662, (vjii
) Of the thyristors disclosed in the publications listed above, (i)
(ii) (iii) (iV) The Sirisk disclosed in (V) is configured so that a part of the third PN junction on the cathode side is brought closer to the second PN junction, and (Vi ) has two auxiliary lights for ignition installed in parallel with the main lights,
(I) and (Viii) provide a portion with high impurity concentration in the cathode-base region, and (Viii) forms a recess in the can-do base region near the gate electrode to reduce the thickness of the cathode-base region in the recess. All of these thyristor risks were developed to prevent thyristor destruction by rapidly expanding the conduction area during Kuhn-on, and to obtain good turn-on characteristics. It also includes those developed for the purpose of providing functionality.

However, in these conventional devices, improvements were made only in the vicinity of the third PN junction, so they had drawbacks as described below and were unsatisfactory as practical devices. That is, in the thyristors disclosed in (i) to V) above, the turn-on characteristics are improved by bringing a part of the third PN junction near the gate or the auxiliary electrode closer to the second PN junction, Even if such a structure becomes an amplification gate structure, current concentration occurs at weak points, and destruction of the element cannot be avoided when a forward overvoltage or a steep rising reverse voltage is applied.

On the other hand, even when the weak point in the third PN junction is configured in a ring shape as shown in Figure 5 of the above-mentioned publication (VU), current concentration occurs in the first PN junction.
The disadvantage is that the reverse voltage deteriorates.

In addition, the above (ij) CLi1) (iv) (su(v
The thyristors disclosed in the publications i) and (viii) have the disadvantage that the forward blocking voltage and reverse voltage deteriorate because current concentration occurs at the center of the element aligned with the gate region at the first PN junction and the second PN junction. be.

Therefore, each of the above-mentioned known risks does not have a complete self-protection function, and does not have a forward overvoltage or dv/d
It had a built-in danger of being destroyed when turned on, and also had the drawback of lowering the maximum element operating voltage.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor device, ie, a thyristor, which eliminates the drawbacks of the known thyristors, has a complete self-protection function, and can be used at high voltages and large currents.

[Summary of the invention]

The characteristics of the improved silicon risk according to the present invention are such that the on-voltage drop in a portion of the anode base layer aligned with the gate signal application area is larger than the on-voltage drop in the remaining area of the anode base layer. The anode base layer is formed. By forming the anode base layer in such a way that the on-voltage drop in a part of the anode base layer aligned with the signal application region (that is, the initial turn-on region) is large, turn-on F\jK is It is possible to prevent element destruction due to current concentration in a region, and to eliminate the drawbacks of known cyrisks.

In order to make the on-voltage drop in a partial region of the anode base layer aligned with the gate signal application region larger than that in the remaining region, for example, the layer thickness in the partial region,
It is effective to control parameters such as carrier lifetime and impurity concentration. In an embodiment of the present invention, the thickness of the partial region of the anode base layer (the region aligned with the gate signal application region or the region aligned with the initial turn-on region) is set to be thicker than the remaining region. In the PN junction, a part of the anode base layer is formed to protrude into the anode emitter layer in the shape of a boss. In other words, in the embodiment of the present invention, the layer thickness of the remaining region (the portion aligned with the main current carrying region) is formed to be thinner at least at the 10th PN junction, and at least at the 1st PN junction.
A feature is that a step is provided at the N junction, and two regions with different on-voltage drops are formed in the anode base layer.

[Embodiments of the invention]

Examples of the present invention will be explained below with reference to the drawings]
do.

FIG. 1 is a longitudinal sectional view of an embodiment of the present invention. As shown in the figure, this thyristor has a base made of a silicon semiconductor material, and the base has a first main surface 1 and a second main surface 1.
A first semiconductor layer (P
□anode) 6, second semiconductor layer (N□ base) 4, third semiconductor layer (P2 base) 5, and fourth semiconductor layer (N□ base) 5
2 Emitsuta] 9. One surface of the first semiconductor layer 6 constitutes the first main surface 1, and the first main surface has a first
A main electrode 6 is provided. A concave portion 6a is formed on the other surface of the first semiconductor layer B at a position aligned with a gate signal region to be described later, and a ring-shaped convex portion 3 is formed around the concave portion 6a.
Therefore, in the first PN junction 7 between the first PN junction 7 and the second semiconductor layer 4, a concave part 6a and a convex part 6b are formed so as to form a step difference. One surface of the second semiconductor layer 4 is formed to have a complementary shape to the end surface of the first semiconductor layer, and in detail, the protrusion 4a and the ring are formed in the recess 6a. A ring-shaped depression 4b and a ring-shaped depression 4b are formed on one surface of the second semiconductor layer 4. On the other hand, the other surface of the second semiconductor layer 4 is configured as a flat surface in this embodiment, and is bonded to the third semiconductor layer 5 having the same flat surface to form a second PN junction 8.

Therefore, in the second semiconductor layer 4, the layer thickness at the boss-shaped projection 4 is larger than the layer thickness at the surrounding ring-shaped four parts 4b. The magnitudes of the on-voltage drops at 4b are different values.

A plurality of ring-shaped fourth semiconductor layers 9 are formed in the third semiconductor layer 5 at regular intervals. A third PN junction 10 is formed at the surface exposed on the main surface 2 and connected to the third semiconductor layer 5 . A ring-shaped main electrode 11 is provided on the second main surface 2 in common to the third exposed semiconductor layer surface and the fourth exposed semiconductor layer surface. (
The structure of the fourth semiconductor layer 9 and the arrangement of the main electrode 11 are generally known as a short emitter structure, which is a suitable structure that provides a high dv/dt withstand capability to a high frequency thyristor. An annular fifth semiconductor layer 12 is formed in the third semiconductor layer 5 at an inner position, and the fifth semiconductor layer 12 is also exposed on the second main surface 2 . The fifth semiconductor layer 12 has the same conductivity type as the fourth semiconductor layer 9, and therefore the junction surface between the third semiconductor layer 5 and the fifth semiconductor layer 12 constitutes a part of the third PN junction. ing. and the exposed surface of the third semiconductor layer and the fifth semiconductor layer 5
A ring-shaped auxiliary electrode 16 is provided on the exposed surface of a and is in common contact with the exposed surfaces of the auxiliary electrode 16 and the fifth semiconductor layer 12.
Further, the PNPN structure directly under the fifth semiconductor layer constitutes an auxiliary thyristor section or a pilot thyristor section with respect to the main thyristor section consisting of the fourth semiconductor layer 9 and the PNPN structure immediately below it.

Third semiconductor layer 5b existing inside the fifth semiconductor layer 12
serves as a gate signal application region, and an annular gate electrode 14 is in contact with the exposed surface of the third semiconductor layer 5b. The gate electrode 14 and the third semiconductor layer 5b immediately below it, the fifth semiconductor layer 12 and the auxiliary electrode 16 thereon form a so-called amplification gate structure, and the fifth semiconductor layer 12
The structure utilizes the voltage drop caused by the lateral resistance in the

The radius r□ of the inner circumferential edge of the fifth semiconductor layer 12 may be approximately equal to the radius r2 of the boss-shaped protrusion 4a of the second semiconductor layer 4 in the first PN junction 7, so that r2>rl.

In the cyrisk of the present invention having the structure as described above, dv/d
When t-turn-on and turn-on due to forward overvoltage occur, conduction occurs in a ring shape along point B in the figure, so there is no risk of element destruction due to current concentration. That is, conventional thyristors (for example, Japanese Patent Application Laid-Open No. 50-1476
Since the gate electrode is provided on the center line of the element, the position A of the first PN junction on the center line of the element at the time of turn-on is
There was a risk of element destruction due to current concentration occurring at
A boss-shaped protrusion 4a substantially aligned with the inner peripheral edge of the semiconductor layer 12 of
, the annular region along point B at the base of the boss-shaped protrusion 4a is partially turned on when turned on, and as a result, the thyristor is smaller than the thyristor disclosed in JP-A-50-147681. The initial turn region in the PN junction has become much wider, and even if dv/dt turn-on or turn-on due to forward overvoltage occurs, there is no risk of device destruction.

Further, in the embodiment of the present invention, the layer thickness of the initial turn-on region (the portion aligned with the boss-like protrusion 4a) in the second semiconductor layer 4 is the same as that of the region outside the region (this is the thickness of the fourth and fifth semiconductor layers). Since the layer thickness of the ring-shaped recesses 4b aligned with the arrangement regions 9 and 12 (corresponding to the main current carrying region) is also thicker, the on-voltage of the initial turn-on region in the second semiconductor layer 4 is increased. Since the drop is larger than the on-voltage drop in the main current carrying area, the initial current increase rate at turn-on can be suppressed from becoming excessive, and as a result, the risk of element destruction at turn-on is prevented. can do.

In order to make the on-voltage drop in the initial turn-on region larger than the on-voltage drop in the main current carrying region, it is necessary to Although this can be achieved by reducing the layer thickness of the turn-on region, it is still possible to achieve this by making the lifetime of the main current carrying region of the second semiconductor layer longer than the lifetime of the initial turn-on region.
Alternatively, this can be achieved by making the impurity concentration in the main current carrying region lower than the impurity concentration in the initial turn-on region. Moreover, these means may be combined.

In order to cause dv/ilt turn-on without causing device destruction, it is necessary to appropriately set the value of the lateral resistance in the fifth semiconductor layer 12 in terms of device design. This can be achieved by appropriately setting the impurity concentration and width W of the semiconductor layer.

FIG. 2 shows another embodiment of the present invention, in which the layer thickness of the initial turn-on region in the second semiconductor layer 4 and the layer thickness of most of the main current carrying region are equal. The difference from the embodiment shown in FIG. 1 is that it is designed so that However, in the first PN junction, the boss-like protrusion 4a is formed in the second semiconductor layer 4, and the recess 6a corresponding to the boss-like protrusion 4a is formed in the first semiconductor layer 6. This is the same as the embodiment shown in the figure. and the first
In order to produce the same effect as the embodiment shown in the figure, an annular groove 4C with an inclined surface into which the first semiconductor layer is inserted is formed around the boss-shaped protrusion 4a in the second semiconductor layer 4. The apex of the groove bottom of the annular groove 4C, that is, the root of the boss-like protrusion 4a □
The original point C is provided at a position substantially aligned with the inner peripheral edge of the fifth semiconductor layer 12 so as to perform the same function as the point B in FIG.

In the embodiment shown in FIG. 2, the same effects as in the embodiment shown in FIG. 1 can be obtained. In other words, at turn-on, the first
The turn-on of the junction 7 begins precisely in the annular region indicated by point C, and therefore there is no risk of current concentration occurring on the central axis of the element unlike in the conventional element.

〔Effect of the invention〕

As described above, according to the present invention, the disadvantage of the conventional SIRISK, that is, the fact that the first PN junction is prone to breakage at turn-on, is eliminated, and when a steep rising voltage or forward overvoltage is applied, A self-protecting silicon risk, that is, a semiconductor device that can be turned on without being destroyed is provided. In the above embodiments, the layer thickness in the initial turn-on region of the second semiconductor layer is increased. Instead of making the layer thickness of each part of the second semiconductor layer 4 different in this way, an element may be formed so that the carrier lifetime or impurity concentration in each part has different values. . Further, in the illustrated embodiment, an annular gate electrode is provided on the third semiconductor layer 5b in the gate signal application region exposed on the second main surface 2, and an electrical gate signal is applied. It may also be configured as a light-sensitive cyrisk.

[Brief explanation of drawings]

1 and 2 are cross-sectional views of a thyristor in an embodiment of the present invention. 1... First main surface, 2... Second main surface, 6...
- First semiconductor layer, 4... Second semiconductor layer, 5...
third semiconductor layer, 6... first main electrode, 7... first
8... Second PN junction, 9... Fourth semiconductor layer, 10... Third PN junction, 11... Second PN junction.
main electrode, 12... fifth semiconductor layer, 16... auxiliary electrode, 14... gate electrode. Patent applicant: Tokyo Shibaura Electric Co., Ltd. Agent: Eiji Morota, patent attorney

Claims (1)

[Claims] 1. A first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type forming a first PN junction with the first semiconductor layer, and the second semiconductor layer. and a third semiconductor layer of the first semiconductor type forming a second PN junction;
a fourth semiconductor layer of a second conductivity type forming a PN junction, the first semiconductor layer having a first main surface, and the fourth semiconductor layer having a second main surface. , a portion of the third semiconductor layer is exposed on the second main surface, a first electrode is formed on the first main surface, and a fourth electrode is formed on the second main surface.
In a semiconductor device, a second electrode is formed on the semiconductor layer of the second main surface, and a third electrode is formed on the third semiconductor layer of the second main surface. Regarding the approximately ring-shaped partial region of the second semiconductor layer,
In the remaining regions, at least one of (A) reducing the layer thickness by providing a step in at least the first PN junction, (B) increasing the lifetime, and (C) lowering the impurity concentration is applied. A semiconductor device characterized by comprising means. 2. Claim 1, wherein the boundary between the partial region and the remaining region in the second semiconductor layer substantially opposes the boundary between the third semiconductor layer and the fourth semiconductor layer on the second main surface. The semiconductor device described. 6. Claim 1 or 2, wherein the fourth semiconductor layer is comprised of two or more regions and the electrodes form an amplification gate structure.
1. Semiconductor device described in Section 1. 4 d in the fourth semiconductor layer close to the third electrode
A semiconductor device according to any one of claims 1 to 3, which ignites v/d. 5. A semiconductor device according to any one of claims 1 to 4, which is driven by an optical signal.