JPS5971167A - Rotation control system of recording disc - Google Patents

Abstract

PURPOSE:To attain normal clock signal extraction and to switch the control to quartz servo, by applying forcibly external disturbance to the clock extraction PLL if no frame synchronism detection is done during the frame synchronism servo operation. CONSTITUTION:A reproducing RF signal from a pickup 2 is shaped at a waveform shaping device 3 to be an EFM signal. This signal is inputted to a frame synchronism servo device 4 from which a frame synchronism signal is generated. This servo signal is impressed to a spindle driver 6 via a switching device 5 to bring the spindle motor to the SYNC servo. The output of the waveform shaping device 3 is inputted to a clock extracting device 7, and the extractor 7 is formed as the PLL circuit constitution locked to clock information of a prescribed frequency included in the reproducing information. The reproducing clock signal extracted at the PLL7 and the said waveform shaping output are inputted to a demodulator 8, where they are converted into a prescribed digital signal (NRZ). The demodulated signal is inputted to an RAM9 and read out with a prescribed readout clock pulse, is converted into analog information at a D/A converter 10 to be an audio output.

Description

[Detailed description of the invention]

The present invention relates to a recording disk rotation control system, and more particularly to a recording disk rotation servo system for controlling the rotation of a disk on which digital signals are recorded. In recent years, technology has been researched and put into practical use that converts the analog information of the audio signal into PCM (pulse code conversion vIJ>) and records it on a recording medium in the 1 or O digital signal format.In this case, it is possible to easily demodulate the digital signal. In order to do this, we adopted a so-called self-clocking modulation method, and in order to achieve higher density recording, we adopted a constant linear velocity (CL V ) method, in which the linear velocity of all recording tracks is constant, instead of a constant rotational angular velocity method. When playing back CLV discs, it is necessary to control the rotation of the disc so that it maintains a constant linear velocity, and for this purpose, reproduction clock information of a predetermined frequency is extracted from the reproduction signal. It is common to perform spindle servo based on this clock signal. An example of this modulation method is FFM' (E 1oht
t. Fourteen Modulation) system has a format as shown in FIG. That is, one frame consists of, for example, 588 bits, and the data signal is converted to 14 bits every 8 bits using the EFM method according to a predetermined conversion table (not shown), and 3 adjustment bits are added to convert the 17 bits into 1 bits. When it is 1, there is an inversion from a logic torubel or the opposite of A, and when it is 0, there is no inversion, that is, NR7T.
recorded in the form of At the beginning of each frame, the first bits 1 to 1 are 1, the second to 11th bits are 01, the 12th bits 1 to 1 are 1, the 13th to 22nd bits are 01, and the 23rd bit is 1.
: Sea urchin frame sync signal is recorded. Based on the frame sync signal of J:, a control signal is placed at a predetermined position of 588 bits. And throughout the whole thing, there are two things between 1 and 1, 1 in 1 step.
Ic: processing is performed so that zero or less O's are arranged. That is, the minimum inversion interval at the signal level is 3T (T is the length of a bit cell), and the maximum inversion interval is 11T. Further, in the portion outside the frame sync signal ';'31, the maximum inversion interval is set so as not to occur two or more times in succession. A signal equivalent to a differentiated high-frequency rectified signal of this modulation signal is input to a PLL (phased locked loop) to extract clock information and perform signal reproduction processing.
In a non-musical band portion of the disc, musical tone data may have a fixed pattern corresponding to a zero level. In this case, the EFM signal is inverted to, for example, 7T, 3T, 7Tffl,
This is a time-series signal that includes many repetitive waveforms in which 17T is one cycle bright. In addition to the spectrum of the clock information frequency (/1., 3218MHz), the PIL input signal in the non-musical band part has a frequency that is shifted from the bright line spectrum by an integral multiple of 1/17 of the clock frequency (254Kl-1z). Has high energy level spurs. Since the frequency of this spurious is close to that of the positive phase clock, it is difficult to distinguish between the two based on the frequency. Therefore, the PLI for clock extraction may mislock to this large spurious energy level.
If the input lip frequency of P L l- is significantly deviated from the correct frequency, no locking will be possible. Therefore, when starting up, especially during a non-musical band part, or when moving the pickup largely and sharply in the direction of the disk to search for address information, the number of rotations of the disk will be significantly higher than the predetermined speed. The problem is that it may be impossible to extract the correct clock due to differences in the timing, and it takes a long time to control the rotation speed of the T-disc to the correct rotation speed and extract the correct clock again. be. The present invention was devised in view of this situation, and its purpose is to quickly escape from the mislock state and accurately extract the reproduced clock even when it is impossible to extract the recovered clock due to the above-mentioned PIL mislock, etc. The objective is to provide a rotation control method that can control the rotation of the disk. The rotation control method according to the present invention is a rotation control method for a recording disk on which a digital signal including clock information of a predetermined frequency and a synchronization signal in which n (n is an integer) consecutive inversions of the maximum interval is recorded. , a PLL circuit that can lock within a predetermined frequency range that includes the frequency of the clock information, in a state where a period of 0 times the maximum inversion interval is detected from the reproduced signal and the detected signal is used to control the disk rotation. Supply the reproduced signal to extract the clock signal, demodulate the synchronization signal using the extracted clock signal, and forcefully sweep the oscillation frequency of the voltage controlled oscillator of the PLL circuit if the synchronization signal is not demodulated. It is characterized by Hereinafter, the present invention will be explained with reference to the drawings. FIG. 2 is a schematic block diagram of an embodiment of the present invention, mainly depicting a spindle control system for disk rotation control. Before explaining FIG. 2, the main operating functions of the spindle control system will be described. The first function is an acceleration function (ACCII function), which is an operation that increases the motor rotation speed by flowing a large constant current to the spindle motor, and the second function is a holding function (HLD function). , by passing a small constant current through the spindle 1 motor, it maintains a constant rotational speed against the frictional force of the rotating system. It detects the frame sync directly from the playback RF signal (without extracting the playback) and controls the almost accurate linear velocity and rotation speed. It is a function. The fourth function is the quartz servo function (QRTZ servo function), which is
A signal corresponding to the frequency of the reproduced clock signal extracted from the signal 8 and the base? ! ! The frequency error signal obtained by comparing the EFM signal with the reproduced clock signal 8 is used to convert the EFM signal from 1 to 11.
Then, the phase of the frame sync detected from this demodulated signal is compared with the phase of the reference frame sync (7, 35KI17.), and the disk rotation speed is controlled using the detected phase error signal to obtain an accurate line. The purpose is to obtain speed.3 These four functions are selected by each control signal of system control [ΔCC, Hl-D, SYNC, QRTZ from 1-RA1 (see Figure 2)]. When there is no need for the disk to rotate (during the drive and eject operations), none of these control signals are output, and the spindle motor drive current is set to zero. For reference, re'I:R from Pickup 2
The r signal is shaped by the waveform shaper 3 to become the E/M signal. This signal is input to the frame sync servo device 4 and a frame sync servo signal is generated. This servo signal passes through the switch 5 to the spindle driver. 6 and makes the spindle motor a 5YNC servo. △In the case of CC operation, a constant voltage is applied via low resistance Ro+.
Since (2) is applied to the spindle driver 6, a large constant current (or constant voltage) is supplied to the spindle morph and ΔCC
It becomes an action. Furthermore, in the case of HLDf7+ operation, the value of resistor R02 is selected to be larger than resistance Ro+ so that a small constant current (or constant voltage) is supplied to the spindle motor, and HLD operation is possible. The output of the waveform shaper 3 is input to a clock extractor 7, and this extractor 7 has a P L l (phase locked loop) circuit configuration that locks to reproduction information (included clock information of a predetermined frequency). This P 1.,, L
The re-11T7/[]tsuku signal extracted in step 7 and the previous waveform shaping output are both input to demodulator 8 and converted into a predetermined digital signal (N R',7 ). The demodulated output is input to a RAM (random access memory) 9 and read out by a constant read clock pulse.
The A converter 10 converts the signal into analog information and outputs audio. Reference numeral 11 denotes an error corrector, which detects and corrects pips 1 to 1i and burst errors.
2. The demodulator 8 also has a sync detection function for detecting frame sync from the FFM signal using the reproduced clock, and the RAM:]n i to []-ra 12 is controlled. On the other hand, the frequency-divided output from the frequency divider 13 of this reproduced frame sync serves as a power source for the phase comparator 14, which includes the frequency-divided output of the reference frame signal generated from the reference signal generator 14. The frequency-divided output of the circuit 15 is supplied. The phase comparison output is level-shifted by a level shifter 16 and output to an adder 17 as a phase error signal. The loop filter connected to the previous PI 17 (7 in Figure 5)
The output of the level shifter 18, which compares the output of (see 3) with a predetermined reference voltage and adjusts the level of the comparison output, serves as a frequency error signal for the adder 17.
The output of this adder 17 becomes an A-2 servo signal and is applied to the spindle driver 6. Further, the frame sync detection output of the demodulator 8 is supplied to the system controller 1. This detection output controls the state of the switch 5 and switches the spindle motor operation, which will be described in detail later. Furthermore, from the system controller 1, the VCO of PLI 7 (see 74 in Figure 5)
A control signal for sweeping or forcing the oscillation frequency of IJ or a forced sweep control I signal is supplied, and the operation in this case will also be described later. Note that 19 indicates a keyboard, which means an operation panel or a player control board of the playback device. 20 and 2
Reference numeral 1 indicates a tracking servo system and a focus servo system, the operations of which are also controlled by a system controller 1. FIG. 3 is a block diagram showing a specific example of the frame synchronizer vibrator 4, and the reproduced EFM signal as shown in FIG. is input to. MMV4
1 is the input signal 1. Triggered by reversal in one direction, MM
V/+2 is triggered in the negative direction (C), and outputs a logic signal of To for a certain period of time.The outputs of both MMVs are connected to the retriggerable MMV4
4 trigger input, and the output of this MMV/I/l is I
- converted to DC level at P F /I 5; This DC level is determined by the comparator 46 as a reference level/1.
7 and the comparison output becomes a sync servo signal, which is input to the switch 5 shown in FIG. Incidentally, a relet signal g is supplied to the MMV 171 and the I-P F 45 from the outside, and when the sync servo is off, the timing of this reset signal causes the MMV 4.
The capacitor of the time constant circuit between /I and I-P F 45 is discharged and returns to the initial state.J: 1
Therefore, the settling time when the sync servo is next turned on is shortened. Here, the output pulse width T of MMV41,42. is the period of the frame synchronization signal (maximum inversion interval 2fR)
22T (20-30 ns shorter than 22T in y&density). Also, the output pulse width T1 of the MMV44 is the cycle of the frame dome signal (for example, 1/7.
35KH2"; 136 μs) (for example, 1/2 of the frame synchronization signal frequency). Whether the frame sync of the EFM signal starts from the rising edge or from the falling edge is determined by the first As shown in the figure, it is not fixed, and this is due to the properties of EFM (r?F3).
MMV41 to be triggered. /12 is provided. Now, the only time the interval from one rising edge of the input signal to the next rising edge or from one falling edge to the next falling edge is 22T is in the case of frame sync, so if the disk rotates at the correct linear speed. If so, this 22T interval would be approximately 5.09μs, so
Sui ~ Output pulse width T of regrable MMV4.1.42
o is approximately 20 to 30 nS (next stage M
The width of the pulse that can trigger MV/14) is set short. FIG. 4 shows the operation timing plate of the circuit of FIG. 3, and (A) shows that when the linear velocity exceeds the specified value,
(B) shows when it is approximately at the specified value, and (C) shows when it is smaller than the specified value. In other words, when the linear velocity is large as in (△), 5.09 μs does not elapse from the input rising edge (the same applies to falling edges, and the same applies hereinafter).13- Since the next rising edge will always arrive before , M.M.V.
/1.1 continues to be triggered and its output remains low level. In the almost proper case as shown in (B), the rising edge interval of only the frame sync part is 5.09 μs, so a thin pulse of about 20 to 3 Qns is output in synchronization with the frame sync. Become. Next, when the linear velocity is small as in (C), 1q pulses are added to the output of the MMV 41 in the frame sync portion and other portions as well. In this way, since the number of output pulses of the OR gate 43 changes depending on the linear velocity, the MM
Trigger V44 to generate a pulse train of a predetermined width and
If you convert DC using P F 4.5, you will end up with LPF 45.
An F/V conversion signal of the reproduced signal is obtained at the output. In other words, if the linear velocity of the disk is correct, MMV44 is triggered only in the frame sync part, so 1-
/V conversion signal shows a predetermined value, but if it is higher than MM
Since V44 is not triggered, the F/14- ■ conversion signal becomes snow, and if it is slower, MMV44 is triggered at the frame sync part and the outside part of the frame sync, so the F/V conversion signal is fixed. greater than the value. Level 47 corresponding to this F/V variable power output normal m speed
A servo signal can be obtained by comparing the levels with (-). By the way, how the output voltage of the LPF (/I5 in FIG. 3), which is a /V conversion signal, changes as the linear velocity of the disk changes will be explained based on FIG. 5. If the disk is rotating faster than the correct l11M a If yi, the MMV44 1~Riga pulse will not occur as shown in FIG. 4 (Δ), so the output voltage will also be 1''≧. Also, if it is rotating very slightly slower than the correct linear speed of 7J22, each frame sink can have an MMV44
A trigger pulse is generated, and the output voltage J4 has a value corresponding to the frame sync frequency factor of 7.35Kt17. The linear velocity is Ul! 2J: When it comes to Richida lυdanR,
Since the frame sync frequency itself decreases from 7.35 Kl-1z, the output voltage also decreases accordingly. However, the linear velocity is about 4
．． When U21 becomes 5% slower, 21T becomes a time width equivalent to 227 (5.09 μs), so in addition to the frame sync where the transition interval is 22T, the MMV44 trigger pulse is also used at the 21T transition interval included in the signal. occurs,
Therefore, the output voltage increases suddenly. A similar change occurs as the linear velocity gradually decreases. Also,
If the linear velocity becomes very slow, the next trigger pulse will arrive between the time the MMV 44 is triggered and the end of the output pulse, so the MMV 44 will continue to be triggered and the output voltage will thus saturate to its maximum value. In this way, the characteristics shown in Figure 5 can be expressed as "The difference signal between the output voltage and level 47 is used as a servo signal, but level 47 is equivalent to the correct frame sync frequency of 7.35 KHz. When set to a value (predetermined value a in Fig. 5), the output voltage of the IPF is not only 1J22 but also v2+ and U2.
Since the linear velocity is equal to the predetermined value a even at a linear velocity of 0, there are many stable points, and correct servo cannot be performed. However, the level 47 in Figure 5 is J: Sea urchin, 7.3
If you set it to 5 sufficiently lower (for example, about half) than the value equivalent to +-17, you will reach a stable point.

[There is only one location where the linear velocity is correct, 11ρ, and therefore almost accurate linear velocity servo can be performed. That is, the circuit system shown in FIG. 3 detects a period that is 0 times the maximum inversion interval (n-2 in the embodiment) of the re/1 signal by comparing it with a reference period, and detects all signals corresponding to this detection signal. Generate the rope'5 F/V conversion signal,
Frame sync servo No. 15 was obtained by comparing this signal with Haku Motobo's signal. By driving the spindle motor using this servo signal, it is possible to drive the recording disk at a substantially accurate linear speed. This frame sync servo is extremely useful when clock information cannot be extracted from the raw signal, such as during startup or search (address information search) operations. The details of the function will be explained below. Record de 17 rotating with wow and flutter to the right
− The digital information played from the disk is first transferred to the RA.
After being written to M9 (see FIG. 2), it is read out using a constant clock signal and subjected to D/A conversion, resulting in a high quality audio signal without wow and flutter. In this case, since the capacity of RAM is limited, if the read speed and write speed are not exactly equal on average, the RAM
The storage information within will be empty or vice versa. In this case, the reproduced sound becomes choppy. When a musical tone signal is to be reproduced using a lever, a quartz servo is operated to maintain a constant disk linear velocity so that the reading speed always matches the reading speed. That is,
The phase comparator 14 compares the phase of the frequency-divided output of the reproduced frame sync obtained from the demodulator 8 in FIG. (The signals may be directly compared), and a signal corresponding to this phase difference is applied to the spindle motor as a servo signal. 18- However, since it is not possible to obtain appropriate damping characteristics for a servo with this phase error alone, it is necessary to further introduce a frequency error and mix it with the phase error. Therefore, clock extraction PI-1-7 1-1) F
Since the output voltage corresponds to the frequency of the reproduced clock signal, this voltage is compared with the reference voltage and the comparison output is used as frequency error information and added to the phase error information in the adder 17 to obtain the quartz servo signal 8. -ing Apply this quartz servo for the first time RΔM9
It is possible to perform accurate linear velocity servo in which the readout and retrieval speeds are equal to T degrees on average. Therefore, upon startup, in order to bring the rotational speed of the spindle motor to a certain level, an acceleration (8CG) operation is performed followed by a holding (TIL, D).
The frame sync (SYNC) servo operation is performed, and after that, the frame sync (SYNC) servo operation can be controlled at a speed close to the specified Pal speed to some extent even if no clock signal is extracted. After that, after confirming that the playback frame sync has been detected, the servo operation is switched to quartz servo (t) RT7), and an operation is performed such that a constant prescribed linear velocity is always maintained. FIG. 6 is a block diagram of the PLL 7 for extracting self-clock information from the reproduced EFM signal.
) is input to the edge detector 71, and a pulse (B) synchronized with the level transition timing of the reproduced signal (Δ) is generated. This edge pulse ([3) is set to have a pulse width approximately equal to the 2L period of the regular clock signal. This edge pulse serves as a single input to the phase comparator 72, and its phase is compared with the output (C) of the VCO 74. This phase difference output is converted into DC by L P [73 and becomes VC○7
4 control signals. The output of this VCO 7'4 is pulsed by a waveform shaper 75 and output as a reproduced clock signal. In order to quickly lock the PLL, sweep control is performed using the LPI (output of 73), and the sweep controller 76 controls the oscillation frequency of the VCO 74 to sweep between a predetermined upper and lower limit. In addition, in order to release the PLL error []tsuku, the forced sweep control signal is set to sweep control fill in order to apply a disturbance to the PLL 7 and force it to perform a forced sweep even further than the previous sweep operation. These sweep controls and forced sweep controls are performed by commands from the system controller 1 shown in Fig. 2. Fig. 7 shows the operating waveform of P L L 7 in Fig. 6.
(A) to (C) are the signals 8 (Δ) to (C) of the block in Fig. 6.
) are shown correspondingly. As you can see from the figure, VC
The output of O74 has 4.3218M at normal linear velocity.
A sine wave of Hz (emission line spectrum component) is obtained, and clock extraction becomes possible. FIG. 8 is a circuit diagram of the frame sync detector included in the demodulator 8 of FIG.
1 input, and one pulse is generated in response to the level transition timing of the reproduced signal. These edge pulses are sequentially enriched into a 23-bit shift register 82 operated by the re/I-clock signal 6. A total of 10 bits output from the second bit to the eleventh bit of the shift register 82 is input to the NAND gate 21-83, and the first bit of the shift register 82 is input to the NAND gate 21-83.
A total of 10 bits output from 3 bits 1 to 22 are input to a Nant gate 81'I. The outputs of both NAND gates 1- and the outputs of the 1st, 12th, and 23rd bits of the shift register 82 are input to a five-man gate 85, and the output of this gate serves as a reset signal for the counter 86. There is. The counter receives the reproduced clock as an input, and the output of this counter is derived as a frame sync detection signal and supplied to the system controller 1. When a frame sync signal is included in the reproduced Er:M signal and the frame sync signal has been input, the contents of the shift register 82 are as shown in the figure. Therefore, the output of the AND gate 85 at this point shows a logic H (1) level, and in all other cases it shows a logic (0) level.
) indicates the level. Therefore, if the counter 86 is a 588-bit counter corresponding to one frame of the reproduced signal, the counter 82 will be
Since 2-6 is always reset to zero, the frame sync detection signal is logic L when playback frame sinter is detected.
It becomes level and 59 is issued. On the other hand, when the power counter 86 counts 588 reproduced clocks, if frame 11 sync does not arrive, the counter 86 will not be reset and the logic 1-
1 signal, so by monitoring the output of this counter, it is possible to identify whether or not the correct reproduced clock is being extracted without detecting the reproduced frame sync. Switching from frame sync revo to quartz servo is performed only when this replay frame sync is detected, and if re-171 norm sync is not detected during frame sync servo, re-A-T ()
--Since it is impossible to move to
7 is forcibly swept, and the forcible retraction to []tsuku information is controlled. FIG. 9 is a diagram showing a specific example of the sweep controller 76 shown in FIG. 6. In both figures, equivalent parts are designated by the same reference numerals 8 and their explanations will be omitted. DC voltages Vg and vh having different levels are applied to the anti-phase input of the amplifier OP1 constituting the loop filter 73 via the switches 701 and 702, respectively, and further via the resistors R3 and R4. Note that the filter 73 has a resistor R+ connected to the amplifier OP+ and the capacitor C1. It has an active filter configuration using R2. To control the switches 701 and 702, an R-S flip-flop 70 consisting of three gates Gl' and G7 is used.
3, the switch 701 is turned on and off by the output (C) of the gate G1, and the switch 702 is turned on and off by the output (D) of the gate G2. Furthermore, the output of the loop filter 73 (T1), that is, the VCO
Level comparators 704, 705 are provided to determine the upper and lower limits of the control input voltage level of 74. A voltage Vm that determines the upper limit level is applied to the negative phase input of one comparator 704, and a voltage Vn that determines the lower limit level is applied to the positive phase input of the comparator 705. Both comparators 704.
The positive phase and negative phase inputs of 705 are connected to the output of LP ``73 (1-
1) is supplied. The outputs (T) and (J) of both comparators 704 and 705 are respectively
3 gates G2 and G1 are operated by one person and are used as set and reset inputs. A sweep controller 8 (A) is applied to the remaining inputs of G1 to G1 and G2 to perform sweep control. A switch 706 is installed at both ends of the resistor R4, and is turned on by the forced sweep control signal (B) to short-circuit the resistor R4. FIG. 10 is a diagram showing the operation of the circuit in FIG. 9, and (A)
.about.Ll) indicate waveforms of signals (Δ) to LJ) of the circuit shown in FIG. 9 in roughly corresponding manner. Furthermore, (E) and (“)
is a chart showing the on/off timing of the switches 701 and 702, and (G) is a chart showing the on/off timing of the switches 701 and 702.
This is a waveform showing the charging/discharging current. Sweep control signal (△
) is at the [ ] level, the flip-flop 703 is clamped to the reset state and no sweep operation occurs. If the signal <A) is 1. , when it comes to the level,
The flip 70 knob 703 is released from the reset state 25- and becomes capable of sweeping. Assume that the forced sweep control signal (B) is at H level and the switch 706 is turned off. At this time, when switch 701 is turned on, a charging/discharging current shown by (G) flows to capacitor C1, and LP
The output of F73 gradually decreases as shown in (H). When this output level reaches the lower limit level Vn (4V), the comparator 705 generates an output as shown in (J) to set the flip-flop 703. Therefore, the output of the flip-flop 703 is inverted as shown in (C) and (D), and the switch 701 is turned off and the switch 702 is turned on, so that the negative voltage v
h is applied to the capacitor C1, and the capacitor C1 is discharged as shown in (G). By this, LPF
The output of 73 gradually increases from the lower limit level Vn to the upper limit level Vm (6V) as shown in (H). When the upper limit level Vl11 is reached, the comparator 704 operates and resets the flip-flop 703, so the on/off states of the switches 701 and 702 are reversed, and the LPF output (1'') 26- changes again from the upper limit to the lower limit. do. In this way, the oscillation output frequency of the VCO 74 can be increased or decreased over a certain range. This is a so-called sweep operation. For example, 4.3218M1l±200K H
The sweep is carried out within a range of approximately 10m5. This sweep is relatively slow and P L I
Since it is only a small disturbance for -, if PLL is locked to the one-ro reproduction clock frequency, the one-rotation clock will not deviate again. The fourth sweep is T again! : 200 Kl-1z, which is inside the spurious interval (25/IK+-17), so as long as the disk is rotating at the correct linear velocity, PIL will not mislock to the spurious. When this P L l- is spuriously mislocked during a search and the mislock is to be released, the forced sweep control signal (B) becomes the - level and the switch 706 is turned on. Therefore, the resistor R4 is short-circuited, so that the charging and discharging current to the capacitor C1 increases, and the sweep speed becomes faster (for example, about 100 times the normal sweep). The timing diagram of each part in this case is shown as a forced sweep at the right end of FIG. That is,
This means that a large disturbance is given to the PLL, and the PLL
is no longer able to maintain the lock, the mislock is released, and a forced sweep is performed. This forced sweep signal (tl l゛ ρl-L should be sufficiently removed from mislock) 1"l l:'knee,',,'
,' 1 space width (1 word is about 1011S)+,
+=1. If there is, system control II, ':4', control sweep signal (I3), and then return to number 10/・H-T'l°p"f. Then, After that, the normal 1' sweep speed returns.Then, the system controller monitors the presence or absence of frame sync at 1T1, and even after a predetermined period of time (for example, about 10 m5, which is one sweep cycle in Fig. 9), frame sync is still not detected. If a frame sync is not detected, a forced sweep is performed again. By repeating this operation until a frame sync is detected, the Pll can be correctly set. An example of a flowchart in which the operation from starting the spindle motor to a stable state in which the linear velocity becomes normal using the diagonal configuration is shown in FIG. 11.12. The pickup laser diode (L
D) is converted to 2111f/l. After this diode stabilization time (approximately 200 m5) has elapsed, the spindle motor acceleration (ACC) is started at the same time as the focus servo pull-in operation is started. CC operation to this is approximately 500m5
After that, a hold (+-11-, r) operation is performed to keep the rotational speed approximately constant for lIt. If the focus servo is "1", the focus servo pull-in command is issued! 1 is issued and the focus servo pull-in command is issued for at least 100m5 (this 100m5 is). (This is the period during which the ACC operation approaches the J.
It is designed to reach a rotational speed of rpm. This is close to the rotational speed at which a specified linear velocity is obtained at the track radius (approximately 24 mm) of the innermost circumference of the disk (at the time of startup (the pickup is always located at the 21' radius). 29- During the 1-+l-D operation after the ACC operation, the focus servo lock state is detected, but since activation is always performed at the position where the track exists, this detection is performed by the reproduction R "signal level detection. At this point, if the focus servo is not locked, the tracking servo cannot operate and the recovered clock cannot be extracted, so the focus servo loop is opened and the focus servo pull-in operation is performed again. is repeated. If the focus cannot be pulled in after two tries, it is assumed that the focus cannot be started and is ejected. If the focus servo is locked, then the 1~locking servo loop is turned on. After a certain period of time (after the lock is stabilized), the frame sync (SYNC) servo operation is switched to.During the 5YNC servo, the demodulator 8 determines whether or not the playback frame sync is detected. Unless the sink is detected,
The disk rotation speed is still far from the correct value (
The range exceeds approximately ±4.6%, and this range is PL30
- Sweep range of L τ゛4, 32113Ml1712
00 K I-1z range) or mislock due to spurious.
Of course, it is impossible to transition to quartz servos. Therefore, the R signal is checked again (this is to check that the focus has not been caused by strong external vibrations, etc.), and the focus servo is checked to see if it is unlocked. If so, 1~
It becomes Tsubu mode. Playback R “If the signal is good, PL
Forced slider control of I- (forced sweep control tIl signal 8 in FIG. 8 is supplied) is performed, and as described in @, for example, after 1olIls has elapsed, it is determined again whether or not frame sync detection has been performed. That is, P1. is added to the recovered clock information. Since frame sync is detected when . Then, for example, repeat this loop a predetermined number of times vlIi! If frame sync is not detected even after returning, the mode shifts to eject mode. This is to take into consideration cases where the disc is dirty or the disc is bent upside down. When frame sync is detected, the switch is made to the A-2 servo for the first time, and a constant linear velocity movement is performed. The reason why it is sometimes impossible to detect is not that the linear velocity becomes correct instantly after turning on the frame 11 sync servo, but because it takes a certain amount of time for the moment of inertia of the disk, etc. The reason why the clock is not simply set to the timing state is to make the clock extraction as early as possible by 4 TJ.Next, during the so-called search operation that reproduces desired information by searching for address information, This address information is
1 piece is recorded at a specific location in 1 frame, and 98
One address unit consists of a frame, or 98 bits. The 16 bits after 8 of 98 bits 1 to 8 are CRC (C'/CI j CRed Und
a n CyCh (3Ck) 7'f It forms a bow and is designed to allow error detection. At the time of search, a target search address is specified, and the addresses are compared while performing a fast forward movement (slider control) of the relative position of the recording disk and the pickup information detection point in the disk half-stroke direction. . In order to make further corrections, the process of performing a slight forward movement, stopping it, applying tracking servo, extracting the reproduced clock, reading the address information, and comparing it with the search address is repeated many times. Therefore, in order to shorten the search operation, it is desirable that the time it takes for the address information to become legible after stopping the instep feed is as short as possible. On the other hand, during transport, the pickup crosses tracks one after another and the RE signal waveform is very disturbed, so the servo signal of the frame sync servo also has a large error, so it is not a good idea to apply the sync servo. Therefore, during I'V+ feed, the sync servo is turned off and the rotation speed is maintained (ILD) operation. After sending a predetermined distance, it is necessary to read the address information and compare it with the search address.
Due to the necessity of extracting a reproduced clock during this address reading period, it is necessary to control the linear velocity to a predetermined linear velocity or a velocity close to it. Therefore, during this period, the frame sync servo operation is switched. That is, H.L.
Fast-forwarding a predetermined distance while performing the D operation approaches the search address, turns off the ILD operation, then switches to the frame sync servo operation, and reads and compares addresses. Here, during fast forwarding, the error of the frame sync servo becomes large as described above, and therefore, during this time, this large error voltage is applied to the capacitor such as the LPF 45 in FIG. 3. In this case, a large current will be supplied to the spindle motor when fast forwarding is stopped and switched to frame sync servo operation, and correct servo operation will be performed after the linear velocity has once deviated greatly. Therefore, it takes a long time until the clock extraction r L L 7 locks again, which causes a long search operation. There-
34 = In order to prevent this drawback, when the sink servo is off, a reset signal is generated from the system controller 1 and the third
The capacitor in the frame sync servo system shown in the figure is discharged. FIG. 13 shows an example of a search operation, and shows a case where the search is started from an address portion smaller than the target search address. The period from to to t1 is a forward ψ feeding operation (FAST FWDl) period, during which the disk moves a predetermined distance in the radial direction while being maintained at a constant rotational speed by the HLD operation. [1~t
During 2, the address is read and compared with the search address while performing the sync servo operation. Since the search address is more human, FAST FWDI is performed again with H1-D operation between 12 and t3, and address comparison is performed with sync servo operation between t3 and t4. At this time, the search address is exceeded, so next 14~t5
During this period, the ILD operation is performed and the reverse direction fast-forwards for a predetermined distance (
FAST RVS), and address comparison is performed by sync servo operation between 15 and t6. Since it is smaller than the search address, t6 to [7 is 1
- While performing ILD operation, the above type or reverse fast forward operation (
FAST FWD1 or FAST RVS) to send a predetermined distance pickup shorter than FAST FWD1 or FAST RVS). Between 17 and t8, the addresses are compared using the sync servo, and if it is detected that the search address has been exceeded, a so-called jump operation using a tracking mirror or the like is performed instead of a fast forward operation. That is, the rotation angle of the tracking mirror is changed instantaneously to cause the spot light, which is the information detection point, to jump over the adjacent track. This jumping motion is divided into two stages. First t
During 8=-t9, jump reverse (jump to adjacent track in opposite direction) is performed for several to several dozen tracks (this is called multi-jump reverse), and then address comparison is performed.Jump of one track. The operation is instantaneous (approximately 100 to 500 μs). Therefore, the time during which the playback signal is disturbed is also about that amount. Therefore, if the jumps of several to several tens of tracks are performed at intervals of several milliseconds as described above, the playback The signal is a number 1 every few ms
The waveform is disturbed by 00 .mu.s, and with this degree of disturbance, it is sufficiently possible to control the linear velocity by the sink. Therefore, during multi-jump reverse, the rotation of the ice flap is controlled by the sink servo. Multi-jump reverse is performed and addresses are compared between t9 and tto, and when it is found that the search address has been exceeded, the transition to 100 is one track, so jump forward (
(jump to an adjacent track in the forward direction) and compare addresses until the search address is reached. Of course, rotation control is performed by the sync servo during the m period of jump forward. After reaching the search address at t I+, if PLAY'E- is specified, the quartz servo is used and normal playback occurs, and PAIJSE
If the mode is specified, it will be a pause action. The pause operation means that the operation of jumping and reversing one track at the search address point is repeated. During the pause operation, the playback signal is only disturbed by several 100 μs, which is one jump time, every several 1001113, which is one rotation time. It is quite possible to do this, so the disk rotation control may be switched to a quartz servo,
You may leave it as sink servo. Note that each step in FIG. 13 is repeated until the search address is exceeded. The example shown in FIG. 13 is just one example and various modifications are possible.The point is that the ILD operation is performed while the slider is being fed, and the frame sync servo operation is used when reading the address. . As shown above, according to the present invention, if frame sync is not detected during frame sync servo operation, a disturbance is forcibly applied to the clock extraction PLL so that it can lock to a normal or lock frequency. Therefore, from now on, it is possible to extract a normal lock signal and shift to quartz servo, which is convenient.

[Brief explanation of drawings]

Figure 1 is a diagram showing an example of a part of the EFM bow,
Fig. 2 is a block diagram for an embodiment of the present invention, Fig. 3 is a block diagram of a frame sync servo circuit, and Fig. 4 is a block diagram of a frame sync servo circuit.
Figure 4 is a block diagram of the frame sync servo circuit, Figure 4 is a diagram explaining the operation of the circuit in Figure 3, Figure 5 is a characteristic diagram of our frame sync servo,
FIG. 6 is a block diagram of Pl-1-, FIG. 7 is an operation waveform diagram of the circuit of FIG. 6, FIG. 8 is a frame diagram of the frame l\sync signal detection circuit, and FIG. 9 is a block diagram of P L1. , a sweep circuit diagram, FIG. 10 is a diagram explaining the circuit operation of FIG. 9, and FIGS. 11 and 12.
The figure shows the operation at disk startup.
FIG. 3 is a diagram illustrating an example of the operation at the time of zazzing. Explanation of symbols of main parts 1...System controller 2...Pickup 4...Frame sync servo device 6...
Spindle driver 7...PLL 8・Old...Demodulator 9・
...RAM 14 ... Phase comparator applicant Motohiko Fujimura, agent of Pioneer Corporation, patent attorney

Claims (1)

[Claims] A rotation control system for a recording disk on which a digital signal is recorded, including one full clock information of a predetermined frequency and a synchronization signal in which the maximum interval is inverted n times (integer is an integer of 1 or more). P that can be locked within a predetermined frequency range including the frequency of the clock information while detecting a period n times the maximum reversal interval and controlling the rotation of the disk using the detection signal.1. ,
The reproduced signal is supplied to the L-circuit to extract the clock signal, the extracted clock signal is used to demodulate the synchronization signal, and if the synchronization signal is not demodulated, the voltage of the PLL circuit is A method characterized by forcibly sweeping the oscillation frequency of a controlled oscillator.