JPS5970063A - Modulating circuit of frequency shift keying - Google Patents

Abstract

PURPOSE:To generate reference carrier of modulated wave precisely and continuously and to simplify a circuit configuration by supplying the average DC voltage of data ''1'' and ''0'' from an LPF to an FSK modulator at the generation of the reference carrier. CONSTITUTION:A clock generator 11 generates a clock signal with 50% duty at a prescribed frequency f0, an 1/K frequency divider 9 in an 1/M frequency divider 12 divides the input signal into 1/K.f0 and an 1/L frequency divider 10 divides the signal by 1/L to output 1/M.f0 from the frequency divider 12. The 1/M.f0 is inputted to a switch 14 through a data generator 13 and the output of the frequency divider 9 is also applied to the switch 14. The switch 14 is switched by the 3rd switching signal to output data signals ''1'', ''0'', ''1''. These data signals ''1'', ''0'', ''1'' are limited at their bands by an LPF 15 and the outputted data signal (e) is modulated by the FSK modulator 16. The value of 1/K of the frequency divider 9 is set up larger than the cutoff frequency of the LPF 15 and the FSK modulation is executed at the average DC voltage of data ''1'' and ''0'' to generate reference carrier for modulated wave precisely.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an FSKf modulation circuit arbitration path, and particularly to an F'SKeg circuit capable of transmitting a reference carrier wave.

(2) Background of the technology FSX modulation is to change the frequency of the carrier wave to 1'' and ``o'' of the input data, respectively.
This is a method for transmitting by shifting to fL''. Therefore, FS
It is difficult to directly measure the frequency of a K-modulated carrier wave. Therefore, when measuring frequency stability, etc., if it becomes necessary to measure the frequency of the unmodulated carrier wave (hereinafter referred to as the reference carrier wave) with frequency CJH+fL)/2, only the reference carrier wave is generated separately. It is necessary to measure the frequency.

(3) Prior Art and Problems A conventional FSK modulation circuit is shown in FIG. In the figure, 1 is a clock generator, 2 is a 1/M frequency divider, 3 is a data generator,
4 is a first switch, 5 is a low-pass filter, 6 is an FSK modulator, 7 is a high frequency amplifier, and 8 is a second switch.

For example, a clock signal with a duty ratio of 50 is generated from the clock generator 1, and the 1N signal is divided into 1/M by a 1/M frequency divider 2 and supplied to the data generator 3 as a reference clock signal. Ru. A data signal from the data generator 3 is supplied to the low-pass filter 5 via the first switch 4 in synchronization with the reference clock signal, and after being subjected to band limitation, is manually input to the FSKf adjuster 6. The modulated wave signal subjected to FSK modulation in the FSK modulator 6 is amplified by the high frequency amplifier 7 and output.

Now, when it becomes necessary to measure the frequency of a reference carrier wave in frequency stability measurements, etc., it is necessary to generate only the reference carrier wave separately in the steps described below.

That is, in FIG. 1: the first switching signal causes the first switching device 4 to
The input is switched from the data generator 3 to the second switch 8.

Then, the second switching signal forces the second switching device 8 to
A signal of 1" or 0" was input, and the output of the FSX modulation circuit 6 was set as a high frequency "fs+" or a low frequency frequency.

Therefore, in the conventional water power system mentioned above, base # = conveyance (4)
Purpose of the Invention The present invention has been made in view of the above-mentioned conventional drawbacks, and includes:
An object of the present invention is to provide an FSK modulation circuit that enables continuous transmission of reference carrier waves.

(5) Structure of the invention and the above-mentioned object is to divide the output of the clock generator into 1/M (M: an integer), and the divided clock is used after data is created based on the number. In a variable circuit that performs FSX modulation, the output of the clock generator is divided into M
A means for dividing the frequency by a factor of 1, and a switching means for taking out the output of the first frequency divider and inputting it to the fl14 unit through a low-pass filter, and inputting a predetermined DC signal to the modulator to generate a reference carrier signal. FSX is characterized by being able to generate
(by providing a modulation circuit).

(6) Embodiments of the invention Examples of the invention will be described below with reference to FIGS. 2 and 3. FIG. 2 is a block diagram showing an embodiment of the FSX modulation circuit according to the present invention, and FIG. 3 is a time chart showing output waveforms of main parts. In the figure, 11 is a clock generator, 12 is a 1/M frequency divider, and the clock generator 11
A first frequency divider 9 (hereinafter referred to as K) that divides the output of
It is called a 1/1 frequency divider 9. ) and a 20th frequency divider 10 (hereinafter referred to as 1/L frequency divider 10) that divides the frequency by 1/L. (M=KXL.

K, L, M are integers) 13 is a data generator, 14 is a switch 1, 15 is a low-pass filter, 16 is F' S K
The modulator 17 is a high frequency amplifier.

Now, when a clock signal with a frequency f and a data ratio of 50% as shown in FIG. 3(a) is output from the EI7R generator 11, the clock signal becomes as shown in FIG. 3(b). The frequency is divided by a 1/1 frequency divider 9, resulting in a clock signal having a frequency of fv'. Subsequently, as shown in FIG. 3(c), the frequency is divided by a 1/L frequency divider 10, and the frequency becomes fs<=7o, 1
== Lo > as the reference clock signal of De K L
fVz - is supplied to the generator 13. That is, frequency divider 9°10
A reference clock signal of frequency fs is supplied from the 1/M frequency divider 12 as in the conventional case. Based on this reference clock signal tone, the data generator 13 generates a data signal "1.0.1"" as shown in FIG. 3(d), for example.
is generated. The data signal is then passed through a switch 14 and subjected to band limitation by a low pass filter 15 as shown in FIG. 3(e). This band-limited data signal (e
) is received by the FSK modulator 16, and the FSKl & frequency signal (f) is amplified by the high frequency amplifier 17 and output.

Next, a method for generating a reference carrier wave will be explained. In this case, the third switching signal switches the switch 14 to the 1/1 frequency divider 9 side. And the frequency f shown in FIG. 3(b). The clock signal at / is directly input to the low-pass filter 15, subjected to band restriction, and input to the FSK modulator 16. By the way, the reference carrier frequency is (fn+fL)/2, so in order to generate
It is necessary to apply modulation using the average DC voltage of the 1" and "O" levels.

For this purpose, the frequency f of the output clock signal of the 1/1 frequency divider 9. / is the cutoff frequency f of the low-pass filter 15
Set the width and width to be sufficiently large. Specifically, the clock signal at frequency fa/ is passed through the low-pass filter 1.
It is desirable to set the value of fo/ so that the spurious emission intensity of the modulated wave modulated by the FSX modulator 16 passes through 5 and is below the allowable value specified in the spurious emission intensity standard. . That is, as the frequency fo/K of the output clock signal of the 1/K frequency divider 9 becomes larger than the cutoff frequency fc of the low-pass filter 15, the level of the clock signal at the output of the low-pass filter 15 is attenuated. Finally, approximately the average DC voltage of the clock signal is obtained. Therefore, if the frequency fo/K is sufficiently larger than the cutoff frequency fc of the low-pass filter, the output Gt of the low-pass filter 15 becomes an average DC voltage of approximately '1'' and 10'', as shown in FIG. 3(g). The FSK modulator 16 continuously outputs extremely approximate reference carrier waves as shown in FIG. 3(h).

Here, an example of the values of the frequency division ratios K and L will be shown. Now, the data generator 13 requires a reference clock signal of 16 KHz, and the oscillation frequency f of the clock generator 11 prepared for this purpose. Suppose that is 4.096 [:Mn2:].

In this case, the M field of the 1/M frequency divider is 256. In order to obtain a predetermined DC voltage output from the low-pass filter 15, the output clock signal frequency f of the 1/K frequency divider 9 is adjusted.

/ is set at 4 times so that the amount of attenuation becomes 70 dB or more when passing through the low-pass filter 15. So f. For example, set the value of / to 32 KHz. Then, the value of the frequency division ratio is 24096/32=128,
From this, L=come=256/128=2.

As explained above, by determining the value of L for the frequency division ratio and making the output signal of the low-pass filter 15 equal to the average DC voltage (!l:) of the 1''' and °'0# levels, accurate 0(7) that can generate a reference carrier wave of
Effects of the Invention As explained in detail above, according to the present invention, when generating a reference carrier wave, data "1" and "
Since the average DC voltage of °0''' is supplied to the FSK modulator, the reference carrier wave of the FSX modulated wave can be generated accurately and continuously.In addition, the circuit configuration is simpler than the conventional circuit. This makes it easy to operate.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional FSX modulation circuit, Figure 2 is a block diagram showing a conventional FSX modulation circuit.
The figure is a block diagram showing one embodiment of the present invention, and FIG.
3 is a time chart showing main part output waveforms in the figure. In the drawing, 1.11 is a clock generator, 2.12 is M
1/1 frequency divider, 3.13 is data generator, 4.8°14
is a switch, 5. '15 is a lowx filter, 6°16
is an FSK modulator, 7.17 is a high frequency amplifier, 9 is a 1/2 frequency divider, and 10 is a 1/L frequency divider. −&

Claims (1)

[Claims] Divide the output of the four-wave generator into 1/M (M: integer)
, in a modulation circuit that creates data based on the frequency-divided clock signal and then modulates it to FS', a lock is generated by dividing the output of the clock generator by an integer). means for dividing the output of the frequency divider into 1/M, and switching means for taking out the output of the first frequency divider and inputting it to the modulator via a low-pass filter, and applying a predetermined DC signal to the modulator. An FSKXN circuit characterized in that it is possible to input and generate a reference carrier wave.