JPS5969920A - Thin-film semiconductor device - Google Patents

Thin-film semiconductor device

Info

Publication number
JPS5969920A
JPS5969920A JP57180448A JP18044882A JPS5969920A JP S5969920 A JPS5969920 A JP S5969920A JP 57180448 A JP57180448 A JP 57180448A JP 18044882 A JP18044882 A JP 18044882A JP S5969920 A JPS5969920 A JP S5969920A
Authority
JP
Japan
Prior art keywords
film
added
layer
impurity
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57180448A
Other languages
Japanese (ja)
Inventor
Takeshige Ichimura
市村　剛重
Shigeru Kobayashi
茂 小林
Yukio Takeda
幸雄 武田
Masakazu Ueno
正和 上野
Yoshiyuki Uchida
内田　喜之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Corporate Research and Development Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Corporate Research and Development Ltd filed Critical Fuji Electric Corporate Research and Development Ltd
Priority to JP57180448A priority Critical patent/JPS5969920A/en
Publication of JPS5969920A publication Critical patent/JPS5969920A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02425—Conductive materials, e.g. metallic silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To obtain the thin-film semiconductor device, which has an excellent (i) film and consists of amorphous silicon, by forming an N layer in a silicon film containing a crystallite generated by the decomposition of a raw material gas to which a V family element is not added. CONSTITUTION:A film obtained by the 10cc/min gas flow-rate, 250cc/min hydrogen flow-rate and 0.07-0.3W/cm<2> discharge power of silane is a crystallite film containing 30-100% (a volume rate) of 30-200Angstrom crystalline silicon grains, and shows N type conductivity even when a PH3 impurity element is not added intentionally. The crystallite N film 2 not added is formed on a metallic substrate 1, a normal a-Si film 3 not added is formed, and a crystallite P type film 4 containing an addition impurity of 10<-2>% or less is formed, and a transparent conductive film 5 and a metallic latticed electrode 6 are formed, thus forming a photosensor of P-I-N structure. Since the impurity is not added to the N type layer 2 formed before forming the (i) film 3, the impurity is taken in on the formation of the (i) film, and the quality of the same is not deteriorated.

Description

【発明の詳細な説明】 この発明は、例えばその活性領域がシランのグロー放電
によって形成されたアモルファスシリコンから成る光起
電力素子、および整流素子のような薄膜半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to thin film semiconductor devices such as photovoltaic elements and rectifiers whose active regions are made of amorphous silicon formed by glow discharge of silane.

シランガスのグロー放電で得られたＨを含むアモルファ
スシリコン（以下ａ　−Ｓ　ｉ　ト記ス）ハ、結晶シリ
コンと同様に価電子制御が可能で、接合型半導体装置が
出来ることが示されて以来、低コスト、大面積半導体装
置への応用が・進められている。このａ−８ｉを用いた
ｐ　ｉ　ｎ、型半導体装置では、金属基板あるいは透明
導電膜をつけたガラス基板上に、シランあるいは添加不
純物元素を含むガスの直流あるいは高周波の高圧印加に
よるグロー放電分解番こより、ｐ形層、ｉ形層（添加不
純物元素を含まない層）、ｎ形層を積層させて構成する
。ショットキー形の場合には、同様の基板にｎ形層ある
いはｐ形層そしてｉ層、バリア金属を積層して構成する
。この場合、ｎ形層およびｐ形層中の添加不純物濃度は
１％にも達するのが普通である。その理由は、ａ−８ｉ
は結晶シリコンとちがって不規則構造のために不純物添
加効率が悪く、第１図（Ｗ、Ｅ、５ｐｅａｒ、Ｐ、Ｇ、
ＬｅＣｏｍｂｅｒ’：雑誌［フイロソフイカル＋１−７
ガジｙ　Ｊ　（Ｐｈ１ｌｏｓ、Ｍａｇ、　）　３３巻９
３５〜９４５頁（１９，７６年）に示すように１チの不
純物添加でも、その導電率が１Ｏ−３（Ω・ｃｒｎ）−
１活性化エネルギー０．２ｅＶｌ、か得られない。この
ためにａ−８ｉのｐ形あるいはｎ形層には不純物濃度を
高くせさるを得ない。Since it was shown that amorphous silicon containing H (hereinafter referred to as a-Si) obtained by glow discharge of silane gas can control valence electrons in the same way as crystalline silicon, and can be used for junction-type semiconductor devices. Application to low-cost, large-area semiconductor devices is progressing. In a pin-type semiconductor device using this a-8i, glow discharge decomposition is performed by applying direct current or high frequency high voltage of a gas containing silane or an added impurity element onto a metal substrate or a glass substrate coated with a transparent conductive film. Therefore, a p-type layer, an i-type layer (layer containing no added impurity element), and an n-type layer are stacked. In the case of a Schottky type, an n-type layer or a p-type layer, an i-layer, and a barrier metal are laminated on a similar substrate. In this case, the concentration of added impurities in the n-type layer and the p-type layer typically reaches as much as 1%. The reason is a-8i
Unlike crystalline silicon, impurity doping efficiency is low due to its irregular structure, as shown in Figure 1 (W, E, 5pear, P, G,
LeComber': Magazine [Philosophical +1-7
Gaziy J (Ph1los, Mag, ) Volume 33 9
As shown on pages 35-945 (1976), even with the addition of 1 tres of impurity, the conductivity is 1O-3(Ω・crn)-
1 activation energy of 0.2 eVl cannot be obtained. For this reason, it is unavoidable to increase the impurity concentration in the p-type or n-type layer of a-8i.

したがって、ａ　−Ｓ　ｉ半導体装置の製作においては
、ｎ形あるいはｐ形層中およびこの層を形成中、反応器
の壁についた高濃度の不純物、およびガス中に残留して
いる添加不純物が、続く工程であるｉ膜の成膜時にｉ膜
中に取り込まれ、半導体装置の特性上最も重要であるｉ
膜の膜質を低下させる欠点があった。Therefore, in the fabrication of a-Si semiconductor devices, high concentrations of impurities in the n-type or p-type layer and during the formation of this layer are present on the walls of the reactor and doped impurities remaining in the gas. It is incorporated into the i-film during the subsequent step of forming the i-film, and is most important for the characteristics of semiconductor devices.
There was a drawback that the quality of the membrane deteriorated.

更に、ｉ膜上につけた高濃度のｐ形層（あるいはｎ形層
）から、ｉ膜中に不純物元素が拡散するという欠点もあ
った。その上、この半導体装置を光起電力素子として使
う場合には、この高濃度不純物を含む層の光吸収が大き
いために、光活性領域であるｉ膜に到達する光量が減少
せられるという欠点もあった。Furthermore, there is also the drawback that impurity elements diffuse into the i-film from the highly concentrated p-type layer (or n-type layer) formed on the i-film. Furthermore, when this semiconductor device is used as a photovoltaic element, there is a drawback that the amount of light reaching the i-film, which is a photoactive region, is reduced due to the large light absorption of this layer containing high concentration impurities. there were.

この発明はこれらの欠点をすべて解決し、前に形成され
た膜中の添加不純物の影響を受けない良質なｉ膜をもつ
薄膜半導体装置を得ることを目的とする。The object of the present invention is to solve all of these drawbacks and to obtain a thin film semiconductor device having a high-quality i-film that is not affected by added impurities in previously formed films.

この目的は、少なくとも基板上にアモルファスシリコン
からなる複数の層が積層され、ｉ層の基板側にｎ層が存
在する薄膜半導体装置において、ｎ層がｖ族元素を添加
しない原料ガスの分解によって生成された微結晶を含む
シリコン膜であるこ本発明は以下の知見に基づく。This purpose is to develop a thin film semiconductor device in which multiple layers of amorphous silicon are laminated on at least a substrate, and an n layer exists on the substrate side of an i layer, in which the n layer is formed by decomposition of a raw material gas to which group V elements are not added. The present invention is based on the following findings.

第２図ｆａｔ　、　（ｂｌはシランのガス流量１０　ｃ
ｃ／分。Figure 2 fat, (bl is silane gas flow rate 10c
c/min.

水素流量２５０ＣＣＺ分、放電パワー０．０７〜０．３
Ｗ／ｃＩ！で得た膜の導電率（曲線Ｃ）と活性化エネル
ギ−（曲線Ａ）をＢ２几およびＰＨ３ガス濃度をパ゛ラ
メ−ターにして示したものである。これらの膜は第１図
のアモルファス膜とちがって、３０〜２００Ａの結晶シ
リコン粒を３０〜１００％（体積率）含む微結晶化膜で
ある。この膜は、第２図（ｂ）に示すようにＰＩ−１，
不純物元素を意図的に添加しなくてもｎ形導電性を示し
、その導電率は４Ｘ１０　　（Ωｃｎ１）−’活性化エ
ネルギーは０．２　ｅ　Ｖである。この値は１係もの高
い不純物濃度をもつアモルファスｎ形層と同程度である
。更にｎ形不純物を添加すれば導電率は増加し活性化エ
ネルギーは減少する。これでも不純物濃度はａ−８ｉの
ｎ形層に比べればｌ／　１０００以下である。Hydrogen flow rate 250CCZ, discharge power 0.07-0.3
W/cI! The electrical conductivity (curve C) and activation energy (curve A) of the film obtained in the above are shown using the B2 gas concentration and the PH3 gas concentration as parameters. These films, unlike the amorphous films shown in FIG. 1, are microcrystalline films containing 30 to 100% (volume percentage) of crystalline silicon grains of 30 to 200 A. As shown in FIG. 2(b), this film is composed of PI-1,
It exhibits n-type conductivity even without intentionally adding impurity elements, and its conductivity is 4X10 (Ωcn1) -'activation energy is 0.2 eV. This value is comparable to that of an amorphous n-type layer having an impurity concentration as high as a factor of 1. Furthermore, if n-type impurities are added, the conductivity will increase and the activation energy will decrease. Even with this, the impurity concentration is 1/1000 or less compared to the n-type layer of a-8i.

は、無添加微結晶化膜が既にｎ形であるために、ｐ形化
するためには、ｎ形層に比べて多くの不純活性化エネル
ギー０．２ｅＶであり、１％ものほう素を添加したｐ形
アモルファス膜と同程度の特性を示す。その上、これら
の微結晶化ｎ形あるいはｐ形層は、同等の特性をもつａ
−８ｉ膜に比べて光吸収係数が小さく、この膜は光を透
しやすいという性質をもっている。この様子を第３図に
示した。曲線３１は微結晶化ｎ形あるいはｐ形層の吸収
係数を表わし曲線３２．３３はそれぞれりん。Since the undoped microcrystalline film is already n-type, in order to change it to p-type, the impurity activation energy is 0.2 eV, which is higher than that of the n-type layer, and it is necessary to add as much as 1% boron. The properties are comparable to those of p-type amorphous films. Moreover, these microcrystalline n-type or p-type layers have similar properties.
The light absorption coefficient is smaller than that of the -8i film, and this film has the property of easily transmitting light. This situation is shown in Figure 3. Curve 31 represents the absorption coefficient of a microcrystalline n-type or p-type layer, and curves 32 and 33 respectively represent phosphorus.

はう素を含んだａ　−Ｓ　ｉ膜の吸収係数を表わす。It represents the absorption coefficient of an a-Si film containing boronate.

微結晶化膜の吸収係数はａ−８ｉ膜のそれに比べて小さ
くなっている。The absorption coefficient of the microcrystalline film is smaller than that of the a-8i film.

以上のように、微結晶化膜に微量の添加不純物（ａ−８
ｉに比べて１／１００〜１／１０００以刀を含む膜の特
性は高添加不純物濃度をもつａ−８ｉ膜と同程度の特性
をもち、なおかつ、先の透過性もよいことを示した。特
に微結晶化ｎ形層は、原料ガスにｖ族元素を添加しなく
てもこのような特性を示す。本発明はこれをｐｉｎ構造
のｎ層として利用したものである。As mentioned above, a trace amount of added impurity (a-8
It was shown that the properties of the film containing 1/100 to 1/1000 of that of the a-8i film were comparable to those of the a-8i film with a high concentration of added impurities, and the permeability was also good. In particular, the microcrystalline n-type layer exhibits such characteristics even without adding group V elements to the source gas. The present invention utilizes this as an n layer of a pin structure.

以下図を引用して本発明の実施例について述べる。第４
図において、金属基板１の上に無添加の微結晶化ｎ形２
を前述した条件で１００〜１００ＯＡの厚さに成膜し、
つづいて通常の無添加ａ−８ｉ膜３を０．４〜１μｍの
厚さに成膜し、次に１０″′２％以下の添加不純物を含
む微結晶化ｐ形層４を１００〜５００の厚さに成膜し、
その上に透明導電膜５をつけ、さらに金属格子電極６を
設けてｐｉｎ構造の光起電力素子が形成されている。し
かしｎ。Embodiments of the present invention will be described below with reference to the figures. Fourth
In the figure, an additive-free microcrystalline n-type 2 is placed on a metal substrate 1.
was formed into a film with a thickness of 100 to 100 OA under the conditions described above,
Next, a normal additive-free A-8I film 3 is deposited to a thickness of 0.4 to 1 μm, and then a microcrystalline p-type layer 4 containing 10"'2% or less of added impurities is deposited to a thickness of 100 to 500 μm. A film is formed to a thickness of
A transparent conductive film 5 is applied thereon, and a metal grid electrode 6 is further provided to form a pin-structured photovoltaic element. But n.

ｐ両膜２，４さも微結晶化膜を用いないで、第５図に示
すようにｎ形層２だけを微結晶化膜とし、ｐ形層は通常
のｐ形膜−８ｉ膜７で構成してもよい。このようにＩ膜
３の形成前に基板上に設けられるｎ形層２に不純物が添
加されていないので、ｉ膜の成膜時にｉ膜中に不純物が
取り込まれてｉ膜の膜質を低下させることがない。Both p-type films 2 and 4 do not use a microcrystalline film, but only the n-type layer 2 is made of a microcrystalline film, as shown in FIG. 5, and the p-type layer is composed of a normal p-type film-8i film 7. You may. In this way, since no impurity is added to the n-type layer 2 provided on the substrate before the formation of the I film 3, impurities are incorporated into the i film during the formation of the i film, reducing the film quality of the i film. Never.

第６図、第７図はガラス基板８を用い、基板側から光が
入射する光起電力素子における本発明の実施例を示し、
第４．第５図と共通の部分には同一の符号が付されてい
る。ガラス板８の上に透明導電膜５があり、上面電極９
が全面に設けられているちがいはあるが、１層２，１層
３およびｐ層４あるいは９層７の形成法、順序などは金
属基板ｉ膜に入る光景が増加する効果も生ずる。6 and 7 show an embodiment of the present invention in a photovoltaic device using a glass substrate 8 and in which light enters from the substrate side,
4th. Components common to those in FIG. 5 are given the same reference numerals. There is a transparent conductive film 5 on the glass plate 8, and a top electrode 9
Although there is a difference in whether the 1st layer 2, 1st layer 3, and the p layer 4 or 9th layer 7 are formed, the formation method, order, etc. of the 1st layer 2, 1st layer 3, and the 9th layer 7 have the effect of increasing the amount of sight that enters the metal substrate i-film.

第８図はショットキー構造の実施例を示す。金属基板１
の上に無添加ｎ形微結晶化膜２を１００〜ｘｏｏｏＸの
厚さに形成し、次に０．４〜１μｍの厚さのａ−８ｉの
１層３、Ｐ　ｔ　、　Ａ　ｎなどのバリア金属１０の順
に構成する。FIG. 8 shows an example of a Schottky structure. Metal substrate 1
An additive-free n-type microcrystalline film 2 is formed thereon to a thickness of 100 to xooooX, and then a layer 3 of a-8i with a thickness of 0.4 to 1 μm, a barrier such as P t , An etc. Constructed in the order of metal 10.

以上にのべたこの発明による光起電力素子の構造は、−
見上従来のａ　−Ｓ　ｉ光起電力素子の構造と変わりが
ないが、基板上のｎ形層に不純物を添加しない微結晶化
ａ　−８ｉ膜を用いた結果、次の点において、大きなち
がいがある。The structure of the photovoltaic device according to the present invention described above is -
Although the structure is apparently the same as that of a conventional a-Si photovoltaic element, there are major differences in the following points as a result of using a microcrystalline a-8i film without adding impurities to the n-type layer on the substrate. There is.

その一つはｎ形層に不純物が添加されていないこと、お
よびこの膜をつくるときのガス中に不純物がないために
、次いで形成される光電流発生領域として重要であるｉ
膜が添加不純物によって汚染されることがない結果、良
質なｉ膜が保持されていることである。One of them is that no impurities are added to the n-type layer, and since there are no impurities in the gas used to form this film, it is important as a photocurrent generating region that will be formed next.
Since the film is not contaminated by added impurities, a high quality i film is maintained.

その二つめは、微結晶化膜の光透過性がよいために光損
失が少なく、これを光の入射側に用いたときはｉ膜によ
り多くの光を導入出来る。Ｃｂる窓効果が大きいことで
ある。The second reason is that the microcrystalline film has good light transmittance, so there is little light loss, and when it is used on the light incident side, more light can be introduced into the i-film. Cb has a large window effect.

以上の前にも述べた利点のほかに三つめとして、添加不
純物元素は毒性であることが多く、安全上その原料ガス
きしては出来るだけ希釈して使用し原料ガスの使用が少
なくて済む利点がある。In addition to the above-mentioned advantages, the third advantage is that added impurity elements are often toxic, so for safety reasons, the raw material gas should be diluted as much as possible to reduce the amount of raw material gas used. There are advantages.

この発明はいままで説明した光起電力素子のほかにｐｉ
ｎまたはｎｉ接合をもつアモルファスシリコン半導体装
置に応用できる。In addition to the photovoltaic device described above, this invention
It can be applied to amorphous silicon semiconductor devices having n or ni junctions.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はａ　−Ｓ　ｉの不純物添加量と導電率および活
性化エネルギーとの関係曲線、第２図（ａ）、　（ｂ）
は微結晶化ａ−８ｉ膜の不純物添加量と導電率および活
性化エネルギーとの関係曲線で（ａ）はｐ形層、（ｂ）
はｎ形層、第３図はａ−８ｉ膜と微結晶化膜の光吸収係
数と波長との関係線図、第４図、第５図はそれぞれ金属
基板をもつ光起電力素子における本発明の二つの実施例
の断面図、第６図、第７図はそれぞれガラス基板をもつ
光起電力素子における本発明の二つの実施例の断面図、
第８図はショットキー構造光起電力素子における本発明
の実施例の断面図である。 １・・・金属基板、２・・・微結晶化ｎ膜、３・・・ａ
−８ｉｌ膜、４・・・微結晶化ｐ膜、７・・・ａ−８ｉ
、ｐ膜、８・・・ガラス板、１０・・・バリア金属０原
料ガス組威 牙１図 （Ｑ）（ｂ） ７２図 第３図 ｆ５図 オフ図Figure 1 shows the relationship curve between the amount of a-Si impurity added, conductivity, and activation energy, Figure 2 (a), (b)
are the relationship curves between the amount of impurity added and the conductivity and activation energy of the microcrystalline A-8i film, (a) is the p-type layer, (b)
is an n-type layer, FIG. 3 is a diagram of the relationship between the light absorption coefficient and wavelength of the A-8I film and the microcrystalline film, and FIGS. 4 and 5 are the present invention in a photovoltaic device having a metal substrate, respectively. 6 and 7 are cross-sectional views of two embodiments of the present invention in a photovoltaic device having a glass substrate, respectively,
FIG. 8 is a sectional view of an embodiment of the present invention in a Schottky structure photovoltaic device. DESCRIPTION OF SYMBOLS 1... Metal substrate, 2... Microcrystallized n film, 3... a
-8il film, 4... Microcrystallized p film, 7... a-8i
, p film, 8...Glass plate, 10...Barrier metal 0 Raw material gas assembly 1 Figure (Q) (b) Figure 72 Figure 3 Figure f5 Off view

Claims (1)

【特許請求の範囲】[Claims] ｌ）基板上にアモルファスシリコンからなる複数の層が
積層され、ｉ層の基板側にｎ層が存在するものにおいて
、ｎ層が■族元素を添加しない原料ガスの分解によって
生成された微結晶を含むシリコン膜であることを特徴と
する薄膜半導体装置。l) In a structure in which multiple layers of amorphous silicon are laminated on a substrate, and an n layer exists on the substrate side of the i layer, the n layer contains microcrystals generated by decomposition of a raw material gas that does not contain group II elements. 1. A thin film semiconductor device characterized by being a silicon film containing silicon.
JP57180448A 1982-10-14 1982-10-14 Thin-film semiconductor device Pending JPS5969920A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57180448A JPS5969920A (en) 1982-10-14 1982-10-14 Thin-film semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57180448A JPS5969920A (en) 1982-10-14 1982-10-14 Thin-film semiconductor device

Publications (1)

Publication Number Publication Date
JPS5969920A true JPS5969920A (en) 1984-04-20

Family

ID=16083403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57180448A Pending JPS5969920A (en) 1982-10-14 1982-10-14 Thin-film semiconductor device

Country Status (1)

Country Link
JP (1) JPS5969920A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0949685A2 (en) * 1998-03-16 1999-10-13 Canon Kabushiki Kaisha Semiconductor element and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0949685A2 (en) * 1998-03-16 1999-10-13 Canon Kabushiki Kaisha Semiconductor element and its manufacturing method
EP0949685A3 (en) * 1998-03-16 2007-06-13 Canon Kabushiki Kaisha Semiconductor element and its manufacturing method

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