JPS5968947A - Electrical apparatus - Google Patents

Abstract

PURPOSE:To prevent transmission delay by Mirror effect by separating the wirings for electrical signals which are changed each other in the relation of reversed phase and arranging approximately the lines for sub-signals sent from the same signal source. CONSTITUTION:The ground wire GND, 4-bit signal lines A1-A4, B1-B4, clock phi1, power supply line Vcc are approximately wired in parallel on a SOS substrate, and the signal lines A1-A4 are connected to the poly-Si leadout lines D1-D4 through windows C1-C4. Simultaneously, the signal lines A1-A4 in which signals may be changed reversely are not approximated and the signal lines B1-B4 in which signals may change in the other timings are alternately provided. Thereby, the rising/falling times can be improved by about 40% or more due to reduction of effective capacitance between the adjacent wirings. For the signal lines A0-A2, the sub-signal lines A01-A22 are respectively disposed in both sides of wiring. For A1, the same electrical signal is applied to A11, A12 and a current of A11, A22 is set to 1/2 of A1. At this time, operation of A1 occurs quicker than that of A11, A12 and the rising/falling time is improved by 70% or more than the conventional time. This structure is very effective for IC having a small capacity of wiring to the ground and a large wiring capacitance and is capable of remarkably improving signal delay.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an electrical device having signal line wiring in which a plurality of signal lines each transmitting electrical signals of various phases are arranged substantially in parallel.

[Technical background of the invention and its problems] In logic elements such as microcomputers, gate arrays, etc., or memories with multi-bit configurations, 8 to 16
The signal lines are arranged in parallel with bus lines arranged adjacent to each other in parallel. for example.

FIG. 1 shows a sectional view of the central portion of an 8-bit microcomputer. These are silicon-on-SOS (SOS) interconnects, with a silicon oxide film about 1 μm thick being exposed on the sapphire layer, and aluminum interconnections W1, W2, 1 μm thick and L μm wide. There is W3.

These aluminum wirings Wl, W2. W3 is the interval Sμ
It is arranged vertically. Figure 2 is.

When the substrate is a conductor, this corresponds to bulk LSI wiring. Aluminum wirings Wl, W2 . There is W3.

The time Δ↑ required to drive the aluminum wiring by a potential ΔV is given by the following equation, where YI is the drive current of the drive source and C is the capacitance of the wiring.

Δt=Equation...(1) ■ The capacitance RC of this wiring is the capacitance C・
and the ground capacity Cg. However, ■ Considering changes in adjacent wiring, the effective capacitance CF.

depends on the potential change of the adjacent wiring as follows.

■ In the case of reverse phase change If one of the adjacent wires changes from high voltage to low voltage, and the other wire simultaneously changes from low voltage to high voltage in reverse phase,
It is considered that the voltage change was relatively doubled. Therefore, CF,=2C1+Cg (2
).

■ In the case of a different phase change If one of the adjacent wirings changes and the other does not change at the same time, then CE=Ci+Cg . . . +3J.

■ In the case of in-phase change If both adjacent wires are in the same phase and change in the same direction at the same time, it is considered that there is no relative voltage change, so c = c... (4) It becomes g.

According to the actual measured value of the effective capacitance CE of the wiring shown in FIGS. 1 and 2 shown in FIGS. 3 and 4, there is a large difference between the three aspects described above. In the case of on-sapphire wiring, the ratio is approximately 2:1:0. According to equation (1), this difference in effective capacitance directly affects the operating speed, and especially in the case of negative phase change (2), it causes an unacceptable delay in signal line operation. However, in conventional electrical devices, the wiring does not take such things into account, causing a problem in that transmission signals are delayed due to delays due to the mirror effect.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to prevent delays in transmission signals caused by such mirror effects.

[Summary of the invention]

In order to achieve this object, the electrical device according to the first invention is characterized in that mantissa signal lines that transmit electrical signals that change in an antiphase relation to each other are arranged apart from each other.

Further, the electric device according to the second invention is characterized in that a sub-signal line that conveys an electric signal from the same signal source is arranged close to a signal line that conveys an electric signal from the signal source.

[Embodiments of the invention]

An electrical device according to an embodiment of the first invention is shown in FIG.

Figure 5 shows the bus wiring for electrical equipment.
ND, 4-pit signal line A□, A2゜A3. A4. Signal lines B, , B2. B3. B4. Clock φ0. power av. Aluminum wires are arranged in parallel and close to each other on a silicon substrate. Signal line A□,
A2. A3. A4 is contact C.

The lead line D1 of the polysilicon layer is formed by C2, C3, and C4.
．． D2. D3. Connected to D4. As shown in Figure 6, signal lines A□, which may change in opposite directions at the same time,
A2. A3. A4 is not placed adjacent to the signal line B□, B2 . B3. B4 are arranged alternately.

According to this example, the rise/fall time (in all rooms) can be improved by more than 40%. This is due to the fact that the effective capacitance between adjacent wirings according to this example is reduced as shown in equation (3). It is something.

Note that if there is no signal line that changes at another timing, a wiring that does not change, such as a ground line or a power line, may be inserted between the signal lines.

Next, an electric device according to an embodiment of the second invention is shown in FIG. Signal line A as shown in FIG. , A□.

A sub signal line A for each A2. 1. Ao2. A□□
.

A□2. A2□ and A2□ are placed on both sides. For example, enter two sub signal lines for signal line A1, A and 2.
for.

The same electrical signal is transmitted. Signal line A1 and sub signal line A□1. A1□ is driven by separate drive transistors, and the sub signal line A□□.

The current value flowing through A1□ is set to 1/2 of the current value flowing through signal line A□. Signal line A□ and sub signal line A1□.

Regarding the operation of A12, as shown in FIG. 9, the operation of the signal line A□ is faster than the operation of the sub signal lines AH and A□2.

This means that more current (flows) and the sub signal lines A0□ on both sides
, A□2, the same electrical signal is flowing through them, so the effective capacitance between the wirings is as shown by equation (4).

In this way, according to this embodiment, the rise/fall time is approximately 70% compared to the conventional example, as shown in FIG.
This can be improved. Note that even if only one sub-signal line is provided, a certain effect can be expected.

In the embodiments of the first invention and the second invention, the wiring of an integrated circuit on a silicon-on-sapphire (SOS) substrate has been described, but the wiring on a printed circuit board or the wiring having a bundle of ordinary wires is also described. The first invention and the second invention can also be applied to the device.

Note that the actual measured values in Figures 3, 4, 7, and 10 are for a silicon-on-sapphire substrate, with an aluminum wiring layer thickness of 1 μm, an underlying interconnection layer thickness of 1 μm, and a silicon-on-sapphire substrate. The sapphire layer is 250 μm, and the relationship between the wiring spacing S and the wiring width was actually measured by changing L, assuming that S=1.5L.

〔Effect of the invention〕

As described above, according to the present invention, delay in transmission signals due to the Miller effect can be significantly improved.

This is particularly effective when the wiring has a small ground resistance and a large wiring capacitance, as in the case of an integrated circuit on a silicon-on-sapphire substrate.

[Brief explanation of drawings]

Figures 1 and 2 are cross-sectional views showing specific examples of signal line wiring in conventional electric devices, respectively. Figures 3 and 4 are cross-sectional views showing the effective relationship between wiring in the electric devices shown in Figures 1 and 2, respectively. Graph showing capacity. FIG. 5 is a plan view showing the signal line wiring of the electrical device according to one embodiment of the first invention, FIG. 6 is a time chart showing the electrical signals of the device, and FIG. 7 is the rise of the electrical signal of the device. /Graph showing fall time. Fig. 8 is a plan view showing the signal line wiring of the electric device according to the disaster embodiment of the second invention, Fig. 9 is a time chart showing the electric signal of the same device, and Fig. 10 is the rise of the electric signal of the same device. /
It is a graph showing fall time. Wl, W2. W3...aluminum wiring, L...wiring width, S...wiring spacing, co...inter-wiring effective capacitance,
Ao. A□, A2. A3. A4. B□, B2yB3*
B4 signal line, C□, C2, C3, C4...Contact, D, D2 p D3 'D4...Leader line, Aol j A02 j A11 j A12 e
A211A2゜...Sub signal line, GND...Saiji line,
■cc...power line, φ1...clockwise.

Claims (1)

[Claims] 1. In an electrical device having signal line wiring in which a plurality of signal lines each transmitting electrical signals of various phases are arranged substantially in parallel, a plurality of signals transmitting electrical signals that change in an opposite phase relationship with each other. An electrical device characterized by wires arranged at a distance from each other. 2. In an electrical device having signal line wiring in which a plurality of signal lines each transmitting electrical signals of various phases are arranged substantially in parallel. An electric device characterized in that a sub-signal line that conveys an electric signal from the same signal source is arranged close to a signal line that conveys an electric signal from the signal source.