JPS5968921A - Formation of thin film - Google Patents

Formation of thin film

Info

Publication number
JPS5968921A
JPS5968921A JP17940582A JP17940582A JPS5968921A JP S5968921 A JPS5968921 A JP S5968921A JP 17940582 A JP17940582 A JP 17940582A JP 17940582 A JP17940582 A JP 17940582A JP S5968921 A JPS5968921 A JP S5968921A
Authority
JP
Japan
Prior art keywords
film
substrate
chamber
thin film
psg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17940582A
Other languages
Japanese (ja)
Inventor
Juro Yasui
安井 十郎
Shohei Shinohara
篠原 昭平
Masanori Fukumoto
正紀 福本
Shozo Okada
岡田 昌三
Koichi Kugimiya
公一 釘宮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17940582A priority Critical patent/JPS5968921A/en
Publication of JPS5968921A publication Critical patent/JPS5968921A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

PURPOSE:To obtain a thin film with very low content of impurities by a method wherein a film forming chamber and pre-exhaust chamber are provided adiacent to each other and a door is provided between them and after a PSG film is formed on a lower surface of a quartz substrate placed in the film forming chamber by CVD method a semiconductor substrate placed in the pre-exhaust chamber is transferred into the film forming chamber and the PSG film is transferred onto the semiconductor substrate by plasma CVD method. CONSTITUTION:A plurality of semiconductor substrates 10 are put on a substrate holder 11 and placed in a pre-exhaust chamber 2 and a door 13 to an adjacent film forming chamber 1 is closed and the chamber 2 is exhausted by an exhaust pipe 12. On the other hand, a quartz substrate 3, the 1st substrate, is placed and a PSG film 14 is formed on a lower surface of the 1st substrate. Then the door 13 is opened and the holder 11 is transferred onto a parallel electrode 6 for plasma CVD placed below the substrate 3. Then Ar gas is introduced from an inlet 8 and a voltage is applied between a supporting electrode 4 in which a magnet is contained and a sputtering electrode 5 to drive Si, O and P atoms out by Ar ions and the PSG film 15 is formed on the substrate 10.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造工程における薄膜の形成方法
に関る。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of forming a thin film in the manufacturing process of a semiconductor device.

従来例の構成とその問題点 半導体装置、例えばMO8LSIの製Zl;工程におい
て絶縁体、半導体あるいは金属の薄膜が何度か形成され
るが、その形成方法は薄膜の神類に応じて大気圧下又は
減圧下におけるCVD法(chemical vapo
r deposition二気相化学堆積法)、真空蒸
着法、スパッタリング法等が選ばれる。たとえばSiゲ
ー)MO8LSIの製造工程においては多結晶S1より
なる第1層配線とA1よりなる第2層配線間の層間絶縁
膜として5102膜やPSG (リンケイ酸ガラス)膜
がCVD法で形成される。
Structures of conventional examples and their problems Semiconductor devices, for example, MO8LSI manufacturing Zl; thin films of insulators, semiconductors, or metals are formed several times in the process, and the method of forming them depends on the nature of the thin film. Or CVD method under reduced pressure (chemical vapor
(r deposition method), vacuum evaporation method, sputtering method, etc. are selected. For example, in the manufacturing process of MO8LSI (Si game), a 5102 film or a PSG (phosphosilicate glass) film is formed by CVD as an interlayer insulating film between the first layer wiring made of polycrystalline S1 and the second layer wiring made of A1. .

CVD法で形成されたSiO2膜やpsG膜は重金属や
アルカリイオン等MO3LSIの特性に悪影響を及ぼす
不純物の含有量が少ない。これはガスの精製が答易なた
めCVD法ではSiH+ 、 02やPHs等高純度の
反応ガスを用いるためである。一方GVD法は庶温たと
えば450℃で薄膜を形成するためにこの薄膜は基板へ
の密着力が弱く緻密さが不十分である。したがって密着
力を強化し緻密にして層間絶縁膜として十分な特性をも
たせるために1”OOO″Cに近い高温での熱処理を施
こす必要がある。
The SiO2 film and psG film formed by the CVD method have a low content of impurities such as heavy metals and alkali ions that adversely affect the characteristics of MO3LSI. This is because the CVD method uses highly purified reaction gases such as SiH+, 02, and PHs because gas purification is easy. On the other hand, since the GVD method forms a thin film at a normal temperature, for example, 450° C., this thin film has weak adhesion to the substrate and is insufficiently dense. Therefore, in order to strengthen the adhesion, make it dense, and have sufficient characteristics as an interlayer insulating film, it is necessary to perform heat treatment at a high temperature close to 1"OOO"C.

LSIの高密度化が進み微細寸法のMOS トランジス
タを形成するためにはソース、ドレインの接合深さを浅
くする必要がある。たとえばゲート長が1・5μmのM
OS)う/ジスクを形成するにはソース、ドレイ/の接
合深さを0・3μm程度にする必要があり、ソース、ド
レイ/領域にイオン注入でB−i添加した後は、従来の
1000℃という高温の熱処理を施すことができない。
In order to form MOS transistors with fine dimensions as the density of LSIs continues to increase, it is necessary to reduce the junction depth of the source and drain. For example, M with a gate length of 1.5 μm
To form the OS) disk, it is necessary to make the junction depth of the source and drain region about 0.3 μm, and after adding B-i to the source and drain region by ion implantation, it is necessary to It is not possible to perform high-temperature heat treatment.

そのため層間絶縁膜としてC,VD法で形成しただけの
SiO2膜やPSG膜は、緻密さが不十分なため層間絶
縁膜として必要な絶縁耐圧あるいは不純物阻止能かアル
カリイオン捕獲力などが劣る。
Therefore, a SiO2 film or a PSG film formed only by the C or VD method as an interlayer insulating film is insufficiently dense and is inferior in dielectric strength, impurity blocking ability, alkali ion capturing ability, etc. necessary for an interlayer insulating film.

寸だLSIの層間絶縁膜としてCVD法で形成した前記
の5102膜やPSG膜は下部配線上でのステンプカバ
レッジが悪い。そのためにこれら5102膜かPSG膜
上に形成した上部配線は下部配縁と交差する部分で厚さ
が小となったり、エツチノグによるパターン形成の際に
線幅が細くなったり、さらにひどくなると断線さえも生
じやすくなる。この問題を解決するために層間絶縁膜に
高濃度のリンを含むPSG膜を形成し1000℃のり/
を含む雰囲気中で熱処理を施して流動させる、いわゆる
リフロー処理を行っていた。しかしながらこの1000
℃の高温の熱処理であるリフロー処理も前述のように浅
いソース、ドレイ/接合を形成するためには行なうこと
ができず、したがって高密度のLSI製造においては上
部配線の細りか断線等の問題が生ずることが多い。
The 5102 film and PSG film formed by the CVD method as an interlayer insulating film of a large scale LSI have poor stamp coverage on the lower wiring. For this reason, the thickness of the upper wiring formed on these 5102 films or PSG films may become smaller at the portions where they intersect with the lower wiring, the line width may become thinner during pattern formation using etching nog, or even breakage may occur. It also becomes more likely to occur. To solve this problem, we formed a PSG film containing a high concentration of phosphorus as an interlayer insulating film, and
A so-called reflow treatment was performed in which the material was heat-treated in an atmosphere containing . However, this 1000
Reflow processing, which is heat treatment at a high temperature of °C, cannot be performed to form shallow sources and drains/junctions as mentioned above, and therefore problems such as thinning or disconnection of upper wiring occur in high-density LSI manufacturing. It often occurs.

以上に述べたように高温の熱処理を施すことができない
高密度LSIの製造工程においては従来のCVD法で形
成した層間絶縁膜は製造歩留りや信頼性の低下の大きな
原因となる。
As described above, in the manufacturing process of high-density LSIs in which high-temperature heat treatment cannot be performed, interlayer insulating films formed by conventional CVD methods are a major cause of deterioration in manufacturing yield and reliability.

発明の目的 本発明は不純物の含有量が少なく、さらに高温で熱処理
を施さなくても十分に特性の良い薄膜を形成する方法お
よび薄膜形成装置を提供することを目的とする。
OBJECTS OF THE INVENTION An object of the present invention is to provide a method and a thin film forming apparatus for forming a thin film with a low content of impurities and sufficiently good characteristics without the need for heat treatment at high temperatures.

発明の構成 薄膜の形成方法の一つにスパンクリング法がある。これ
はたとえばArイオンを高電界で加速しターゲットに衝
突させてターゲットを構成する原子を解離させターゲッ
トに対向して置かれたたとえば半導体基板に付着させる
ことにより薄膜を形成するものである。
One of the methods for forming thin films constituting the invention is the spankling method. In this method, for example, Ar ions are accelerated in a high electric field and collided with a target to dissociate the atoms constituting the target and deposit them on, for example, a semiconductor substrate placed opposite the target, thereby forming a thin film.

本発明の薄膜形成方法は、前述のCVD法で第1のノ占
仮に薄膜を形成しひき続いてこの薄膜が形成された第1
の基板をターゲットとしてスパッタリング法によシ対回
して置かれた半導体基板の表iA+に所望の厚さの薄膜
を形成することを特徴とするものである。
The thin film forming method of the present invention includes forming a thin film on a first layer by the above-mentioned CVD method, and subsequently forming a thin film on a first layer on which this thin film is formed.
The method is characterized in that a thin film of a desired thickness is formed on the surface iA+ of a semiconductor substrate which is rotated around the substrate by a sputtering method using the substrate as a target.

すでに述べたようにCVD法で第1の基板に形成したl
’4!7膜は純度の高い反応ガスを月1いることによっ
て不純物含有量を十分に少なくすることができる。
As already mentioned, the l formed on the first substrate by the CVD method
The '4!7 membrane can sufficiently reduce the impurity content by supplying highly pure reaction gas once a month.

一方、スパッタリング法ではターゲットがら解離した原
子は商いエネルギーを有している。これは高電界で加速
された高エネルギーのArイオンによりターゲット表面
からたたき出されたためで、この高エネルギーの原子が
半導体基板表面に伺着することによシ形成された薄膜は
半導体)、(板への密着力が強く高温の熱処理を施さな
くても十分な緻密さを有している。
On the other hand, in the sputtering method, atoms dissociated from the target have commercial energy. This is because the high-energy Ar ions accelerated in a high electric field are ejected from the target surface, and the thin film formed by these high-energy atoms landing on the semiconductor substrate surface (semiconductor), (semiconductor) It has strong adhesion to the surface and is sufficiently dense even without high-temperature heat treatment.

したがって本発明は上述のようLL特性の良い薄膜をス
パッタリング法で形成する際に、不純物含有量の少ない
薄膜がCVD法で表面に形成された第1の基板を、しか
もこの薄膜が形成されたあと外部から汚染されることな
く半導体基板に対向させてクーゲットとして用いるもの
である。
Therefore, when forming a thin film with good LL characteristics by a sputtering method as described above, the present invention provides a first substrate on which a thin film with a low impurity content is formed by a CVD method, and furthermore, after this thin film is formed. It is used as a cugette facing a semiconductor substrate without being contaminated from the outside.

実施例の説明 以下に本発明の一実施例を説明する。Description of examples An embodiment of the present invention will be described below.

本実施例での薄膜形成装置の断面図を第1図に示す。A cross-sectional view of the thin film forming apparatus in this example is shown in FIG.

第1図に示す薄膜形成装置は膜形成室1と予備、?11
−気室2を有している。膜形成室1内には第1の基板た
とえば石英基板3と、これを保持し、保持する石英基板
3′f:加熱するための加熱装置及びスパック時に電子
を加速するだめの磁石を内蔵する保持電極4、スパッタ
用電極6、対向電極6が設けられ、さらにCVD用の反
応ガス導入管7、スパッタ用のムrガス導入管8と膜形
成室1内を排気するために排気ポンプにつながる排気管
9が接続されている。
The thin film forming apparatus shown in FIG. 1 includes a film forming chamber 1 and a spare chamber. 11
- It has an air chamber 2. Inside the film forming chamber 1, there is a first substrate, for example, a quartz substrate 3, and a quartz substrate 3'f for holding and holding the same: a holder containing a heating device for heating and a magnet for accelerating electrons during sputtering. An electrode 4, a sputtering electrode 6, and a counter electrode 6 are provided, and furthermore, a reaction gas introduction pipe 7 for CVD, a mixed gas introduction pipe 8 for sputtering, and an exhaust pipe connected to an exhaust pump to exhaust the inside of the film forming chamber 1. A pipe 9 is connected.

予備排気室2には半導体基板10を載置した半導体基板
保持具11があり、排気ポンプにつながる排気管12が
接続されている。また膜形成室1と予備排気室2どの隔
壁には扉13が設けられており、この扉13を開けて半
導体基板IC)’(1−載置して半導体基板保持具11
を予備排気至2から膜形成室ivCあるいはその逆方向
に搬送するための搬送装置も設けられている。
The preliminary exhaust chamber 2 has a semiconductor substrate holder 11 on which a semiconductor substrate 10 is placed, and is connected to an exhaust pipe 12 leading to an exhaust pump. Further, a door 13 is provided on the partition wall of the film forming chamber 1 and the preliminary exhaust chamber 2, and when the door 13 is opened, the semiconductor substrate IC)'(1-1) is placed on the semiconductor substrate holder 11.
A conveyance device is also provided for conveying the gas from the preliminary exhaust gas 2 to the film forming chamber ivC or in the opposite direction.

この薄膜形成装置を用いて半導体基板1oの表面にPS
G膜を形成する場合について説明する。
Using this thin film forming apparatus, PS is applied to the surface of the semiconductor substrate 1o.
The case of forming a G film will be explained.

複数の半導体基板10が半導体基板保持具11に載置さ
れて予備排気室2に置かれる。扉13が閉じられ排気管
12につながった排気ポンプにより予備排気室2内が排
気される。
A plurality of semiconductor substrates 10 are mounted on a semiconductor substrate holder 11 and placed in the preliminary evacuation chamber 2. The door 13 is closed and the interior of the preliminary exhaust chamber 2 is exhausted by the exhaust pump connected to the exhaust pipe 12.

一方膜形成室1内では第1の基板である石英基板3表面
にPSG膜1膜圧4VD法で形成される。
On the other hand, in the film forming chamber 1, a PSG film is formed on the surface of a quartz substrate 3, which is a first substrate, by the 4VD method.

1ず膜形成室1が排気管9につながる排気ポンプで真空
度が1Q  ’1:orrになる壕で排気され、その間
に保持電極4に保持された石英基板3は保持電極4の加
熱装置によ5350’Cになるまで加熱される。その後
反応ガス導入管7から反応ガスであるSiH4,02、
PH5が導入され膜形成室1内の真空度が10 TOr
rに安定した後、対向電極6と保持型1極4間に高周波
電力が印加される。両電極間では反応ガス分子が高周波
電力により励起されガス間の反応が起りやすくなる。そ
の結果、保持電極4に保持され加熱された石英基板30
表面にPHsガスより分解したp−1含む5IH4と0
2  との反応により形成された5102膜、すなわち
PSG膜1膜圧4成される。PSG膜1膜圧4捷れるP
の量は例えば4重量係になるようPH3の流量を制御し
、膜厚は例えば1μmになるように反応時間すなわち高
周波電力の印加時間を制御する(第1図a)。
1. The film forming chamber 1 is evacuated by an exhaust pump connected to an exhaust pipe 9 in a trench with a vacuum level of 1Q'1:orr, and during this time the quartz substrate 3 held by the holding electrode 4 is heated by the heating device of the holding electrode 4. It is heated to 5350'C. After that, from the reaction gas introduction pipe 7, the reaction gas SiH4,02,
PH5 is introduced and the degree of vacuum in the film forming chamber 1 is 10 Torr.
After stabilizing at r, high frequency power is applied between the counter electrode 6 and the holding type single pole 4. Reactive gas molecules are excited by high frequency power between the two electrodes, and reactions between the gases tend to occur. As a result, the quartz substrate 30 held by the holding electrode 4 and heated
5IH4 and 0 containing p-1 decomposed by PHs gas on the surface
A 5102 film, that is, a PSG film with a film thickness of 4 is formed by the reaction with 2. PSG film 1 film thickness 4 kink P
The flow rate of PH3 is controlled so that the amount of PH3 becomes, for example, 4 weight percent, and the reaction time, that is, the application time of high frequency power is controlled so that the film thickness becomes, for example, 1 μm (FIG. 1a).

この時に石英基板3表面に形成されたPSG膜1膜圧4
形成時の石英基板3の温度が360°Cと低いために緻
密ではないが高密度の反応ガス5IH4r 02 + 
PHsを用いること、膜形成室1内の温度が350℃以
下と低いため内壁や対向電極6等から汚染されることも
ないため、不純物の含有量は十分に少なくなっている。
At this time, the PSG film 1 formed on the surface of the quartz substrate 3 has a film thickness of 4
Because the temperature of the quartz substrate 3 during formation is as low as 360°C, the reaction gas 5IH4r 02 + is not dense but has a high density.
Since PHs is used and the temperature inside the film forming chamber 1 is as low as 350° C. or less, there is no contamination from the inner wall, the counter electrode 6, etc., and the content of impurities is sufficiently small.

残留ガスが排気管9より排気され膜形成室1と予備排気
室2との真空度が等しくなると、これら二つの空間の隔
壁に設けられた扉13が開いて十M4体基板1oがr+
z置された半導体基板保持具11が予備排気室2から膜
形成室に搬送され、保持電極4の下方において、各半導
体基板10が石英基板3の各りに対向するように置かれ
る。
When the residual gas is exhausted from the exhaust pipe 9 and the degree of vacuum in the film forming chamber 1 and the pre-evacuation chamber 2 become equal, the door 13 provided on the partition between these two spaces opens and the 10M4 substrate 1o is exposed to r+
The semiconductor substrate holder 11 placed in the z-position is transported from the pre-evacuation chamber 2 to the film formation chamber, and each semiconductor substrate 10 is placed so as to face each of the quartz substrates 3 below the holding electrode 4 .

Arガス導入口8よI) Arガスが尋人され、磁石全
内蔵する保持電極4とスパック用型1?1j 50間に
高周波電力が印加される。この時に表面にPSG膜1膜
圧4成された石英基板3をターゲットとするスバソクリ
/グが行なわれ、PSG膜1膜圧4成するSi 、 O
、P原子が加速されたArイオンによりたたき出され、
ターゲットと対向して位1値する半導体基板10表面に
飛来し、再びこの半導体基板1Q表面にpsG膜15が
形成さiしる。
Ar gas is introduced through the Ar gas inlet 8, and high frequency power is applied between the holding electrode 4, which has a built-in magnet, and the spacing mold 1-1j 50. At this time, substrate drilling is performed targeting the quartz substrate 3 on which the PSG film 1 film thickness 4 has been formed, and Si, O, which has formed the PSG film 1 film thickness 4
, P atoms are ejected by accelerated Ar ions,
The particles fly onto the surface of the semiconductor substrate 10 which faces the target, and the psG film 15 is again formed on the surface of the semiconductor substrate 1Q.

所望の膜厚例えば0・5μmのPSG膜15が構成され
ると高周波電力とArガスがきらノし、残留ガスが排気
口9より排出された後扉13が開いて半導体基板10が
載置された半導体基板保持具11は膜形成室1から予備
室2Vc搬送され外に取出される。
When the PSG film 15 with a desired film thickness of 0.5 μm, for example, is formed, high frequency power and Ar gas are emitted, and after the residual gas is exhausted from the exhaust port 9, the door 13 is opened and the semiconductor substrate 10 is placed. The semiconductor substrate holder 11 is transported from the film forming chamber 1 to the preliminary chamber 2Vc and taken out.

以上に述べた方法でスパノクリ/グ法によりPSG膜1
6が形成される際に、クーゲットである石英基板3より
たたき出されたSi、O,P原子は十分高いエネルギー
を有しているために下部配線が形成された半導体基板1
00表面に形成されたPSG膜15は下部配線上のステ
ングヵバレッジが良く、外部から水分か不純物等が混入
するのを阻止するに十分な緻密さをもっている。また半
導体装置の特性を劣化させるアルカリイオンに対するゲ
ッタリング効果を決めるPSG膜1膜中5中濃度はCV
D法で石英基板3表面にPS(1,膜14を形成する際
のPH3流量を制御することにより精密に制御すミ℃と
ができる。さら[CVD法で石英基板3表面にPSG膜
1膜圧4成する際に高純変の反応ガスを用いておシ、寸
たCVD法やスパックリング法でPSG膜16を形成す
る際の温度が低いため外部から不純物の侵入することが
なく、PSG膜16は半導体装置の特性に悪影響を及ぼ
す不純物の含有量が少ないという大きな特長を有してい
る。このように高温の熱処理を施すことなく特性の良い
層間絶縁膜が形成できるために、高密度でかつ信頼性の
高いLSIの製造が容易になるO 寸だ本実施例ではCVD法で石英基板3表面にPSG膜
15を形成する際に、膜形成室1内壁にもPSG膜が形
成され、そのために後で半導体基板1Q表面にPSG膜
をスパッタリング法で形成する際に膜形成室1内壁から
金属イオンA:どの不純物が出るのを防げるため、半導
体基板10が形成されたPSG膜が汚染されることがな
いという長所もあわせもっている。
Using the method described above, the PSG film 1 is
6 is formed, the Si, O, and P atoms ejected from the quartz substrate 3, which is a cuget, have sufficiently high energy, so that the semiconductor substrate 1 on which the lower wiring is formed has a sufficiently high energy.
The PSG film 15 formed on the 00 surface has good coverage on the lower wiring and is dense enough to prevent moisture or impurities from entering from the outside. In addition, the concentration in one PSG film, which determines the gettering effect for alkali ions that degrade the characteristics of semiconductor devices, is CV.
By controlling the flow rate of PS (1, PH3) when forming the PS (1, film 14) on the surface of the quartz substrate 3 using the D method, it is possible to precisely control the temperature. When forming the PSG film 16 using a high-purity reaction gas, the temperature is low when forming the PSG film 16 using the CVD method or the spackling method, so impurities do not enter from the outside, and the PSG film 16 is The film 16 has a great feature of having a low content of impurities that adversely affect the characteristics of semiconductor devices.In this way, an interlayer insulating film with good characteristics can be formed without performing high-temperature heat treatment. In this embodiment, when forming the PSG film 15 on the surface of the quartz substrate 3 by the CVD method, the PSG film is also formed on the inner wall of the film forming chamber 1. Therefore, when a PSG film is later formed on the surface of the semiconductor substrate 1Q by a sputtering method, metal ions A and impurities can be prevented from coming out from the inner wall of the film forming chamber 1, so that the PSG film on which the semiconductor substrate 10 is formed is not contaminated. It also has the advantage of not causing any problems.

以上に述べた実施例ではCVD法で石英基板3表面K 
、P S G膜14を形成するのに高周波電力で反応ガ
スを励起するプラズマCVD法を用いているが、熱分解
反応を用いるCVD法あるいは紫外光で反応ガスを励起
する光CVD法を用いても良い。捷た薄膜形成装置は実
施例のようにCVD法とスパックリング法を同一の膜形
成室1内で行う必要はなく、CVD法でPSG膜14が
形成された石英基板3が隣接するチャンバーに搬送され
てそこで半導体基板10表面へスパックリング法でps
G膜16が形成されても良い。さらには、外部からの汚
染が十分考慮されておれば、cvn法で石英基板表面に
PSG膜を形成した後、他のスパッタリング装置にこの
石英基板3をターゲットとして用いて半導体基板11表
面にPSG膜15を形成してもよい。
In the embodiment described above, the surface K of the quartz substrate 3 is
In order to form the PSG film 14, a plasma CVD method in which a reactive gas is excited with high frequency power is used, but a CVD method using a thermal decomposition reaction or an optical CVD method in which a reactive gas is excited with ultraviolet light is used. Also good. The spun thin film forming apparatus does not need to perform the CVD method and the spackling method in the same film forming chamber 1 as in the embodiment, and the quartz substrate 3 on which the PSG film 14 has been formed by the CVD method is transported to an adjacent chamber. There, ps is applied to the surface of the semiconductor substrate 10 using a spackle method.
A G film 16 may also be formed. Furthermore, if sufficient consideration is given to contamination from the outside, it is possible to form a PSG film on the surface of a quartz substrate by the CVN method, and then use this quartz substrate 3 as a target in another sputtering device to form a PSG film on the surface of the semiconductor substrate 11. 15 may be formed.

以上は半導体装置の層間絶縁膜として用いるPSG膜を
形成する方法と装置について説明してきたが、ゲート電
極を形成するために高融点金属薄膜を形成する場合にも
本発明の製造方法は大きな効果を有する。MO等の高融
点金属は、従来ゲート電極として用いられている多結晶
Siに比べ、電気抵抗が2桁も小さいため高密度、高速
度のLSIのゲート電極材料として期待されている。し
かしながら薄膜形成をスパックリング法により形成する
場合に高純度のターゲットが得がたく、そのためアルカ
リイオンをはじめとする不純物含有量の少ない高融点金
属薄膜を形成するのが困難である。そしてこのことが高
融点金属をゲート電極として用いることの大きな障害と
なっている。そこで、本発明の薄膜の形成方法を用いる
と容易に不純物の含有量が少ない高融点金属な9膜を有
するターゲットが得られ、不純物含有量の少ない高融点
金属薄膜がスパックリング法で形成できるので高密度、
高速度かつ高信頼性のLSIを高歩留りで製造すること
ができる。
The above has described the method and apparatus for forming a PSG film used as an interlayer insulating film of a semiconductor device, but the manufacturing method of the present invention also has great effects when forming a high melting point metal thin film to form a gate electrode. have High-melting point metals such as MO have electrical resistance two orders of magnitude lower than polycrystalline Si, which is conventionally used as gate electrodes, and are therefore expected to be used as gate electrode materials for high-density, high-speed LSIs. However, when a thin film is formed by the spackling method, it is difficult to obtain a highly pure target, which makes it difficult to form a high melting point metal thin film with a low content of impurities such as alkali ions. This is a major obstacle to using high melting point metals as gate electrodes. Therefore, by using the thin film forming method of the present invention, a target having 9 films of high melting point metal with low impurity content can be easily obtained, and a high melting point metal thin film with low impurity content can be formed by the spackling method. high density,
A high-speed and highly reliable LSI can be manufactured with a high yield.

発明の効果 半導体装置に悪影響を及ぼす不純物の含有量が少なく、
かつ高温での熱処理を施さなくても十分特性の良い緻密
な薄膜を形成することができる。
Effects of the invention: The content of impurities that adversely affect semiconductor devices is small;
Moreover, a dense thin film with sufficiently good properties can be formed without heat treatment at high temperatures.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は本発明の薄膜の形成方法を説明するた
めの薄膜形成装置の概略断面図である。 3・・・・・・石英基板、4・・・・・・CVD法存び
スパックリング法で薄膜を形成する際の保持型イ”ルく
、5・・・・・・スパックリング法の電極、6・・・・
・・プラズマG V D法を行う場合の対向電極、10
叩・・半ij:、L体基板、14・・・・・・CVD法
で石英基板表面に形成した薄膜5.16・・・・・・ス
パックリング法で形成したハ11膜。 @1図 第2図
1 and 2 are schematic cross-sectional views of a thin film forming apparatus for explaining the thin film forming method of the present invention. 3...Quartz substrate, 4...Holding type electrode when forming a thin film by CVD method or spackling method, 5... Electrode for spackling method , 6...
...Counter electrode when performing plasma G V D method, 10
Punching...Half ij:, L-body substrate, 14...Thin film formed on the surface of a quartz substrate by CVD method5.16...C11 film formed by sputtering method. @Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 基板の表面に気相化学堆積法によシ薄膜を形成した後、
前記基板をターゲットとするスパッタリング法により半
導体基板に所定の厚さのV’1J膜を形成することを特
徴とする薄膜の形成方法。
After forming a thin film on the surface of the substrate by vapor phase chemical deposition,
A method for forming a thin film, comprising forming a V'1J film of a predetermined thickness on a semiconductor substrate by a sputtering method using the substrate as a target.
JP17940582A 1982-10-12 1982-10-12 Formation of thin film Pending JPS5968921A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17940582A JPS5968921A (en) 1982-10-12 1982-10-12 Formation of thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17940582A JPS5968921A (en) 1982-10-12 1982-10-12 Formation of thin film

Publications (1)

Publication Number Publication Date
JPS5968921A true JPS5968921A (en) 1984-04-19

Family

ID=16065288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17940582A Pending JPS5968921A (en) 1982-10-12 1982-10-12 Formation of thin film

Country Status (1)

Country Link
JP (1) JPS5968921A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7465966B2 (en) 2003-03-19 2008-12-16 Semiconductor Energy Laboratory Co., Ltd. Film formation method and manufacturing method of semiconductor device
JP2009135504A (en) * 2004-03-26 2009-06-18 Nissin Electric Co Ltd Method and apparatus for forming silicon dots

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5391084A (en) * 1977-01-20 1978-08-10 Gnii Pi Redkometa Method and apparatus for evaporating source matter to evaporation portion

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5391084A (en) * 1977-01-20 1978-08-10 Gnii Pi Redkometa Method and apparatus for evaporating source matter to evaporation portion

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7465966B2 (en) 2003-03-19 2008-12-16 Semiconductor Energy Laboratory Co., Ltd. Film formation method and manufacturing method of semiconductor device
JP2009135504A (en) * 2004-03-26 2009-06-18 Nissin Electric Co Ltd Method and apparatus for forming silicon dots

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