JPS5966996U

JPS5966996U - Digital recording and playback device

Info

Publication number: JPS5966996U
Application number: JP16184582U
Authority: JP
Inventors: 荒木　省二
Original assignee: 株式会社東芝
Priority date: 1982-10-26
Filing date: 1982-10-26
Publication date: 1984-05-07

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のデジタル記録再生装置の構成を示すブロ
ック図、第２図はこの考案に係るデジタル記録再生装置
の要部を示すブロック図である。１１．１２・・・増幅器、１３．１４・・・プリエンフ
ァシス回路、１５．１６・・・ＬＰＦ、　１７．　１８
・・・Ｓ／Ｈ回路、１９・・・混合回路、２０・・・Ａ
ＤＣ回路、２１・・・記録処理回路、２２・・・ビデオ
増幅器、２３・・・ＶＴＲ１２４・・・緩衝増幅器、２
５・・・データ分離　　−回路、２６・・・同期信号分
離回路、２７・・・再生シンクセパレータ、２８・・・
再生処理回路、２９・・・ＤＡＣ回路、３０・・・分離
回路、３１．３２・・・ＬＰＦ　。３３．３４・・・デエンファシス回路、３５．３６・・
・ミューティング回路、４１・・・ＰＣＭプロセッサ、
４２・・・アナログスイッチ、４３・・・緩衝増幅器、
４４・・・エンベロープ検出回路、４５・・・波形整形
回蕗、４６・・・ウィンドパルス発生回路、４７・・・
第１のカウンタ、４８・・・データ比較回路、４９・・
・第１の表示器、５０・・・第２のカウンタ、５１・・
・制御回路、５２・・・第１の発振器、５３・・・第２
の発振器、５４−・・第２の表示器、ｓｌ、　ｓ２．　
ｓＲ，ｓＰ、　Ｓｓ、、、スイッチ。FIG. 1 is a block diagram showing the configuration of a conventional digital recording and reproducing apparatus, and FIG. 2 is a block diagram showing the main parts of the digital recording and reproducing apparatus according to this invention. 11.12...Amplifier, 13.14...Pre-emphasis circuit, 15.16...LPF, 17. 18
...S/H circuit, 19...mixing circuit, 20...A
DC circuit, 21... Recording processing circuit, 22... Video amplifier, 23... VTR124... Buffer amplifier, 2
5...Data separation circuit, 26...Sync signal separation circuit, 27...Reproduction sync separator, 28...
Reproduction processing circuit, 29... DAC circuit, 30... Separation circuit, 31.32... LPF. 33.34... De-emphasis circuit, 35.36...
- Muting circuit, 41... PCM processor,
42... Analog switch, 43... Buffer amplifier,
44... Envelope detection circuit, 45... Waveform shaping circuit, 46... Wind pulse generation circuit, 47...
First counter, 48...Data comparison circuit, 49...
・First display, 50...Second counter, 51...
- Control circuit, 52... first oscillator, 53... second
oscillator, 54--second indicator, sl, s2.
sR, sP, Ss,, switch.

Claims

[Scope of utility model registration request]

In a digital recording and reproducing apparatus that interconnects a PCM processor and a VTR to record and reproduce analog signals, a television signal outputted by the PCM processor is predetermined in a data interval portion of a magnetic tape mounted on the VTR. a first means for muting and recording a predetermined track number intermittently at intervals of a desired number of times; a second means for arbitrarily setting a desired track number for reproduction; a third means for counting the number of muting times of the television signal recorded for each data interval from the reproduction output signal of the VTR in the reproduction state; and a track number set in the second means and the third means. and fourth means for detecting a state in which the counted values of the means coincide with each other.