JPS5966934U - Digital recording and playback device - Google Patents
Digital recording and playback deviceInfo
- Publication number
- JPS5966934U JPS5966934U JP16184482U JP16184482U JPS5966934U JP S5966934 U JPS5966934 U JP S5966934U JP 16184482 U JP16184482 U JP 16184482U JP 16184482 U JP16184482 U JP 16184482U JP S5966934 U JPS5966934 U JP S5966934U
- Authority
- JP
- Japan
- Prior art keywords
- vtr
- digital recording
- recording
- magnetic tape
- playback device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のデジタル記録再生装置の構成を示すブロ
ック図、第2図はこの考案に係るプレタル記録再生装置
の要部を示すブ吊ツク図である。
11.12・・・増幅器、13.14・・・プリエンフ
ァシス回路、15.16・・・LPF、 17. 18
・・・S/H回路、19・・・混合回路、20・・・A
DC回路、21・・・記録処理回路、22・・ゼデオ増
幅器、23・・・VTR,24・・・緩衝増幅器、25
・・・アナログシンクセパレータ、26・・・再生シン
クセパレータ、27・・・マスタクロック発生回路、2
8−・・再生処理回路、29・・・DAC回路、30・
・・分離回路、31゜32・・・LPF、 33. 3
4・・・デエンファシス回路、−35,36・・・ミュ
ーティング回路、41・・・PCMプロセッサ、42・
・・ミューティング回路、43・・・エンベローフ検出
回路、44−ψ・コンパレータ、。
窄
45・・・VTR制御回路、46・・・操作装置。FIG. 1 is a block diagram showing the configuration of a conventional digital recording and reproducing apparatus, and FIG. 2 is a block diagram showing the main parts of the pretal recording and reproducing apparatus according to this invention. 11.12...Amplifier, 13.14...Pre-emphasis circuit, 15.16...LPF, 17. 18
...S/H circuit, 19...mixing circuit, 20...A
DC circuit, 21... Recording processing circuit, 22... Zedeo amplifier, 23... VTR, 24... Buffer amplifier, 25
... Analog sync separator, 26... Reproduction sync separator, 27... Master clock generation circuit, 2
8-... Reproduction processing circuit, 29... DAC circuit, 30...
...Separation circuit, 31°32...LPF, 33. 3
4... De-emphasis circuit, -35, 36... Muting circuit, 41... PCM processor, 42...
... Muting circuit, 43 ... Envelope detection circuit, 44-ψ comparator. 45... VTR control circuit, 46... operating device.
Claims (1)
記録および再生をなすデジタル記録再生装置において、
記録状態で前記VTRに装着される磁気テープのビデオ
トラックにデータ部およびデータ間部を形成するそれぞ
れの場合に応じて選択的に垂直同期信号を磁気テープの
音声トラックに記録する第1の手段と、前記VTRの高
速再生状態で前記磁気テープの音声トラックの再生出力
から上記第1の手段により記録された垂直同期信号の有
無を検出する第2の手段とを具備してなることを特徴と
するデジタル記録再生装置。In a digital recording and reproducing device that interconnects a PCM processor and a VTR to record and reproduce analog signals,
a first means for selectively recording a vertical synchronization signal on an audio track of a magnetic tape according to each case forming a data portion and an inter-data portion on a video track of a magnetic tape loaded on the VTR in a recording state; and a second means for detecting the presence or absence of a vertical synchronization signal recorded by the first means from the reproduction output of the audio track of the magnetic tape in a high-speed reproduction state of the VTR. Digital recording and playback device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16184482U JPS5966934U (en) | 1982-10-26 | 1982-10-26 | Digital recording and playback device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16184482U JPS5966934U (en) | 1982-10-26 | 1982-10-26 | Digital recording and playback device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5966934U true JPS5966934U (en) | 1984-05-07 |
Family
ID=30355565
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16184482U Pending JPS5966934U (en) | 1982-10-26 | 1982-10-26 | Digital recording and playback device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5966934U (en) |
-
1982
- 1982-10-26 JP JP16184482U patent/JPS5966934U/en active Pending
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