JPS5965904A - Equalizing circuit of video signal - Google Patents

Abstract

PURPOSE:To convert easily to an IC, to obtain an optional frequency characteristic by a resistance and a capacitor which are provided on the outside, and to use only one pin for a pin of the IC for that purpose, by realizing a video equalizing circuit constituted of only a low capacity capacitor and a resistance transistor. CONSTITUTION:A case when a resistance 28 and a capacitor 32 are connected is considered. To connect the resistance 28 and the capacitor 32 to the emitter of a transistor 24 is to vary the gain and a frequency characteristic of a video equalizing circuit. Accordingly, the resistance 28 and the capacitor 32 are provided to the outside so as to be variable, and an amount of overshoot and undershoot, and width of overshoot and undershoot become variable by varying the resistance 28 and the capacitor 32, respectively. Also, as for a pin of an IC, only one pin is used, and constitution of a circuit which is converted to an IC very easily is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a waveform correction circuit for video@blind, and in particular to a video tape recorder that makes the outline of a reproduced image clear and provides a high-quality image. Regarding the equalization circuit.

[Prior art]

In a VTR, the following processing is performed to make the boundary between brightness and darkness of a reproduced image clear. That is, processing is performed to subtract the second-order differential component of the reproduced luminance signal from the reproduced luminance signal. Next, stiffness will be explained using a diagram. Figure 1 shows the block diagram.
Figure 2 shows the waveform. In FIG. 1, 1 is a luminance signal input terminal, 2G non-primary differential circuit, 6 is a secondary differential circuit 4 is a subtracter, and 5 is an output terminal. In Fig. 2, 6 is the signal applied to input terminal 1, 7 is the output of primary circuit 2,
8 is the output of the second-order differential circuit $3, and 9 is the output of the output terminal 5. As shown in Fig. 2, the input signal 6 is not corrected like the output signal 9, and autoshoots and undershoots are added to the many rising and falling parts of the signal waveform (that is, the parts where the brightness changes are large). Ru. That is, the boundaries between areas with different brightness become clear on the screen.

Next, an example of the conventional circuit is shown in Fig. 6.◇In Fig. 6, 10 is a luminance signal input terminal, 11 is a bias voltage
, i2 is a transistor, 16 is a power supply terminal, 14, 1
5 is a coil, 16 is an output terminal, 17, 1819, 2
0 is a resistor and 21.22 is a capacitor.

A luminance signal applied to input terminal 10 is extracted from the collector and emitter of transistor 12. The collector output signal is first differentiated by the coil 14 and then by the resistor 1
7 and the coil 15. As a result, the collector output signal will be second-order differentiated. Further, the emitter output signal is first-order integrated by the coil 15 and added to the second-order differentiated collector output signal. However, since the second-order differential signal is a collector output, its phase is inverted, and the second-order differential signal is subtracted from the first-order integral signal. Above, we have explained the operating principle of Fig. 6 as an example, but in the configuration of Fig. 6,
Since two coils are used, it is difficult to form an IC, and
In this case, there was a problem in that six pins of the IC were used because the coil was externally attached.

[Purpose of the invention]

An object of the present invention is to provide a video equalizer circuit that can be easily integrated into an IC in a video signal processing circuit and can be manufactured at low cost.

[Summary of the invention]

In the present invention, in order to make the video equalizer circuit easily integrated into an IC, the circuit is constructed using only low-capacity capacitor resistors and transistors that can be built into an IC, without using a coil. Take the circuit configuration. That is, a transistor having a base electrode for inputting a signal, a first capacitor having a first terminal connected to the collector electrode of the transistor, a first capacitor having the first terminal connected to the emitter electrode of the transistor, and a second terminal having a first terminal connected to the emitter electrode of the transistor. a first resistor whose first terminal is connected to the second terminal of the capacitor; and a second resistor whose first terminal is connected to the emitter electrode of the transistor.
a second capacitor (resistance) whose first terminal is connected to the second terminal of the second resistor (capacitor) and whose second terminal is grounded; a sixth resistor whose first terminal is connected to the collector electrode h1 and whose second terminal is connected to a power source; the first terminal is connected to the emitter electrode of the transistor and the second terminal is grounded; An output is taken out from a common connection point between the parallel undefined current source, the first resistor, and the first capacitor.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. , @
In Figure 4, 23 is a luminance signal input terminal 24, 25 is a transistor, 26, 27, 28, 29 are resistors, 60 is a power supply terminal, 31.32 is a capacitor, 666
Reference numeral 4 represents a constant current terminal, 65 represents an output terminal, and 66 represents a bias power source. First, to simplify the explanation, consider a state in which the resistor 28 and capacitor 62 are not connected. resistance 26,
27, the values of capacitor 31 are RLt and Rr, respectively.
Suppose that when the voltage e is applied to the input terminal 23, a pressure e2 is generated at the collector of the transistor 24. In the configuration shown in FIG. 4, the transistors 24 and 25 are considered to form a differential amplifier circuit, so the following equation holds true.

As can be seen from equation (2), e2 is a first-order differential of el. The emitters of the transistors 24 and 25 each have a voltage ele2. e2 is generated, eI82 is divided into linear groups by the resistor 27 and capacitor 51, e2 is first differentiated, and both are added. Assuming that the voltage e generated at the output terminal 35 is 1, it can be expressed as follows.

(6) From equation (b), a difference between the first integral and second derivative of the input occurs in the output, and the desired characteristics can be obtained.

becomes.

Here, the capacitor 31 is formed of a MOS capacitor. Figure 9 shows a configuration diagram of the M'OS capacitor. In FIG. 9, 74 indicates an insulating layer 75 as an upper electrode, 76
77 is an epitaxial layer, 78 is a resistive layer, and 7 is a lower electrode.
9 is a P-type substrate. As shown in FIG. 9, a capacitance equivalent to the original capacitance of the capacitor is generated between the #MOSMOS capacitor layer 78 and the D-type substrate 7Q, and this inter-substrate capacitance has an adverse effect.

In FIG. 4, the upper electrode 75 of the capacitor 31 is the emitter of the transistor 25, and the lower electrode 76 is the emitter of the resistor 25.
7, the above-mentioned inter-board capacitance is attached to the output terminal 35 and significantly deteriorates the frequency characteristics. Therefore, such connections must be avoided. Conversely, the upper electrode 75' of the capacitor 31 (!l- to the resistor 27,
If the lower electrode is connected to the emitter of the transistor 25, the inter-substrate capacitance will be attached to the emitter of the transistor 25, which has a low impedance, and will hardly be a problem. That's all υ, the upper electrode 75 of the capacitor 61
must be connected to the resistor 27 and the lower electrode to the emitter of the transistor 35.

Consider the case where a resistor 28 and a condenser 52 are connected. Connecting the resistor 28 and capacitor 32 to the emitter of the transistor 24 changes the gain and frequency characteristics of the video equalizer circuit. Therefore, the sum resistor 28 and the condenser 62 are externally connected to vary the amount of overshoot and undershoot by changing the resistor 28.
By changing the width of the geobar shoot and undershoot, the width of the geobar shoot and undershoot can be varied. Moreover, only one IC pin is used, making the circuit configuration very easy to use as an IC. However, 33 and 34 in FIG. 4 are not limited to constant current sources, and may be resistors.

Further, another embodiment is shown in FIG. In FIG. 5, 57 is an input terminal, 38 is a power supply terminal, 39 is an output terminal,
40 is a bias power supply, 41 is a transistor, 42,
43 and d4.45 are resistors, 46 and 47 are capacitors, and 48 is a constant current source. The configuration shown in FIG. 5 connects the output of transistor 24 to transistor 2 as shown in FIG.
The output of the transistor 41 is taken out directly through the capacitor 46 without passing through the emitter follower 5.・Transistor 41 in box 5 diagram
The signal input to the input terminal 67 is applied to the base of the . Since the transistor 41 is fed back from the collector to the emitter through the capacitor 46 and the resistor 46, the collector output of the transistor 41 is first differentiated by the capacitor 46 and the resistor 46, and then fed back to the emitter. Therefore, a signal obtained by first-order differentiation of the base input appears at the collector of the transistor 41, and this signal is first-order differentiated by the capacitor 46 and the resistor 46 and output. The second-order differential component of the signal is now 6, and the phase is inverted because it is the collector output. At the same time, transistor 41
The emitter output is first-order integrated by a resistor 45 and a capacitor 46, and added to the above-mentioned phase-inverted second-order differential component to obtain the desired output waveform. As for the capacitor 46, the upper electrode is connected to the resistor 46 and the lower electrode is connected to the collector of the transistor as in the case of FIG. However, in this case, an inter-substrate capacitance is attached to the collector of the transistor, deteriorating the frequency characteristics of the second-order differential component, but this can be corrected by adjusting the gain.

The resistor 44 and capacitor 47 can have arbitrary characteristics by being external to the IC as in the case of FIG. FIG. 5 48 is not limited to constant current sources;
It can also be resistance.

Further, as another embodiment, an example is shown in FIG. 6, 49 is an input terminal, 50 is a power supply terminal, 51 is an output terminal, 521, 53
．． 55 is a transistor, 56 is a variable resistor, 57, 58, 59, 60, 61, and 62 are resistors, 65.64 is a capacitor, 65 and 66 are constant current sources, and 67 and 686 are bias currents. The circuit operation is the same as in FIGS. 4 and 5, and the transistor 55 is connected from the collector to the transistors 52, 5! differential amplifier load by l, transistor 54, capacitor 66,
Since it is fed back to the emitter through the resistor 60, a phase-inverted second-order differential component of the input signal appears at the output terminal 51.
Further, from the emitter of the transistor 55, a resistor 60,
The first-order integrated signal by the capacitor 63 appears at the output terminal, and the two are added together.

The capacitor 65 is connected by connecting the upper electrode to the resistor 60 and the lower electrode 111& to the emitter of the transistor 54 in the same manner as in FIG.

By attaching the resistor 61 and capacitor 64 externally to the IC as in FIGS. 4 and 5, arbitrary characteristics can be obtained. However, 65 and 66 in FIG. 6 are not limited to constant current sources, and may be resistors. Furthermore, the configuration of FIG. 6 has features that the configurations of FIGS. 4 and 5 do not have. That is, by adjusting the variable resistor 56, the amount of overshoot and undershoot in the output waveform can be completely controlled. FIG. 7 shows the frequency characteristics of the configuration shown in FIG. In FIG. 7, 69 and 70° 71 indicate the frequency characteristics when the second-order differential component is maximum, medium, and minimum, respectively. The horizontal axis of FIG. 7 is the frequency, and the vertical axis is the output response.

When the variable resistor 56 is adjusted to minimize the pace potential of the transistor 52, the collector current of the transistor 56 is at its maximum and becomes equal to the collector current of the transistor 55. That is, the second-order differential component is at its maximum, and the overshoot and undershoot of the waveform are at its maximum. The frequency characteristics at this time are shown in @7 Figure 69. Next, when the variable resistor 56 is set to 1lik and the potential of the base of the transistor 52 is raised, the collector current of the transistor 53 decreases, and therefore, the overshoot and undershoot leaves of the waveform also decrease. Eventually, there will be no overshoot or undershoot at all. In other words, the second derivative and the first autumnal equinox are complementary, and Hura,
This results in positive and negative frequency characteristics. The frequency characteristics at this time are shown in FIG. 70. And further transistor 5
As the base potential of the transistor 2 increases, the collector current of the transistor 56 decreases more and more, the first-order integral becomes dominant, and the rising and falling edges of the waveform become softer.

Eventually, the transistor 53 is turned off, the second-order differential component becomes zero, and only the first-order integral component appears at the output terminal 51. The frequency characteristics at this time are shown in FIG. 771. As described above, the configuration shown in FIG. 7 allows the amount of overshoot and undershoot of the output waveform to be arbitrarily changed by adjusting the variable resistor 56.
By outputting the image to the outside, you can easily obtain the desired image quality). Therefore, the present invention applies not only to VTRs but also to
It is also suitable for the image quality of TV etc.

Next, in the configuration shown in FIG. 4, an example of specific circuit constants is shown in FIG. In FIG. 8, 72 is a resistor, 73 is an I
At pin C, resistors 26, 27, 28.

The resistance values of 72 are 10.5 Ω, 15 Ω, and 10
niΩ.

1 and the capacitance of capacitors 31 and 32 are each 10
ppl l 15PF + The current of the constant current sources 53 and 34 is each 0.1 mA. 8. 33 and 34 in FIG. 8 are not limited to constant current sources, but may be resistors. However, everything except resistor 28 and capacitor 62 is inside the IC, and resistor 26,
27 is an ion implantation resistor. The connector 51 is connected in exactly the same way as in FIG. The use of an ion implant resistor for resistor 27 in FIG. 8 is significant.

Conventionally used diffused resistors have a small sheet resistance, so when making a high resistance, they are very long, and therefore the capacitance attached to the resistor is large, and since the resistors are made by diffusion, the absolute value accuracy is poor.

In this respect, the ion implanted resistor has a large area resistance and can be made short, so the capacitance attached to the resistor is small and the absolute value is good, so it is more advantageous than the diffused resistor.

In cases where the characteristics are determined by external resistors and capacitors, it is necessary to use an ionized resistor. This is because the absolute value of the ion implantation resistor is good, so the external resistor can easily achieve high accuracy relative to the resistor 1.

In the example of FIG. 8, the resistance 72 is sufficiently small compared to the resistance 2 days, so the gain is not affected by variations in the resistance 72. However, when the gain is determined by the resistance 26 and the resistance 72, the resistance 72 is also It should be an ion implantation resistor.

Although some embodiments of the present invention have been described above, the present invention is not limited to the embodiments described here.

〔Effect of the invention〕

According to the present invention, it is possible to realize a video equalizer circuit consisting only of a low capacitance capacitor and a resistor transistor, so it is easy to convert it into an IC, and an arbitrary chest frequency characteristic can be obtained by using an external resistor and capacitor. The number of pins required is only one pin, which has the effect of making it possible to significantly reduce costs.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a video equalizer circuit.
Figure 2 shows the waveforms of each part of Figure 1; Figure 3 shows an example of a conventional video equalizer circuit; Figures 4 and 5;
Fig. 6 is a diagram showing an embodiment of the video equalizer circuit using the present invention, Fig. 7 is a diagram showing the frequency characteristics of the circuit shown in Fig. 6, and Fig. 8 is a diagram showing an embodiment of the video equalizer circuit using the present invention. A diagram showing an example of the video equalizer circuit used, FIG.
FIG. 3 is a diagram showing the structure of an S capacitor. 2...1st order integral circuit, 6...2nd order differential circuit, 24
, 25...Transistor, 26, 27, 28, 29...Resistor, 31, 3
2... Capacitor, 55, 54... Constant current source. Figure 1, Volume 4; Figure 11-δ

Claims (1)

[Claims] 1. A transistor having a Vane electrode for inputting a signal, a first capacitor whose first terminal is connected to the collector electrode of the transistor, and an emitter of the transistors;
a first resistor having a first terminal connected to the emitter electrode of the transistor and a second terminal connected to the second terminal of the capacitor; and a second resistor having a first terminal connected to the emitter electrode of the transistor. A second capacitor whose first terminal is connected to the second terminal of the resistor (capacitance) and the second resistor (capacitance t) and whose second terminal is grounded! (resistance), a fifth resistor whose terminal is connected to the collector compartment 4- of the transistor, and whose second terminal is connected to the terminal; a constant current source having terminals connected to each other and a second terminal being grounded, the first resistor and the first resistor;
A video signal equalization circuit characterized in that an output is taken out from a common connection point of three capacitors. 2. The transistor, the first resistor, the first
The third resistor and the constant current source are made inside the IC, the second resistor and the second capacitor are made outside the IC, and the second resistor and the second capacitor are made outside the IC. 2. The video signal equalization circuit according to claim 1, wherein the video signal equalization circuit is capable of varying its magnitude. 6. The video signal equalization circuit according to claim 2, wherein the first resistor and the third resistor are formed of ion-implanted resistors. 4. The first capacitor is formed of a MOS capacitor, and the upper electrode of the first capacitor is formed of the second capacitor.
3. The video signal equalization circuit according to claim 2, wherein the lower electrode of the first capacitor is the first terminal.