JPS5965262A - Apparatus for measuring channel potential - Google Patents

Apparatus for measuring channel potential

Info

Publication number
JPS5965262A
JPS5965262A JP17482182A JP17482182A JPS5965262A JP S5965262 A JPS5965262 A JP S5965262A JP 17482182 A JP17482182 A JP 17482182A JP 17482182 A JP17482182 A JP 17482182A JP S5965262 A JPS5965262 A JP S5965262A
Authority
JP
Japan
Prior art keywords
potential
channel
source
drain
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17482182A
Other languages
Japanese (ja)
Inventor
Achio Shiyudou
首藤 阿千雄
Hiroshige Goto
浩成 後藤
Tetsuo Yamada
哲生 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP17482182A priority Critical patent/JPS5965262A/en
Publication of JPS5965262A publication Critical patent/JPS5965262A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE:To enable the measurement of source potential, by a method wherein a DC voltage form is connected between a source electrode and a reference potential supply source and it is utilized that the potential of a channel becomes equal to that of a source when voltage equal to or less than channel potential and voltage equal to or more than said potential are applied in this order to a drain electrode. CONSTITUTION:Because channel potential phiCH is lower than source and drain potentials phiS, phiD at time t1 as shown by (a), charge is not moved. At time t2, because drain applied voltage VD comes to OV, charge is supplied from a drain region 14 as shown by (b) and the potentials phiS, phiD are equal and come to a value lower than the channel potential phiCH. At time t3, when the drain applied voltage VD comes to high positive voltage, phiD becomes high while charge is moved to the drain region 14 from a low source region 13 and phiS is also raised but, when phiS becomes equal to phiCH, the charge movement is stopped by phiCH as barrier to form potential distribution as shown by (c) and phiCH to gate applied voltage VG is displayed by a DC voltmeter 21 connected to the source electrode 13. As the result, the channel potential phiD can be known by the DC voltmeter 21.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、例えば埋め込みチャネル形MOSトランジ
スタのチャネル電位を測定するだめのチャネル電位測定
装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a channel potential measuring device for measuring the channel potential of, for example, a buried channel type MOS transistor.

〔発明の技術的背、景〕[Technical background of the invention]

従来、埋め込みチャネル形MOSトランジスタのチャネ
ル電位を測定する場合は、第1図に示すようなチャネル
電位測定装置を使用している。
Conventionally, when measuring the channel potential of a buried channel type MOS transistor, a channel potential measuring device as shown in FIG. 1 has been used.

図において、1ノは被測定用のMOS )ランジスタで
、p形の半導体基板12上に形成されたn+形のソース
、ドレイン領域13.14と、ソース、ドレイン領域1
3.14間に形成されたn形の埋め込みチャネル15と
、上記基板12上に被媛形成された絶縁膜16と、この
絶縁膜16上のソース領域13.ドレイン領域14間に
形成されたダート電極17とによって構成されている。
In the figure, 1 is a MOS transistor to be measured, which includes n+ type source and drain regions 13 and 14 formed on a p type semiconductor substrate 12, and source and drain regions 13 and 14 formed on a p type semiconductor substrate 12.
3. An n-type buried channel 15 formed between . The dirt electrode 17 is formed between the drain regions 14.

18は被測定用MO8)ランラスタ1ノのソース領域1
3に所定の電圧を印加する可変直流電源、19はソース
領域13からドレイン領域14に電荷が移動することに
よって生ずるチャネル電流を検出するだめの直流電流計
、20はドレイン領域14に高い正電圧を印加するだめ
の直流電源である。
18 is the source region 1 of the MO8) run raster 1 for measurement.
3 is a variable DC power supply that applies a predetermined voltage; 19 is a DC ammeter for detecting the channel current generated by the movement of charge from the source region 13 to the drain region 14; 20 is a DC ammeter that applies a high positive voltage to the drain region 14; It is a DC power source that cannot be applied.

上記のような構成において、チャネル電位を測定する場
合は まず可変直流電源18の出力11I圧vsを高電
圧にした後、直流電流計19を見ながら一五圧vsを徐
々に低下させて行き、直流電流計19に電流が流れ始め
る時の可変直流電源18の電圧v8の値を読み取ってチ
ャネル電位とする。なお、第1図においてはr−ト印加
゛屯圧がOvの時のチャネル電位を測定する場合につい
て示している。
In the above configuration, when measuring the channel potential, first set the output 11I voltage vs of the variable DC power supply 18 to a high voltage, and then gradually lower the 15 voltage vs while watching the DC ammeter 19. The value of the voltage v8 of the variable DC power supply 18 when the current starts to flow through the DC ammeter 19 is read and taken as the channel potential. Note that FIG. 1 shows the case where the channel potential is measured when the applied pressure to the r-t is Ov.

第2図(a)〜(c)は、上記第1図に示したMOSト
ランジスタのチャネル電位を測定する場合の電位図であ
る。図において、φ8はソース電位、φCHはチャネル
電位、φ0はドレイン電位を示す。ソース印加電圧v8
がチャネル電位φCHよりも高い場合は(a)図に示す
ような電位分布となシ、チャネル電位φ。が障壁となる
ためソース領域からドレイン領域への電荷の移動は起ら
ず、チャネル電流は流れない。ソース印加電圧v8を徐
々に低下させて行き、ソース電位φ8がチャネル電位φ
CHよシ低くなると(c)図に示すような電位分布とな
シ、電荷はソース領域からドレイン領域に移動し、チャ
ネル電流ICHが発生する。従ってチャネル電流工CH
が流れ始める時のしきい値のソース電位φ8を持ってチ
ャネル電位とすることができる。すなわち、この時のチ
ャネル電位φcHはソース電位φ8と等しいので、ソー
ス電位φ6を測定することによシチャネル電位φ。、を
察知できる。(b)図にこの状態の電位分布を示す。
FIGS. 2(a) to 2(c) are potential diagrams when measuring the channel potential of the MOS transistor shown in FIG. 1 above. In the figure, φ8 indicates a source potential, φCH a channel potential, and φ0 a drain potential. Source applied voltage v8
If is higher than the channel potential φCH, the potential distribution as shown in the figure (a) will occur, and the channel potential φ. acts as a barrier, so charge does not move from the source region to the drain region, and no channel current flows. The source applied voltage v8 is gradually lowered, and the source potential φ8 becomes the channel potential φ
When CH becomes lower, the potential distribution becomes as shown in Figure (c), the charge moves from the source region to the drain region, and a channel current ICH is generated. Therefore, channel current engineering CH
The channel potential can be set to the source potential φ8, which is the threshold value when the current begins to flow. That is, since the channel potential φcH at this time is equal to the source potential φ8, the channel potential φcH is determined by measuring the source potential φ6. , can be detected. Figure (b) shows the potential distribution in this state.

〔背景技術の問題点〕[Problems with background technology]

しかし、上記のような構成では、微/JSなチャネル電
流の検出が必要であ)、ソース印加電圧■8の微妙な調
節も必要である。従って、一点測定が出来ず、測定時間
が長くなるとともに測定誤差も犬きくなシ易い欠点があ
る。
However, in the above configuration, it is necessary to detect a minute channel current), and delicate adjustment of the source applied voltage (8) is also necessary. Therefore, single-point measurement is not possible, the measurement time becomes long, and measurement errors tend to be large.

〔発明の目的〕[Purpose of the invention]

この発明は上記のような事情を鑑みてなされたもので、
その目自勺とするところは、チャネル電位の測定が短時
間に容易に行なえ、かつ測定誤差の小さいすぐれたチャ
ネル電位測定装置を提供することである。
This invention was made in view of the above circumstances,
The objective is to provide an excellent channel potential measuring device that can easily measure channel potential in a short time and with small measurement errors.

〔発明の概要〕[Summary of the invention]

すなわち、この発明においては、ソース電極と基準電位
供給源との間に直流7に圧計を接続し、ドレイン電極に
まずチャネル電位よシ低い電圧を印加した後、チャネル
電位よシ高い電位を供給し、この時のチャネル電位とソ
ース電位とが等しくなることを利用して、ソース電位を
上記■14圧計で測定することにょ9チャネル電位を察
知するように構成したものである。
That is, in this invention, a pressure gauge is connected to the DC 7 between the source electrode and the reference potential supply source, and a voltage lower than the channel potential is first applied to the drain electrode, and then a potential higher than the channel potential is applied. By taking advantage of the fact that the channel potential and source potential at this time are equal, the nine channel potential is detected by measuring the source potential with the 14-pressure gauge described above.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例について図面を参照して説明
する。
An embodiment of the present invention will be described below with reference to the drawings.

紀3図はその構成を示すもので、被測定用素子(MOS
 )ランジスタ)のダート印加電圧がOvの時のチャネ
ル電位を測定する場合を示している。図において、1ノ
は被測定用のMOS )ランジヌクで、このトランジス
タ11のンース領域13と基準電位供給源(接地点)と
の間に電圧測定手段として直流電圧計21を接続する。
Figure 3 shows its configuration, including the device under test (MOS).
) shows the case where the channel potential is measured when the dart applied voltage of transistor) is Ov. In the figure, reference numeral 1 denotes a MOS transistor to be measured. A DC voltmeter 21 is connected between the ground region 13 of the transistor 11 and a reference potential supply source (ground point) as a voltage measuring means.

また、ドレイン領域14にはスイッチSWの切換え操作
によって接地電位(第1の電位)あるいは直流電源22
の電位(第2の電位)を選択的に供給するとともに、ダ
ート電極17を接地するようにして成る。
In addition, the drain region 14 is set to a ground potential (first potential) or a DC power source 22 by switching the switch SW.
(second potential) is selectively supplied, and the dirt electrode 17 is grounded.

上記のような構成において、第4図および第5図(a)
 、 (b)を参照して動作を説明する。
In the above configuration, FIGS. 4 and 5(a)
, (b), the operation will be explained.

第5図(=)は第4図におけるタイミングt1の電位図
、第5図(b)はタイミングt2の電位図で、スイッチ
SWの可動接点をターミナルI側に接続するとドレイン
印加電圧はO■となシ、この時の電位分布は第5図(a
)に示すようにドレイン電位φ。とソース電位φ8とが
等しくなる。次に、スイッチSWの可動接点をターミナ
ル■側に接続すると、ドレイン印加電圧(直流電源22
の電位)が高い正電圧であるのでドレイン電位φ0が高
くなる。この時、ソース領域130電荷はドレイン領域
14に引かれて移動し、ソース電位φ8も上昇するが、
ソース電位φ8がチャネル7石、位φ。□に等しくなる
と、チャネル電位φcHが瞳!1、ことなシミ荷の移動
がなくなって第5図(b)に示すような電位分布となる
。従って、この状kE2ではソース電位φ6はチャネル
電位φCHと等しい値に固定されるので、ソース電位φ
Figure 5 (=) is the potential diagram at timing t1 in Figure 4, and Figure 5 (b) is the potential diagram at timing t2. When the movable contact of switch SW is connected to the terminal I side, the drain applied voltage becomes O■. The potential distribution at this time is shown in Figure 5 (a
) as shown in the drain potential φ. and the source potential φ8 become equal. Next, when the movable contact of the switch SW is connected to the terminal ■ side, the drain applied voltage (DC power supply 22
Since the drain potential φ0 is a high positive voltage, the drain potential φ0 becomes high. At this time, the charge in the source region 130 is attracted to the drain region 14 and moves, and the source potential φ8 also rises.
Source potential φ8 is at channel 7, φ. When it becomes equal to □, the channel potential φcH is the pupil! 1. There is no movement of different stains, resulting in a potential distribution as shown in FIG. 5(b). Therefore, in this state kE2, the source potential φ6 is fixed to a value equal to the channel potential φCH, so the source potential φ
.

を上り己[α流it圧計21で測定することによりチャ
ネル電位を紐知できる。
The channel potential can be determined by measuring the upstream [α current] with the pressure gauge 21.

ところで、ソース電位φ8の測定に直流電圧計を用いる
と、この直流電圧計の入力インピーダンスに応じたリー
ク電流が生じ、ソース電位φ8が若干低下するが、この
値を予め測定しておきソース電位φ8の測定値を補正す
れば良い。
By the way, when a DC voltmeter is used to measure the source potential φ8, a leakage current is generated depending on the input impedance of the DC voltmeter, and the source potential φ8 slightly decreases, but this value is measured in advance and the source potential φ8 is measured. Just correct the value.

このような+1トソ成によれば、従来のようにチャネル
電流を検出しながらドレイン印加電圧を調節する必要は
なく、スイッチの切換え操作のみでチャネル電位φ。8
を直流電圧計21に表示できるので、チャネル電位φ。
According to such a +1 toso configuration, there is no need to adjust the voltage applied to the drain while detecting the channel current as in the conventional case, and the channel potential φ can be adjusted by simply switching the switch. 8
can be displayed on the DC voltmeter 21, so the channel potential φ.

□の測定が容易になシ、測定時間も短縮できる。まだ、
チャネル電位φC□が電圧計21に表示できるので読み
取シ誤差も少ない。
□ can be easily measured and the measurement time can be shortened. still,
Since the channel potential φC□ can be displayed on the voltmeter 21, there is little reading error.

第6図は、埋め込みチャネル形MO8)ランジスタのダ
ート印加電圧に対するチャネル電位を測定する回路を示
すもので、第7図に各印加電圧のタイミングチャートを
示し、第8図(a)〜(C)に各状態の電位分布を示す
2.この回路は、被測定用MO8)ランジスタ11のド
レイン領域14に、例えば第7図に示すQVと15Vと
の間を変動するノfルス状の電圧VDを供給するドレイ
ン電位供給回路23を設けるとともに、ダート電極17
に階段状にレベルの変化する電圧■。
Fig. 6 shows a circuit for measuring the channel potential of a buried channel type MO8) transistor with respect to a dart applied voltage. Fig. 7 shows a timing chart of each applied voltage, and Figs. 8 (a) to (C) 2 shows the potential distribution of each state. This circuit is provided with a drain potential supply circuit 23 for supplying a voltage VD in the form of a voltage fluctuating between QV and 15V as shown in FIG. , dart electrode 17
■Voltage that changes level stepwise.

を供給するr−)電位供給回路24を設けたものである
An r-) potential supply circuit 24 is provided.

第7図に示すtllt2+t3のタイミングに対応する
第8図(a)’ ; (b) 、 (e)の電位図を参
照して動作を説明する。
The operation will be described with reference to the potential diagrams in FIGS. 8(a)'; (b) and (e) corresponding to the timing of tllt2+t3 shown in FIG. 7.

まず、タイミングt1では第8図(a)に示すように、
チャネル電位φC1がソース、ドレイン電位φ8.φo
Jニジも低いため電荷の移動はない。
First, at timing t1, as shown in FIG. 8(a),
Channel potential φC1 is source, drain potential φ8. φo
Since the J density is also low, there is no charge movement.

次に、タイミングt2ではドレイン印加電圧VDが0■
となるため、第8図(b)に示すようにドレ・fン領域
14から電荷が供給され、ソース。
Next, at timing t2, the drain applied voltage VD is 0■
Therefore, as shown in FIG. 8(b), charges are supplied from the drain/f drain region 14 and the source.

ドレイン電位φ8.φ0が等しくかつチャネル電位φ9
..よシも低い値となる。次に、タイミングt3になっ
てドレイン印加電圧VDが高い正電圧になると、ドレイ
ン電位φ。が高くなり電荷は電位の低いソース領域13
から電位の高いドレイン領域14に将動し、ソース電位
φ8も上昇するが、ソース電位φ8がチャネル電位φc
Hと等しくなると、このチャネル電位φCHが障壁とな
って電荷の移動が停止し、第8図(c)に示すような電
位分布と彦る。従って、チャネル電位φCHとソース電
位φ8とはほぼ同電位となシ、ダート印加電圧V。(6
V)に対するチャネル電位φCHがソース電極13に接
続した前記直流電圧計21に表示される。ここで、f−
)印加電圧■。は前述したように階段状に電圧が変化す
るので各ダート印加電圧レベル毎に上述した動作を繰夛
返し、ダート印加電圧VGに対するチャネル電位φCH
が得らる。
Drain potential φ8. φ0 are equal and channel potential φ9
.. .. Yoshi also has a low value. Next, at timing t3, when the drain applied voltage VD becomes a high positive voltage, the drain potential φ. becomes high and the charge is in the source region 13 with a low potential.
The source potential φ8 moves from the source to the drain region 14 with a high potential, and the source potential φ8 also rises, but the source potential φ8 is lower than the channel potential φc.
When the channel potential φCH becomes equal to H, the channel potential φCH acts as a barrier and the movement of charges is stopped, resulting in a potential distribution as shown in FIG. 8(c). Therefore, the channel potential φCH and the source potential φ8 are approximately the same potential, which is the dart applied voltage V. (6
The channel potential φCH with respect to V) is displayed on the DC voltmeter 21 connected to the source electrode 13. Here, f-
) Applied voltage■. As mentioned above, the voltage changes stepwise, so the above operation is repeated for each dart applied voltage level, and the channel potential φCH with respect to the dart applied voltage VG is determined.
is obtained.

第9図に上記第6図のチャネル電位測定装置によって求
めたダート印加電圧V。に対するチャネル電位φ、Hの
一例を示す。
FIG. 9 shows the dart applied voltage V determined by the channel potential measuring device shown in FIG. 6 above. An example of the channel potential φ and H for each channel is shown below.

第10図は、この発明の他の実施例を示すもので、CC
D転送レジスタの入力ダートのダート電圧がOvにおけ
るチャネル電位を測定する場合について示している。図
において、25はp形の半心体基板、26はn形の不純
物領域、271.27□ 、273はn+形の不純物領
域、28 Ire p−形の不純物領域、29は転送電
極、30はシリコン酸化膜、31は出力回路、IGは入
力p−ト、OGは出力ダート、ISは入力ソース、R8
はリセットダート、RDはリセントドレインである。リ
セットドレイン端子RDに接続されたスイッチSWの可
動接点をターミナルI側に接続すると、リセットドレイ
ン領域271に接地電位Ovが供給され、スイッチSW
のrTJ’動接点をターミナル■側に接続すると、リセ
ットドレイン領域27菫に直流電源22から高い正電圧
(例えば12v)が供給される。
FIG. 10 shows another embodiment of the invention, in which CC
A case is shown in which the dart voltage of the input dart of the D transfer register measures the channel potential at Ov. In the figure, 25 is a p-type half-core substrate, 26 is an n-type impurity region, 271.27□, 273 is an n+-type impurity region, 28 is a p--type impurity region, 29 is a transfer electrode, and 30 is a Silicon oxide film, 31 is the output circuit, IG is the input p-to, OG is the output dirt, IS is the input source, R8
is a reset dirt, and RD is a recent drain. When the movable contact of the switch SW connected to the reset drain terminal RD is connected to the terminal I side, the ground potential Ov is supplied to the reset drain region 271, and the switch SW
When the rTJ' dynamic contact is connected to the terminal ■ side, a high positive voltage (for example, 12 V) is supplied from the DC power supply 22 to the reset drain region 27.

入カソース昂1子Isと接地点間には高入力インピーダ
ンスな電圧測定手段である直流電圧計21を接続し、入
力ダート端子IGを接地する。
A DC voltmeter 21, which is a high input impedance voltage measuring means, is connected between the input source terminal Is and the ground point, and the input terminal IG is grounded.

その他のケゝ−ト重4:F (!7セツトダート電極、
出力ゲート電極、転送電極)には入力グー)IGのチャ
ネル電位の測定に影響しないように電源32から例えば
15Vの電圧を印加する。
Other gate weight 4:F (!7 set dirt electrode,
A voltage of 15 V, for example, is applied from the power supply 32 to the output gate electrode and transfer electrode so as not to affect the measurement of the channel potential of the input IG.

上記のような4;テ成において、第11図の電位図を参
照して動作を説明する。
The operation in the above-mentioned 4;T configuration will be explained with reference to the potential diagram in FIG.

まず、スイッチSWの可動接点をターミナルIflll
に接続し、所定時間後にターミナル■側に接続すると、
入力グー)ICのチャネル電位φIGと入力ソースIS
の電位φ18が等しい状態となる。従って、入力ソース
ISO電位を直流電圧計21で測定すれば入力グー)I
Gのチャネル電位を察知できる。
First, connect the movable contact of the switch SW to the terminal Ifllll.
If you connect it to the terminal ■ side after a specified period of time,
input source) IC channel potential φIG and input source IS
The potentials φ18 of the two terminals become equal to each other. Therefore, if you measure the input source ISO potential with the DC voltmeter 21, the input source is
G channel potential can be sensed.

また、例えば第10図における転送電極29におけろ制
御信号φ、が供給されるDのダート電圧がOvでのチャ
ネル電位を測定する場合は、制御信号φ、の電位をQV
とし、入力ダートIGに15Vを印加する。そして、ス
イッチSWの可動接点をターミナルI側に接続し、所定
時間後にターミナル■側に接続する。この時のπL電位
図第12図に示す。図示するように上記スイッチSWの
切換え操作によシ転送電極29における制(IIII仏
号φ、が供給される゛に4IiDのチャネル電位φ9ど
入カソースxsc1電位φ□8とが等しくなるので、こ
の時の入力ソースISO電圧を直流電圧計21によって
測定することによシチャネル電位φ9か察知できる。
For example, when measuring the channel potential when the dart voltage of D to which the control signal φ is supplied to the transfer electrode 29 in FIG. 10 is Ov, the potential of the control signal φ is
and apply 15V to the input dart IG. Then, the movable contact of the switch SW is connected to the terminal I side, and after a predetermined time, is connected to the terminal ■ side. The πL potential diagram at this time is shown in FIG. As shown in the figure, the control (III) φ at the transfer electrode 29 is supplied by the switching operation of the switch SW, and the channel potential φ9 of 4IiD becomes equal to the input source xsc1 potential φ□8. By measuring the input source ISO voltage using the DC voltmeter 21, the channel potential φ9 can be detected.

〔発明の効果〕〔Effect of the invention〕

以上説明したようにこの発明によれば、チャネル電位の
測定が短時間に容易に行なえ、かつ測定誤差の小さいす
ぐれたチャネル電位測定装置が得られる。
As described above, according to the present invention, it is possible to obtain an excellent channel potential measuring device that can easily measure channel potential in a short time and has small measurement errors.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のチャネル電位測定装置を示す構成図、第
2図(a)〜(C)はそれぞれ上記第1図のチャネル電
位測定装置の動作を説明するための電位図、8g3図は
この発明の一実−ha例に係るチャネル電位測定装置を
示すrり成因、第4図および第5図(a) 、 (b)
はそれぞれ上記第3図のチャネル電位測定装置の動作を
説明するためのタイミングチャートおよび電位図、第6
図はこの発明の他の実施例を示す構成図、第7図および
第8図(a)〜(c)はそれぞれ上記第6図のチャネル
電位測定装置の動作を説明するためのタイミングチャー
トおよび電位図、2!!9図は上記第6図のチャネル電
位測定JL f’iで測定したダート印加電圧とチャネ
ル電位とのyJ係を示す特性図、第10図〜第12図は
それぞれこの発明の他の実施例を説明するための図であ
Z)。 11・・・被汀用定用ハ10Sトランジスタ、13・・
・ソース領域、14・・・ドレイン領域、17・・・ダ
ート電極、21・・・直流電圧計(電圧測定手段)、2
3・・・ドレイン電位供給回路、24・・・ダート電位
供給口F13゜ 出即人代理人  弁巧(± 鈴 江 武 彦第1図 第2図 第3図 第5図 (a)        (b) 第6図 りA Jl1図 時re’t(t)− s8図 (a)             (b)第9図
FIG. 1 is a block diagram showing a conventional channel potential measuring device, FIGS. 2(a) to (C) are potential diagrams for explaining the operation of the channel potential measuring device shown in FIG. 1, and FIG. Embodiments of the Invention - Reasons for a channel potential measuring device according to an example, FIGS. 4 and 5 (a) and (b)
6 are a timing chart and a potential diagram for explaining the operation of the channel potential measuring device shown in FIG. 3 above, respectively.
The figure is a block diagram showing another embodiment of the present invention, and FIGS. 7 and 8 (a) to (c) are timing charts and potentials for explaining the operation of the channel potential measuring device shown in FIG. 6, respectively. Figure, 2! ! FIG. 9 is a characteristic diagram showing the yJ relationship between the dart applied voltage and the channel potential measured by the channel potential measurement JL f'i in FIG. This is a diagram for explanation. 11... Regular use C10S transistor, 13...
- Source region, 14... Drain region, 17... Dart electrode, 21... DC voltmeter (voltage measurement means), 2
3... Drain potential supply circuit, 24... Dart potential supply port F13° immediate representative Benko (± Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 5 (a) (b) 6th diagram A Jl1 diagram time re't(t) - s8 diagram (a) (b) Figure 9

Claims (5)

【特許請求の範囲】[Claims] (1)  被測定用素子のドレインに第1.第2の電位
を供給するドレイン電位供給手段と、上記素子のソース
と基準電位間に接続される高入力インビーダンスな電圧
測定手段と、上記素子のソース、ドレイン間のチャネル
電位を制御する電位を与える手段とを具備し、上記素子
のドレインに第1の電位を所定時間供給した後第2の電
位を供給し、この時のソース、基準電位間の電圧を上記
電圧測定手段で測定することKよシ被測定用素子のチャ
ネル電位を上記測定値によって察知するように構成した
ことを特徴とするチャネル電位測定装置。
(1) Attach the first to the drain of the device to be measured. drain potential supply means for supplying a second potential; high input impedance voltage measuring means connected between the source of the element and the reference potential; and a potential for controlling the channel potential between the source and drain of the element. and supplying a first potential to the drain of the element for a predetermined period of time, then supplying a second potential, and measuring the voltage between the source and the reference potential at this time with the voltage measuring means. A channel potential measuring device characterized in that the channel potential of the element to be measured is detected by the above measurement value.
(2)上記ドレイン電位供給手段は、低電圧を発生する
第1電位供給源と、高い正電圧を発生する第2電位供給
源と、上記第1および第2電位供給源の電位を切換えて
上記被測定用素子のドレインに供給するスイッチとから
成ることを特徴とする特許請求の範囲第1項記載のチャ
ネル電位測定装置。
(2) The drain potential supply means switches the potentials of a first potential supply source that generates a low voltage, a second potential supply source that generates a high positive voltage, and the first and second potential supply sources to 2. The channel potential measuring device according to claim 1, further comprising a switch for supplying the voltage to the drain of the device to be measured.
(3)上記被測定用素子のソース、ドレイン間のチャネ
ル電位を制御する電位は、階段拠にレベルの変化する電
位で、この電位が一定レベルの間に上記ドレイン電位供
給手段によって第1゜第2の電位を供給し、各レベル毎
のチャネル電位を測定するように構成したことを特徴と
する特許請求の範囲第1項記載のチャネル電位測定装置
(3) The potential that controls the channel potential between the source and drain of the device under test is a potential whose level changes step by step, and while this potential is at a constant level, the drain potential supply means is used to 2. The channel potential measuring device according to claim 1, wherein the channel potential measuring device is configured to supply two potentials and measure the channel potential for each level.
(4)上記被測定用素子は、′MDSトランジスタであ
る仁とを特徴とする特許請求の範囲第1項記載のチャネ
ル電位測定装置。
(4) The channel potential measuring device according to claim 1, wherein the device to be measured is an MDS transistor.
(5)上記被測定用素子は、CCD転送レジスタであり
、その各電極下のチャネルの電位を測定することを特徴
とする特許請求の範囲第1項記載のチャネル電位測定装
置。
(5) The channel potential measuring device according to claim 1, wherein the device to be measured is a CCD transfer register, and the channel potential under each electrode of the device is measured.
JP17482182A 1982-10-05 1982-10-05 Apparatus for measuring channel potential Pending JPS5965262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17482182A JPS5965262A (en) 1982-10-05 1982-10-05 Apparatus for measuring channel potential

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17482182A JPS5965262A (en) 1982-10-05 1982-10-05 Apparatus for measuring channel potential

Publications (1)

Publication Number Publication Date
JPS5965262A true JPS5965262A (en) 1984-04-13

Family

ID=15985247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17482182A Pending JPS5965262A (en) 1982-10-05 1982-10-05 Apparatus for measuring channel potential

Country Status (1)

Country Link
JP (1) JPS5965262A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5788367A (en) * 1980-11-20 1982-06-02 Fujitsu Ltd Measuring circuit for semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5788367A (en) * 1980-11-20 1982-06-02 Fujitsu Ltd Measuring circuit for semiconductor device

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