JPS5964892A - Display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention is a raster scan (luster 5can)
The present invention relates to an operation of reading display information from a refresh memory in a (raster scanning) type display device, and particularly relates to the case of interlaced scanning.

Figure 1 is a block diagram showing the configuration of the display device for this right.
(1) is a display information generation section, (21) is a refresh memory section, (13) is a smart control section, (4) is a display section, and (5) is a readout control section.

The display section (41 is composed of, for example, a cathode ray tube display device, and to improve the display, characters and figures are displayed in the form of a dot pattern. Each dot constituting this display dot pattern is a 1 bit (white or black dot). ) or a signal of a predetermined plurality of bits (color tods or dots with intermediate tones).The number of bits (l or plurality) corresponding to one dot is hereinafter expressed as P). In the refresh memory section (2), a bit corresponding to the dot (hereinafter referred to as display dot information) is stored at an address corresponding to the dot position on the display section (41).The read control section (51 is the display section (4) In synchronization with the sweep of the brightness, display dot information is read out from the refresh memory section (21) and characters and figures made up of dot patterns are displayed on the display section (41).

The dot patterns of characters and figures are displayed in the display information generation section (1).
(consisting of a character generator, for example), and is written to the refresh memory section (21) under the control of the write control section (3). It is possible to be changed and read out by the readout control unit (51) at the same time.

FIG. 2 is a diagram showing the address structure of the refresh memory unit (2). For convenience of explanation, if we assume that addresses start from number 1 in both the X direction and the Y direction, the X direction address is l. -M, Y direction address is 1 to L (IXI)
The address can be composed of any numerical value in the range of .about.(LXM).

For convenience of writing and reading in the refresh memory section (2), the memory contents corresponding to one address serve as a control unit.

FIG. 3 is a diagram showing the storage contents corresponding to one address in FIG. 2, where the addresses (X-1, Y-1), (X.

y-t), (X-t, Y), and (XtY), one address includes JXK pieces of display dot information. The arrangement shown in FIGS. 2 and 3 corresponds to the arrangement of dots on the display section (41).

For example, when displaying a dot pattern of 256 x 256 dots on the display surface of the display unit (41),
In the figure, M=L=64. If J=4, we can obtain a memory in which each dot corresponds to one bit (P=1). In the case of P=2, if two such memories are installed, they can be read out simultaneously by the same address signal, but since the value of P is not directly related to this invention, the following explanation will be given in the case of P=l. Do about. By the way, the physical arrangement of memory elements in the refresh memory section 12) is
It does not match the figure and Figure 3. This is because the memory elements used to construct such a refresh memory section (2) have an address arrangement of one word and one pit. For example, LM=64 x 64 = 4,
096 is 4,096 bit capacity is 4,096
Sixteen memory elements in a word x 1 bit configuration must be used in parallel.

This is because if one memory element of 4,096 bits x 16 = 65,536 bits is used, one bit is one word, so JxK bits cannot be read out simultaneously with one address.

FIG. 4 shows the configuration 911k of the refresh memory section (2).
In the block diagram shown, (20) are memory elements each having a configuration of 4,096 words x 1 pit, (21) and (2
2), (23), and (24) are registers, respectively, and (25) is a signal line for an address signal. Bits at the same address of 16 memory elements (20) are read out simultaneously and the registers (21), (22), (23)
.

(24) and sequentially provided to the display section (4).

The order of JXK bits at the same address can be expressed as j=1~4゜k=3~4. It is shown. However, as far as reading the refresh memory section (2) is concerned, dot information (
In FIG. 3, different j indicates different raster nets, and in FIG. 4, registers (21), (22), (23).

(24) each storing information for different raster elements) does not need to be read out simultaneously, so the unit capacity of the memory elements can be increased and the number of them can be reduced. Figure 5 is a block diagram showing a design example in which the unit capacity of memory elements is doubled compared to the configuration in Figure 4, and the number of memory elements is reduced to 1. Memory element of configuration, (27).

(28) are registers. In order to read all bits of the refresh memory section (2), in the configuration shown in FIG. 4, it is better to change the address signal from 1 to 4,096, but in the configuration shown in FIG. 5, only 8 bits can be read with one address signal. After changing the address signal from l to 4,096 without being able to output it, it further increases to 4,096 + l → 4,096 + 4,09
It takes twice as much time because it has to change up to 6, but the circuit configuration becomes simpler. Generally, if the address of the memory element (20) in Fig. 4 is 1→L% in the X direction and 1-+M in the Y direction, then the address of the memory element (26) in Fig. 5 is 1→L in the X direction. %The Y direction changes from 1 to 2M, and J=2 instead. Therefore, if the time required to access the memory element (26) with one address signal is fTc, the time required to access all addresses of the memory element (26) is T. , in the configuration shown in Figure 2.5, Tt=LX2MxTc...
...(1) becomes.

Since the conventional refresh memory is constructed as explained in connection with FIG. 5, it has the disadvantage that it takes a long time to perform display using interlaced scanning. Generally, when displaying by interlaced scanning, odd numbered rasters are displayed the first time (assuming the number representing the first raster is 1), and even numbered rasters are displayed the second time. Whether displaying odd-numbered rasters or even-numbered rasters, all addresses of the memory element (26), that is, all LX2M addresses, are read out and any of the read data is stored in the registers (27) and (28). Since only one of the frames is sent to the display unit (4), the time To required for displaying one frame by interlaced scanning is twice the time T1 shown in equation (1). That is, Tn
= 2 x (Lx 2MXTc) −・−−−−−
Since it is necessary to perform write control at the same time as read control for f21.degree. refresh memory section 12), it is disadvantageous that read control requires a long time in the case of interlaced scanning.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional one, and is a refresh memory that can read out the memory element (26) by all addresses within the time shown in equation (1) even in interlaced scanning. is intended to provide.

The present invention will be described in detail below with reference to the drawings.

FIG. 6 is a block diagram showing one embodiment of the present invention.
The same reference numerals as in FIG. 5 indicate the same or corresponding parts. The two memory elements (26) at the left end of FIG. 5 are shown in FIG. 6.

The memory elements (26) are all located at the address l→M portion (
Divided into the shaded area) and the lyl + l → 2M area (2
6a), (2fib), (26c), and (26d).

(26a) has j = 1, (26b) has j =
2, j=3 for (2fic), j for (26d)
Bits responsible for the information of =4 are stored. When the address on the address signal line (29) is 1-+M, j=t
% The bits corresponding to the odd raster of j=3 are read out and the odd raster is displayed on the display section (41.Address Z
During the period from EM+1 to 2M, bits corresponding to the even raster of j=2 and j=4 are read out, and an even raster is displayed on the display section.

Therefore, in the device shown in FIG. 6, even if interlaced scanning is performed, all frames need to be read by accessing the LX2M address, and the required time is calculated using the formula (1;% formula%). However, if P is multiple, P
The number of memory elements shown in FIG.
) in parallel.

As described above, the display device of the present invention can perform display using interlaced scanning without changing the number of memory elements.
The contents of the refresh memory section (2) can be read and displayed in the same time as when no interlaced scanning is performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the display device, FIG. 2 is a diagram showing the address configuration of the refresh memory section in FIG. 1,
FIG. 3 is a diagram showing the storage contents corresponding to one address in FIG. 2, FIGS. 4 and 5 are block diagrams each showing an example of the configuration of the refresh memory section, and FIG. 6 is a diagram showing one embodiment of the present invention. FIG. (11...Display information generation section, (2)...Refresh memory section, (31...Write control section, (41...
Display section, (5)...Readout control section, (26)...Memory element, (26a), (26c)...Storage area for odd raster, (26b), (26d)...Even raster storage areas, (27), (28)...respective registers. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Shin Kuzuno - Figure 5 Figure 6

Claims (1)

[Claims] In a display device having a cathode ray tube display section that performs interlaced scanning, a refresh memory section having a bit array that two-dimensionally corresponds to the pixel arrangement on the display screen of the display section is composed of a plurality of memory elements each having a 1-bit configuration. and the means to
Each memory element of the plurality of memory elements is simultaneously accessed using the same address signal, and each memory element is
means for reading bit data, means for sequentially changing the address signal, and storing bits corresponding to odd raster scanning in each of the memory elements in sequential address positions in the order of odd raster numbers in connection with the interlaced scanning; means for storing bits corresponding to even raster scanning in consecutive address positions in the order of even raster numbers; and means for reading out the bits stored in the consecutive address positions in the order of the odd raster numbers and subsequently in consecutive addresses in the order of the even raster numbers. 1. A display device comprising: means for controlling reading of a bit stored in a position.