JPS5963762A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a small-sized high-speed semiconductor device, a wiring thereof is patterned easily, by adjacently arranging a base and an emitter in a flat region through a self-alignment method by a simple manufacturing process. CONSTITUTION:An n<-> epitaxial layer 10 is superposed on an n<+> collector 2 buried in a p<-> substrate 1, and an As added poly Si island 19 is formed selectively on the surface, which is extracted to the surface from the n<+> layer and insulated and isolated 12, while using SiN 20 as a mask. The whole surface is coated with SiO2 21 (21a-21c) including side surfaces, B is implanted, and the p base 22 and the n emitter 23 are formed through heat treatment. The SiO2 21b is removed selectively through reactive ion etching, Al (or Al silicide) 24, SiO2 25 and a resist mask 26 are superposed, and the mask 26 and the film 25 are removed uniformly through reactive ion etching to expose the SiN 20. The Al 24 is patterned, and coated with an SiO2 27, a resist mask 28 is executed and a window is bored, the mask 28 is removed, the Al electrode is attached, and the device is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a transistor manufactured by self-alignment.

(2) Technology background Recently, semiconductor devices such as bipolar transistors have been
(Integrated circuit), LSI (Large scale integrated circuit), etc.
Transistors are constructed using a structure called PSS T (Plane 5upper Self
A structure called "align transistor" has been proposed.

For example, by such PSST, NTL (Non T
There is a report that when a threshold logic) circuit is formed, it is possible to obtain a fairly high-speed semiconductor device with a per-gate speed of 80 ps.

Since the above-mentioned EEIC has extremely difficult construction methods, there has been a need for a method of manufacturing a semiconductor device using a self-fabricated line, which is a simple manufacturing method even if the speed is slightly lowered.

(3) Prior art and problems FIG. 1 shows a side sectional view of the conventional EEIC structure described above, in which a buried layer 2 is formed in a P-type substrate 1 made of silicon or the like, and collector diffusion Jff3. Hess diffusion layer 4. An emitter diffusion layer 5 is formed in the epitaxial layer 10, and an inverted trapezoidal polysilicon layer 6 is formed on the upper part of the emitter diffusion IPi5. SiO2) is formed,
A wiring electrode 7 made of A (aluminum) or the like for the emitter is formed on the upper part, and A crossing line electrodes 8, 8.9 for the base and collector are also provided on the surface of the base diffusion layer 4 and the surface of the collector diffusion layer, respectively. Note that 12 is an oxide film.

In E and EICs with such a structure, the base wiring electrode 8.8 has an inverted trapezoidal structure and can be placed extremely close to the emitter, allowing for faster speeds. In order to form an inverted trapezoid, it is necessary to change the etching rate during etching to form an inverted trapezoid, which makes manufacturing extremely complicated, and because the surface is not flat, wiring patterning is extremely difficult during IC fabrication. It had drawbacks.

(4) Purpose of the Invention In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a method for manufacturing a semiconductor device using a self-line, in which the manufacturing process is simple and wiring patterning is easy.

(5) Structure of the Invention According to the present invention, after forming the collector region on the substrate, a polysilicon film doped with arsenic or the like is formed on the apertured base and the emitter region. , forming a first insulating film such as silicon nitride on the polysilicon film,
The first polysilicon and insulating film are patterned to remain only in the emitter region, an oxide film is formed on the side of the remaining polysilicon film, and after the base and emitter regions are diffused, the patterned part and the substrate surface are patterned. A semiconductor characterized in that a metal or metal silicide is further formed on the metal or metal silicide, a second insulating film is formed thereon, the second insulating film in the emitter region is removed, and the metal or metal silicide is used as a base electrode. This is achieved by a method of manufacturing the device.

(6) Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to FIG. 2 ta+ to (Ql).

FIGS. 2(a) to 2(q) are side cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method of the present invention.

In FIG. 2 Tal, ■ is, for example, a P-type silicon substrate, the substrate is oxidized to form an oxide film (SiO2) 13, a window 14 for a buried diffusion layer is formed, and As is formed by ion implantation. into the surface of the substrate 1. For example, the doping amount may be approximately 7 x xolffi cm-) and the implantation voltage may be 60 K eV.

Next, as shown in FIG. 2 (bl), a buried layer 2 is formed by performing annealing.

Furthermore, epitaxial growth is performed as shown in FIG. 2 TCI.

This is made of N- with a specific resistance of about 0.5Ω and grown to a thickness of 2 μm, then a 5iN (silicon nitride) film 15 is formed, and the SiN film 15 is buttered to perform fill oxidation. ). Part 16 has a flat surface. , Susume 0. 7 shows the part that was cut.

Next, as shown in FIG. 2(e), a filled oxide film 12 is formed, the SiN film 15a in the portion that will become the collector region is removed, and a resist film 17 is applied, after which a window opening pattern 18 is applied to the collector region. Then, P (phosphorus) is implanted by ion implantation, the resist film 17 is removed as in step 211(f), and annealing is performed to form the N+ portion 3 of the collector diffusion frM region.

Next, after removing the SiN film 15 and forming an As-doped polysilicon film or a non-doped polysilicon film, as shown in FIG. 19 is formed.

Next, as shown in FIG. 2thi, a SiN film 20 is grown to a thickness of 1000 on the four-layer polysilicon film lb, and the polysilicon film 19 is patterned using the SiN film 20 as a mask.

Next, by oxidizing at a low temperature of <800°C to 1000°C as shown in FIG. An oxide film 21b is grown to a thickness of about 1,300 layers, and an oxide film 21c is also formed on the SiN film 2o-hi.

Next, perform external-based ion implantation as shown in Figure 2 (jl).For example, move button 11 (13) to
The implantation is performed with an implantation voltage of 0 KeV and a tope amount of about I x 10"cm-'. Thus, the base region 22 is formed.

Further, as shown in FIG. 2 (kl), when annealing and emitter diffusion is performed, As doped into the polysilicon film is diffused to form an emitter region 23.

Next, as shown in FIG. 2+1), the oxide film (SiO2) 21b on the external base is removed by reactive ion etching or ion milling.

Next, as shown in Figure 2+ml, when a metal or metal silicide F24 such as A pattern is formed by sputtering or vapor deposition, the emitter region has a step, so the metal or metal silicide 24a also adheres on the oxide M*21c. .

Insulating material 11ii25 may be formed by spacing or the like to cover these metals or metal silicides 24.degree. 248, or a low temperature (400.degree. C. or less) vapor phase growth film may be formed. The insulating film can be selected from SiO2 or the like.

If metal silicide is selected, the resistance can be lowered compared to polysilicon, etc., but the metal culm resistance cannot be lowered. However, when forming the insulating film 25, the film can be formed by increasing the temperature. .

On the other hand, in the case of metal, although the resistance can be lowered, there is a problem in that the temperature cannot be raised during the formation of the insulating film, and it is advisable to take these into consideration when deciding whether to select metal or metal silicide.

Next, as shown in FIG. 2 tn+, a resist film 26 is applied on the insulating film 25, and ion milling or RIE is performed to remove the resist 26 and the oxide film 25 so as to uniformly etch them. In this way, it is possible to etch up to the surface of the nitride film 20 on the polysilicon film 19 serving as the emitter diffusion source.

The composition of the etching gas used in RIE allows the resist film 26 and the oxidized l*25 to be etched at the same time. For example, Cl4F3
+02 etc. can be used.

Next, as shown in FIG. 2 (01), the resist 26 is peeled off.

Next, as shown in FIG. 2 (pi), the base metal 24 is patterned, and a SiN or SiO2 film 27 is grown using plasma or spuck.

Furthermore, a resist 28 is applied to open windows in the base, emitter, and collector portions.

In this case, if the base part is made up of the oxide film 25 and the nitride film 27, it is preferable to perform dry etching since these have different etching rates, and since the emitter part is made up of only the nitride film or oxide film 27, the emitter part and the base part are separated. It is preferable to open the window in a separate process.

Finally, as shown in FIG. 2 (q), after removing the resist 28, an A or electrode 29 is formed in the window opening portion.

(7) Effects of the Invention As described above in detail, the semiconductor device having the structure of the present invention not only becomes extremely compact, but also allows the base to be placed close to the emitter, making it possible to integrate it into the NTL described at the beginning. The speed per gate could be improved to about 100 p's. Although this is inferior to EEl c, it is considerably faster than the 150 ps per gate speed of NTL integrated using the highest bipolar type technology.
Since the base area is flat, wiring patterning is extremely easy, and the manufacturing process is also very easy.
It has the feature of being simpler than .

[Brief explanation of drawings]

Figure 1 is a side sectional view of the conventional EEIC structure, Figure 2 +al
1 to tq+ are side sectional views of a self-aligned semiconductor element showing the manufacturing process of the semiconductor device of the present invention. DESCRIPTION OF SYMBOLS 1... One substrate, 2... Buried layer, 3... Collector diffusion layer, 4.22... Base diffusion layer, 5.2
3... Emitter diffusion source, 6... Inverted trapezoidal polysilicon layer, 7,8.9... Wiring electrode, 11. 12
．． 2! a, 2 l b. 21c, 24... Oxide film, 15.20... SiN
Film, 19... Polysilicon film, 22... Metal or metal silicide, 28... Resist film,
27c, 29...electrodes. 1i! Part 11 Wing Figure 21 Z diagram 2nd item

Claims (1)

[Claims] After forming the collector region on the substrate, the base is opened with a window,
A polysilicon film doped with arsenic or the like is formed on the emitter region, a first insulating film such as silicon nitride is formed on the polysilicon, and the polysilicon and the first insulator are formed only in the emitter region. An oxide film is formed on the side of the remaining polysilicon film, and after diffusion of the base and emitter regions, a metal or metal silicide is formed to cover the patterned part and the substrate surface, and then on top of that. 1. A method of manufacturing a semiconductor device, comprising forming a second insulating film, removing twelve sharp edge films in an emitter region, and using the metal or metal silicide as a base electrode.