JPS5963719A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5963719A
JPS5963719A JP17503982A JP17503982A JPS5963719A JP S5963719 A JPS5963719 A JP S5963719A JP 17503982 A JP17503982 A JP 17503982A JP 17503982 A JP17503982 A JP 17503982A JP S5963719 A JPS5963719 A JP S5963719A
Authority
JP
Japan
Prior art keywords
substrate
metal
resistance
low resistivity
recesses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17503982A
Other languages
Japanese (ja)
Inventor
Toshimitsu Konno
今野 俊光
Chukei Kaneko
金子 忠敬
Naoyuki Tsuda
津田 直行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP17503982A priority Critical patent/JPS5963719A/en
Publication of JPS5963719A publication Critical patent/JPS5963719A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

PURPOSE:To contrive to reduce the substrate component of a series resistor and the reverse recovery time by forming a recess in a low resistant semiconductor substrate and burying a metal into this recess. CONSTITUTION:Recesses are selectively formed on the other surface side of the low specific resistant substrate 1 provided with a high resistant semiconductor layer 2 on one surface. Next, contact metals 5 are vapor-deposited in these recesses, and the metal 4 is buried in these recesses. Then, an electrode layer 3 is vapor-deposited. Thereby, the substrate component of the series resistor and the reverse recovery time can be remarkably improved.

Description

【発明の詳細な説明】 産業上の利用分野 この発明は半導体装置に関し、肋に、低比抵抗基板上に
高比抵抗層を形成した半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to a semiconductor device, and more particularly to a semiconductor device in which a high resistivity layer is formed on a low resistivity substrate.

従来例の構成とその問題点 一般に、低比抵抗基板上に高比抵抗層會形成した半導体
装置にあっては、低比抵抗層基板は高比抵抗層を単に保
持するためにあり、半導体装置の動作の上からは不用で
ある。そこで従来は、低比抵抗基板全体を均一に薄くシ
、抵抗を下げていた。
Conventional configurations and their problems In general, in semiconductor devices in which a high resistivity layer is formed on a low resistivity substrate, the low resistivity layer substrate is simply used to hold the high resistivity layer, and the semiconductor device It is unnecessary from the top of the operation. Conventionally, the entire low resistivity substrate was made uniformly thin to lower the resistance.

この従来例の断面構造を第1図に示す。第1図において
1が低比抵抗基板、2が賃比抵抗層、3がオーミックコ
ンタクト用の金属である。この構造は、例えばU/V切
換え用バンドスイッチ・ダイオードにおいて、高周波直
列抵抗rs値を低減するのに不可欠である。しかし、低
比抵抗基板1全体全均一に薄くするにも半導体ウニ・・
−の加工上限度があり、上記バンドスイッチ・ダイオー
ドなど半導体装置において、rsで決する逆回復時間t
rr等の値が未だ十分に低減しす扛すい面があった。
The cross-sectional structure of this conventional example is shown in FIG. In FIG. 1, 1 is a low resistivity substrate, 2 is a low resistivity layer, and 3 is a metal for ohmic contact. This structure is essential for reducing the high frequency series resistance rs value, for example in a band switch diode for U/V switching. However, in order to make the entire low resistivity substrate 1 uniformly thin, the semiconductor sea urchin...
- There is an upper limit for processing, and in semiconductor devices such as the above band switch diode, the reverse recovery time t determined by rs
There were still some areas where the values of rr etc. were still sufficiently reduced.

発明の目的 この発明は上記欠点を除去し、低比抵抗基板の従来と同
等な厚さをさらに部分的に薄くシ、この部分に金属を充
填することによって直列抵抗低減を可能としたものであ
る。
Purpose of the Invention The present invention eliminates the above-mentioned drawbacks, and makes it possible to reduce the series resistance by partially reducing the thickness of the low resistivity board, which is equivalent to the conventional one, and by filling these parts with metal. .

発明の構成 この発明の半導体装置は低比抵抗基板の一方の面に高比
抵抗基板を有し、この低比抵抗基板の他面側に選択的に
形成さnた凹部に金属層が埋め込″!!nだ半導体装置
である。
Structure of the Invention The semiconductor device of the present invention has a high resistivity substrate on one side of a low resistivity substrate, and a metal layer is embedded in a recess selectively formed on the other side of the low resistivity substrate. ``!!It's a semiconductor device.

実施例の説明 第2図はこの発明の一実施例であるバンドスイッチダイ
オード・ベレットの断面を示す図である。
DESCRIPTION OF THE EMBODIMENTS FIG. 2 is a cross-sectional view of a band switch diode pellet according to an embodiment of the present invention.

同図において第1図と同一番号は同一部分を示し、4が
低比抵抗基板1の凹部に埋め込titた金属で、6は凹
部のオーミック用金属である。
In the figure, the same numbers as in FIG. 1 indicate the same parts, 4 is a metal embedded in the recess of the low resistivity substrate 1, and 6 is an ohmic metal in the recess.

この半導体装置において具体的には、1はアンチモンを
ドープした比抵抗0.009〜○、o18Ωイ〃lのシ
リコン単結晶基板で厚さは約12077772 、2は
リンをドープ−た比抵抗8〜12Ω・C1rtのエピタ
キシャルシリコン層で厚さは約571η2である。シリ
コン・ベレットのサイズはO−357m :X:0.3
6 ff1Wである。まず、シリコン基板の表面側にバ
ンドスイッチダイオードの通常の拡散及び電極形成を行
う。その後、従来通り基板1の裏面側を均一にエツチン
グにより薄くする。そnから周知のリフトオフ用写真食
刻法により、ポジのフォトレジストを用いて、このレジ
ストをマスクとして例えば第3図に斜線を付して示した
部分4のように選択的に基板1をエツチングする。この
際、そのエツチング深さは、低比抵抗基板1のエツチン
グさ扛た領域の厚さがエツチングさ−nなかった残りの
他の領域と比し深さ3o〜6o%だけくぼむように、側
温jする。さらに、レジストはその筐\残した状態で、
スパッタ蒸着法により金もしくはAuSb @どの合金
5をコンタクト用金属として厚さ約0・1μmだけ蒸着
する。ついで、上記エツチングにより形成さrした凹所
にだけ、金属4として、ニッケルのめっきにより冊ノケ
ルを埋める。このときめっき景が多すぎるとニッケルの
曲部分が発生したり、パリが顕著になって次工程のリフ
トオフが困難になるので注意を要する。ニッケルめっき
はウェハー裏面がはソ平坦になるように実施する。その
後、リフトオフ法により上記レジストを完全に除去し去
る。そして真空蒸着法によりAuSb yどを、電極層
3として、ウニ・・−裏面側に蒸着する。
Specifically, in this semiconductor device, 1 is a silicon single crystal substrate doped with antimony and has a resistivity of 0.009 to 0, and a thickness of about 18Ω, and 2 is a silicon single crystal substrate doped with phosphorus and has a resistivity of 8 to 18Ω. The epitaxial silicon layer is 12Ω·C1rt and has a thickness of about 571η2. The size of the silicone pellet is O-357m:X:0.3
6ff1W. First, usual diffusion and electrode formation of a band switch diode are performed on the front side of a silicon substrate. Thereafter, the back side of the substrate 1 is uniformly thinned by etching as usual. From then on, using a positive photoresist and using this resist as a mask, the substrate 1 was selectively etched, for example, as shown in the hatched areas 4 in FIG. 3, using a well-known lift-off photolithography method. do. At this time, the etching depth is set so that the thickness of the etched region of the low resistivity substrate 1 is depressed by 30 to 60% in depth compared to the remaining region that has not been etched. It's warm. Furthermore, the resist remains in its casing,
Gold or AuSb@alloy 5 is deposited as a contact metal to a thickness of about 0.1 μm by sputter deposition. Then, only the recesses formed by the above etching are filled with nickel plating as the metal 4. At this time, care must be taken because if there are too many plating areas, curved portions of nickel may occur or Paris may become noticeable, making lift-off in the next process difficult. Nickel plating is performed so that the back surface of the wafer is flat. Thereafter, the resist is completely removed by a lift-off method. Then, AuSb y or the like is deposited as an electrode layer 3 on the back side of the sea urchin by vacuum deposition.

このように製作さnたバンドスイッチダイオードの断面
構造が第2図に示すものである。
The cross-sectional structure of the band switch diode manufactured in this way is shown in FIG.

第2図および第3図示の構成で、低比抵抗基板1の厚さ
を41面積をA1薄くした部分の厚さをR′、面積をA
′、裏面加工しない場合の低比抵抗基板の抵抗をR1裏
面加工した場合の抵抗をR′とすnば、 となり、l/(1’>1であるからR’/ R(1であ
る。
In the configuration shown in FIGS. 2 and 3, the thickness of the low resistivity substrate 1 is reduced by 41 area by A1, and the thickness is R' and the area is A.
′, the resistance of the low resistivity substrate when the back side is not processed is R1, and the resistance when the back side is processed is R′, then, since l/(1′>1, R′/R(1).

低比抵抗基板1を、例えば、A’/ A = o、s 
、 l/l’=2とすnば、R’/ R=F−0,67
Tあり、約23チの抵抗低減が可能である。
The low resistivity substrate 1 is, for example, A'/A = o, s
, l/l'=2 and n, R'/R=F-0,67
With T, it is possible to reduce the resistance by about 23 inches.

前記の実施例に従って製作したダイオードの直列抵抗r
B値を逆バイアス状態で高周波測定法により求めた。エ
ピタキシャル層の直列抵抗成分を消去するために、逆バ
イアスし、空乏層の先端が低抵抗基板に到達した時点で
の高周波抵抗及び容−Ffiを求めた。この高周波抵抗
値を直列抵抗rSの低抵抗基板成分とみなした。
The series resistance r of the diode manufactured according to the previous example
The B value was determined by high frequency measurement in a reverse bias state. In order to eliminate the series resistance component of the epitaxial layer, a reverse bias was applied, and the high frequency resistance and capacitance -Ffi were determined at the time when the tip of the depletion layer reached the low resistance substrate. This high frequency resistance value was regarded as a low resistance substrate component of the series resistance rS.

抵抗成分値をエツチング深さに対してプロットした分布
の結果を第4図に示す。尚、エツチング11.深さ以外
は第2図、第3図に示す実施例と同一とする。エツチン
グ量ゼロの基板厚さ120/7772の場合は約0・1
Ω、こnを60μmだけエツチングした後には約o・0
7Ω、70 p、mだけエツチングした後には約0・0
6Ωのrg値基板成分が得らnた。
FIG. 4 shows the distribution of resistance component values plotted against etching depth. In addition, etching 11. The structure is the same as the embodiment shown in FIGS. 2 and 3 except for the depth. Approximately 0.1 in case of substrate thickness 120/7772 with zero etching amount
After etching Ω and this by 60 μm, it becomes approximately o・0.
After etching by 7Ω, 70p and m, it is approximately 0.0.
An rg value substrate component of 6Ω was obtained.

また逆回復時間trr値としてはエツチング量ゼロの場
合351S、60μmだけエツチングした後には3Qn
S と低減した。なお、70μ772よりも更にエツチ
ングすると、分布が広がるとともにシリコン基板ノ・−
の加工上の歩留が低減する。また、オーミックコンタク
トの抵抗は−F記値に比較して無視できる値である。
In addition, the reverse recovery time trr value is 351S when the etching amount is zero, and 3Qn after etching by 60 μm.
It was reduced to S. Note that when etching is performed further than 70 μ772, the distribution widens and the silicon substrate becomes thinner.
The processing yield will decrease. Further, the resistance of the ohmic contact is a value that can be ignored compared to the value indicated by -F.

発明の効果 以上のように、本発明は低抵抗半導体基板に凹部を形成
し、この四部にニッケルのメッキし、この四部の厚さを
他の領域と比し40〜70%薄くすることによ・す、直
列抵抗r5の基板成分及び逆回復時間trrを著しく改
善でき、すぐnた実用的効果を有するものである。
Effects of the Invention As described above, the present invention is achieved by forming a recess in a low resistance semiconductor substrate, plating these four parts with nickel, and making the thickness of these four parts 40 to 70% thinner than other areas. - The substrate component of the series resistor r5 and the reverse recovery time trr can be significantly improved, and this has immediate practical effects.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の半導体装置のベレット断面図・第2図は
本発明の実施例に係る半導体装置ペレノトの断面図、第
3図は半導体ペレットの裏面低抵抗基板を部分的に薄く
したパターン形状図、第4図は本発明実施例に係るダイ
オードの直列抵抗r3とエツチング深さの関係図である
。 1・・・・・・低抵抗半導体基板、2・・・・・・高抵
抗半導体層、3,5・・・・・・オーミックコンタクト
用金属、4・・・・・・金属。
Fig. 1 is a cross-sectional view of a pellet of a conventional semiconductor device, Fig. 2 is a cross-sectional view of a semiconductor pellet according to an embodiment of the present invention, and Fig. 3 is a pattern shape in which a low-resistance substrate on the back side of the semiconductor pellet is partially thinned. 4 are diagrams showing the relationship between the series resistance r3 and the etching depth of the diode according to the embodiment of the present invention. 1...Low resistance semiconductor substrate, 2...High resistance semiconductor layer, 3, 5...Metal for ohmic contact, 4...Metal.

Claims (1)

【特許請求の範囲】[Claims] 低比抵抗基板の一方の面に高比抵抗層を有し、前記低比
抵抗基板の他面側に選択的に形成さfた四部をイイする
とともに、前記凹部分に金属を埋め込んだことを特徴と
する半導体装置。
A high resistivity layer is provided on one surface of the low resistivity substrate, four parts are selectively formed on the other surface of the low resistivity substrate, and metal is embedded in the recessed portions. Characteristic semiconductor devices.
JP17503982A 1982-10-04 1982-10-04 Semiconductor device Pending JPS5963719A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17503982A JPS5963719A (en) 1982-10-04 1982-10-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17503982A JPS5963719A (en) 1982-10-04 1982-10-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5963719A true JPS5963719A (en) 1984-04-11

Family

ID=15989143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17503982A Pending JPS5963719A (en) 1982-10-04 1982-10-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5963719A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4860084A (en) * 1984-09-03 1989-08-22 Kabushiki Kaisha Toshiba Semiconductor device MOSFET with V-shaped drain contact
JP2000040825A (en) * 1998-06-30 2000-02-08 Harris Corp Semiconductor device having reduced effective resistivity of substrate and manufacture thereof
US7504707B2 (en) 2003-06-05 2009-03-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4860084A (en) * 1984-09-03 1989-08-22 Kabushiki Kaisha Toshiba Semiconductor device MOSFET with V-shaped drain contact
JP2000040825A (en) * 1998-06-30 2000-02-08 Harris Corp Semiconductor device having reduced effective resistivity of substrate and manufacture thereof
US7504707B2 (en) 2003-06-05 2009-03-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US7629226B2 (en) 2003-06-05 2009-12-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof

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