JPS5962255A - Fsk demodulator - Google Patents

Abstract

PURPOSE:To obtain a completely digitized FSK demodulator, by applying square wave conversion to an input FSK signal for attaining PWM and using a decimation filter decreasing a sampling frequency while keeping the information amount. CONSTITUTION:An input FSK signal is converted into a square wave at an amplitude limit circuit. The square wave signal is converted into a pulse width modulation wave (PWM) at a digital PLL circuit. The PWM modulation wave is applied to the decimation filter and the sampling frequency is reduced while keeping the information amount of the input signal. An output of the decimation filter is supplied to a digital interpolation comparison circuit via a digital low pass filter, the linear interpolation is attained and the FSK demodulation output is obtained. Thus, the FSK demodulator is formed with the completely digitized circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a demodulator for l·''SK signals suitable for LSI implementation.

(Background technology) A typical example of a conventional FSSKJ adjuster is shown in FIG.

This demodulator is realized by a mixed analog-digital circuit, and the low-frequency 1-wave circuit uses a high-order active filter depending on the modulation speed. Therefore, the mounting area of the demodulator is increasing. For LSI implementation, it is necessary to replace analog circuits with digital circuits isometrically.

A conventionally proposed demodulator for LSI integration is shown in FIG. After converting the input 1i''sKK signal A/1], the frequency is discriminated, and the low-frequency JI wave is converted to perform digital value conversion. All of these are realized by digital circuits, but
A11) A conversion circuit is required, so it is not suitable for LSI implementation due to surface precision.

(Problem to be solved by the invention) The present invention realizes demodulation of F S [(signal) converted into a square wave by digital signal processing, part 1.
The aim is to provide a circuit configuration of li'' S K (Ji modulator) suitable for LSI implementation in order to eliminate the drawbacks of the conventional technology. In the signal demodulator, (1)
Input 1' S K signal amplitude limited and converted to square wave 1~
(2) A digital JL circuit that converts the output into a pulse width modulated signal; (3) Data latching is performed on the output at a frequency that is more than twice the fundamental frequency component, and the latched data is The weight is added so that the attenuation pole is in a band that does not affect the signal band, and the result is data latched at a frequency within the attenuation range. a decimation filter that reduces the sampling frequency while retaining the amount of information; (4) a digital low-frequency Kerr wave circuit whose output is J-connected; and (5) a decimation filter that reduces the output of the d sonic circuit and means for performing linear interpolation and providing a demodulated output of 1 or 0 by comparing the interpolated output with a predetermined threshold.

(1q configuration and operation of the invention) FIG. 3 shows a first embodiment of the invention, in which the input F S
The K signal is converted into a square wave by an amplitude limiting circuit. Next, the t'SK signal converted into a square wave is converted into a digital P
The LL circuit converts the signal into a pulse width (duty rate) modulated waveform. The operations up to this point are equivalent to the conventional circuit configuration shown in FIG. The waveform transitions are shown in (A), (B), and (C) VC in FIG. Modulated signal (A) [Thus, F S J <(1'rcquency SI+i
The signal obtained by limiting the amplitude of the rt Keying) signal is as shown in (1().) Then, by using the digital P L LM path, the pulse width (plane t
y rate) modulated signal (0 is obtained. This signal (C)
Since is a square wave, its frequency components have a spectral spread in the shape of a sampling function. Therefore, in order to sample this signal and perform No. 15 processing, high-speed (high frequency) sampling is required according to the sampling theorem. In general, a digital low-frequency f-wave circuit has an internal gain of 1 (usually the square of the sampling frequency). (function), the minimum required data word length (1) it Ieng mountain) becomes long, and at the same time, the arithmetic processing time increases.

Therefore, it is necessary to somehow reduce the high frequency spectrum of the signal (C) and reduce the sampling frequency.

A decimation filter performs this operation.

Figure 5 shows an overview of the operation of the decimation filter.

As an example, (1) in FIG. 5 shows the folded spectrum when sampling at a frequency fn-1 when the input signal spectrum is as shown in the figure, with a dotted line. Po・1
The line portion indicates the required 8' signal band. Fifth
(11) in the figure shows the frequency characteristics of the decimation filter as an example. As shown in the diagram, f111ノfru →
f at the sampling frequency. -1/2 reduced staff area (zero points)
is set. The song in Figure 5) shows the output signal spectrum when the input signal (1) is manually applied to the decimation filter (11). The result is

At this time, if the frequency spectrum near f+t-1/2 is input to a decimation filter that is set to attenuate, the frequency spectrum that folds back into the l' wave band will be small, as shown in the song in Figure 5. This operation is repeated several times until it does not affect the &" wave band, reducing the sampling frequency and at the same time reducing the high frequency spectrum. As a result, the resulting signal is shown in Figure 4 ( 1)).This signal (1) is input to the digital low frequency harmonic circuit (digital filter)1.
-, an output signal like (1) in FIG. 4 can be obtained. If this signal (1) is directly input to a digital comparator circuit, demodulation code distortion for a period twice the sampling period will occur if the sampling frequency is not sufficiently high compared to the modulation signal. Therefore, each output signal is interpolated and converted into a signal as shown in Fig. m71 (l), which is input to the digital comparator circuit.

Generally, the interpolation operation and the comparison operation can be performed in conjunction with one circuit.

1 due to digital signal processing introduced in LSI
・'51
A specific example of the functional circuit configuration of the Tenmeyon filter and its transfer function is shown in Figure 7.Furthermore, Fig. 7 shows the functional circuit configuration of the Tizotal low-frequency wave circuit and its transfer. The JL field side of the function is shown.

z(!, Figure 6 shows the functional circuit configuration of a decimation filter +1 In the process of sampling 7, in order to sequentially reduce the lean-pulling frequency and adapt the frequency spectrum of the cool digital signal to the changed sampling frequency, the frequency 7t, :, is placed. Category of filter Q/・, i-
It refers to the Jru filter (see fR: Release! 1'If'
Tomari Gazette, 1978-E712 Tenme/Yon Filter). Since it is A55, in order to reduce the spectrum around this frequency as much as possible (that is, to prevent folded spectrum from occurring and appearing within the desired band), press the button. This means that consideration should be given to the frequency characteristics so as to provide an attenuation region (zero point) at 7n-4.

I jf one work, now H1, i-! 'Yu (=fn) 2:
. O) 1.4. Air 1. -7 Push/Go 1: It does not affect the area, and the sample frequency can be reduced. Repeat this operation (=J times).

In FIG. 6, τ5. τ2. τ3. ... τ1
, 1- that is, T1 (1-1 to 11) is the ''th unit delay time, which is the reciprocal of the sample frequency (= 1 /
, 1"8.).

Now, if we calculate the response of 1(...) for the input x, (m), the following difference equation will be derived.

y(m) = n1X+ (1ll-T4)-4 heat)
1XH (1 in Ill-2) ten, ('HXl(m -3γ
1) (C: 1 to 11))・i (n+) I “1(”
') respectively Z[, -(m):] -Y,
(7,) , 7. (x, (IIT) )・-X,
If (Z) and 1-, )′1(Z), =”+Xt(Z)Z
-rll-1) 1Xl (Z) Z-271-I-CHX
+(Z) Z' −Z−τ1xj(Z)(,1,+1), Z angle 10c゛1Z
1) (where Z −= t: 'ω) Therefore, the frequency response 11. (Z) (transfer function) is now +11”-1
,+"j・2.c,=,I and the deviation is 11, (Z)-
Z-TI (1+2Z Ifz +)-= yJ-T1
< t + Z-rl)2Z-T17COS (OτH
−l−j sinωτ1 from l 11+(Z) l−2
(1-1-cos, ωτ, ) (i=t ~++)
This Jr wave number '111 property is 1,4! , vc as shown in Figure 8
cosin (4 curves) Provide an attenuation region (zero point) at the point J/2 times the IC frequency. Repeat this operation several times,
Reduce sample frequency. In this case, the total transmission number i II (input) is 1, t/ (1+ Z-' ) 2 1 (Z-'' is just a delay -[i is added to λ).
), General Te (finally, + Z-2T1) Ninon (21" heat) I Z-T1+
'l-IZ')1-I+.

FIG. 7 shows a geometrical circuit t114 of the digital low-frequency iJf wave circuit, that is, the digital filter.

τ means the unit delay amount, τ-1/L'8 Reciprocal of the Zamplinter frequency (C equals. Now, the output for the input xH(+n)) . When finding the response of (m), the following difference equation is obtained. or η′i or j.

The Z transformations of xH(n+), ); (m) and yl(m) are respectively Z (x, (m))=,
), Z[)・1'(m)) = Y'+(Z)
, ZCyH(+n)) -YH(Z), if we eliminate yi(z) in the above equation, we get X+(Z) -Y;(Z) (1; If Z -l]
+ Z, )Y, (7,)-・Yi(Z) (c, -l-
+1IZ-+Z, ), the frequency response is +1. (Z) (transfer function) is now a total of 6 transfer functions 11 (Z) is (1; l ~ 11) (Z- (U, j (II), ・IH, bl, (+ , d, By selecting (1), a digital filter of (76) is formed (11).

The hanging 0 diagram is the ten-no-simi 1-in filter turn 11'r't.
For example, it is a concrete example of 4'i7+ formation in the I'+ fi diagram, and the human input signal is horn-shaped.
tii + ii] rireshiru Omata&'; 15 to CDI
,1lIIIll! If it corresponds to ゝ0'i'+jO+, the decimation filter 11g1t(is at most (1)/
I (all done manually), minimum 0/1 (all -
1) The oil must be expressed as 7 (, 9) of 2, and the left inviso must be 4. is.l)-t' /
t' is a J] type flip-flop, and each output has (
(l- multiplies 1x and 2x coefficients), respectively, 1110 shirt L, te force 14-: then tongue (song). In Figure 9, the human power data is logic 0, low level, Logic 1 is the quotient level, and regarding the output ■, IICI
X[exist]-=-1-/I Cf)lOt,l')
.

II■--4 (ゝuoo';2's complement), regarding the output ■, ++1; IX inside') -4-16 (ゝ01t) +1
00' ), min Q3)-kawa (5(ゝ) 1.
t,)Ot)l)';2's complement), and ``5(i-+
)-2"s+ (+-1~11) (l・'ai is i
−? I'i 1.1's Zanno° ring J,', 1 wave number).

I] λ10 diagram further shows the It of the decimation filter
In order to simplify the ili, its functional circuit configuration is shown. As shown in Fig. 6, the frequency response II (Z) of the decimation filter is II (1-z-Ti)2! -1, then 2・τ1-1”-τ1 (7.), so if −τ and 1, then 1 11(Z) =, l/ (1+Z)1・-1 −(x+2y, −+y, )(1-1-2Z +Z
>, II"l, T-2n, r ...... (1-1-2Z +"/, )
If these are expanded, there will be 2n digits and 2n digits, and from Po to IJ, 211112), P will be the turning point (211,, I), and there will be 211 digits on the left and right pairs of 4'J5. Therefore, (2"'-3) elements with a unit delay of 11 (τ (= τ1) are prepared, and each 1"4 force has a coefficient P.~L'tznll-0 and Yonago9, and all of them Add this to 211・τ
If it is done and output within the time, the answer will be equivalent to the answer marked in FIG. 6.

gll;++ Figure 21 shows the decimation filter l? ! Functional 1rjl path associated with 'i simplification (
In order to further simplify the 11IN configuration, we have taken the 14IN configuration (high-performance circuit) by 1.As shown in Figure 10, we have added a delay element. (2°1l-1) It is a difficult hardware task to heat each output and take out each output.The operation of adding a coefficient to each output and adding
11.It must be done within 7 hours, but as shown in Figure 11, 2n delay elements are prepared, and ■ in the input diagram and ■ in the output diagram are 2 n + 1- · Figure 10. It is compatible with Okel Z-(2n", Z-(2)K. Now, install the switch 11g
If you move it every 72 hours and select ■signal■signal and take it out in ◎, the output of ■ will be ・Every 72 hours, Z-3 "-"
Z-(2"-2) -(2""'-3) -(2
”-3), , , , , and so on, the current, Z, and Z are sequentially changed. Because every 7 hours, the delay element
The information is sent out to outputs ■, ■, and output. And these can be completed within 2n·τ time.

Figure 12 shows the output of switch 1) jX in Figure 8Eu.
is tracked over time. II; C-CK is the clock of the switch, select ■ when the logic is O', logic X1
Indicates that / is selected. This output is multiplied by a coefficient P and added to the register using the assist clock.

FIG. 13 is a circuit example of the most efficient decimation filter, and is a concrete example of FIG. 11.

The input signal is latched by JJ-F/J=', and each output is outputted by the switch according to the relationship shown in FIG. 12.

This value is 1 or 0, so 13. Itabu X□ /○■
, if logic 1' corresponds to
((Extract the month\1 by ::'j6, avoid inverting or non-inverting the first occurrence, and add the adder registers υ sequentially.) 12
If the data is latched with the clock of 01 river ゛-("1() shown in the figure, it is equivalent to Fig. 6.
.

Using the following 1 J, uni, and denominator filters, a) From Kotoriko, the JJ form is converted to 1"'St\'f
The f number is converted to 1-Si, and the aftertone 2::ka..., i) is output by digital Shinkyu processing, so (
+) b).

1゛ノ, 11 conditions 1-ta, 1-uni, ;i';I's actual IL example is 11, square, 1. 1, 'S1\I, -11, which was pointed to by 11, is realized with a total of 107'' digital circuit kl, 1: te, which includes +tYi technology and provides more stable υ motion 1. The point is 'C'. In addition, A/1] converter Jlu・same(lko1・'S 1
(IF4-Murun's 1νj 1 round), C Kotokade・Kirunote 51・S1 1iC, the advantage of having the circuit configuration that was mentioned, C, B) 1. (Effects of the invention) The present invention can all be realized using digital circuits, so
I'S K with several ICs along with a 'S K modulator
It is possible to make a modem, and furthermore, due to high integration, it is possible to realize a modem with one IC.
・Since it has several advantages, it is relatively inexpensive and can be used for any data transmission (ψ11 end) equipment (6).

[Brief explanation of drawings]

What about figure 1? Mainly based on analog circuits from iC [・
``Circuit configuration of S1\ demodulator, Figure 2 shows the circuit configuration of 1 S1 demodulator based on digital signal processing that has been proposed since 1999. Figure 3 shows the circuit configuration of S1 demodulator, which is the first embodiment of the present invention. )ru l'
Circuit configuration of S kq adjuster, Figure 1 (A) ~ ((
i) Hari! ;':In the circuit configuration of NI-I, the outline of each input/output waveform is shown, and the song from Figure 5 (1) to (the song explains and explains the operating principle of the decimation filter in the frequency domain) Figures 6 and 7 show specific circuit configuration examples of a signal filter and a digital low-frequency Jl wave circuit, respectively, and Figure 8 shows the transfer function of the device in Figure 6, and Figure 9. is a specific circuit example of a ten-day filter, No. 10
Figure 11 shows the simplification of the decimation filter.
The figure shows another simplification of the decimation filter, FIG. 12 shows the output of the switch EX in FIG. 11, and FIG.
The figure shows another example of the configuration of the decimation filter. τ1・・・・・・・・・1st unit delay time 11♀Kojijintoki Electric Industry Co., Ltd.Nippon Telegraph and Telephone Public Corporation'11Numa'1out1jλr1Representative Patent Attorney Megumi Yamamoto -

Claims (1)

[Claims] t”S frequency modulated by a digital modulation signal
A K signal demodulator includes (1) a circuit that limits the amplitude of the input FSK signal and converts it into a square wave, and (2) a digital P signal that converts its output into a pulse width modulated signal.
(3) Data latching is performed on the output at a frequency that is more than twice the fundamental frequency component, and the latched data is designed to have a small attenuation pole of 1fC in the region of 1, so that the latched data does not affect the signal band. Decimation is a decimation method that reduces the sampling frequency while preserving the information path of the input signal by performing addition p- and data latching the result at a frequency within the attenuation range at least once. A filter, (11) a digital low-frequency tear circuit connected to its output, and (5) linear interpolation of the output of the f-wave circuit, and a demodulated output by comparing the interpolated output with a predetermined threshold. and means for providing l or 0.