JPS5962222A - Digital signal input circuit - Google Patents

Abstract

PURPOSE:To attain high speed and low power consumption by using alternately plural amplifier circuits and resetting the state in an amplifier circuit to a state possible for high speed operation during the period not in use. CONSTITUTION:Since a transistor (TR) Q9 turns off and a TRQ10 turns on when a voltage of signal phiD1 is a low voltage in a differential amplifier circuit 1-1, output signal voltages O11, O12 are equal with each other and set to a voltage close to a DC voltage VDD. When the voltage of the signal phiD1 is high, the TRQ10 turns off and the TRQ9 turns on, a differential amplifier circuit is formed. Since the output voltage signals O11, O12 are initial-set equally, it is not required to cancel the preceding output signal, and the time required to confirm the output signals O11, O12 is halved in comparison with conventional circuits. Differential amplifier circuits 1-2-1-n except the differential amplifier circuit 1-1 are operated sequentially in the same way.

Description

Detailed Description of the Invention Technical Field of the Invention The present invention relates to a digital signal that asynchronously amplifies a relatively weak signal applied from outside an integrated circuit to the same amplitude as a signal used inside the integrated circuit. This relates to input circuits.

Technology Background With the rapid progress of digital signal technology and VLSI technology, various high-speed logic circuits and asynchronous MOS memo! J
Signal input circuits such as LSI and MO8 logic LSI are being studied, but it is desired to realize a high-speed, low-power, low-power digital signal input circuit. The present invention mainly applies to asynchronous A40S memory LSI and MO8 logic LS.
I signal input circuit (applied to both. Conventionally, a CMOS inverter circuit or a differential amplifier circuit has been used, but in the case of the former, it is necessary to supply a relatively large amplitude signal from outside the chip. However, in the latter case, power consumption increases.

Prior Art and Problems Conventionally, this type of digital signal input circuit, for example,
As shown in the figure, P-channel MO8) transistors Q, .
Q3<hereinafter referred to as Q+ and Qs. ) and an N-channel transistor Q2. Q, <hereinafter written as Q2 * Q4. ), Q and Q2 constitute a first CMOS inverter, Q and Q4 constitute a second CMOS inverter, and an input signal is provided from outside the integrated circuit as an input to the first CMOS inverter. I is supplied, and the output of the first CMOS inverter is given as the first output signal OL to other circuit blocks inside the integrated circuit (=, at the same time as the input of the second CMOS inverter The output of the second CMOS inverter is given as a second output signal 02 to other circuit blocks inside the integrated circuit.This type of conventional digital signal input circuit has low power consumption and However, the amplitude of the input signal I is different from the DC voltage VI)D and DC'
The difference between the voltages Vss (this difference is the difference between the first and second output signals 0
If the amplitude is, for example, about 1/10 of Such a small signal cannot be amplified, which makes it difficult to do so.

A differential amplifier circuit shown in FIG. 2 is used as a circuit for inputting the above-mentioned digital signal with minute amplitude. As shown in FIG. 2, this second conventional digital signal input circuit includes P-channel transistors Qy, Qs.
C or lower Q5. It is written as Qe. ) and N-channel transistor Qf, Q8. Q, <hereinafter written as Q7sQ, , Q. ), the drains of Q, , Q6 are supplied with a DC voltage VDIJ, the gates are supplied with a DC m voltage Vss, and the sources of Q, , G, l, and Q
The drains of Q9 are connected to each other, the source of Q9 is supplied with a DC voltage VSS, the gate of Q7 is supplied with an input signal I applied from outside the integrated circuit,
The gate of Q8 is given a voltage VR equal to the logic threshold of the input signal I (hereinafter referred to as the 9 reference voltage of the input signal I), the gate of Qg is given an appropriate DC voltage VC, and the source of Q The drains of Q6 and Q7 are connected to each other, and the first output signal 01 is taken out from the connection point.
The source of 08 and the drain of 08 are connected to each other, and the second output signal 02 is taken out from the connection point. Since the DC' voltage VSS is a low voltage compared to the DC voltage Va and the reference voltage 9 DC voltage VDD, the input signal I t7)' [ts: Voltage V (1) output signal OH, O,, Noah 7; .Assume that the input signal Y Ichikawa V(1) is set to a higher voltage than the reference voltage VR from a certain point t1 to nII, and is set to a lower voltage than the reference voltage vn after the time t1.In this circuit, Q5, Qa
operates as a load resistance, so before time t1, the output signal 'voltage V(O+) is a low voltage, and the output signal '
Voltage V(02) is set to high' voltage.

When the input signal l changes at time tl, the output signal 'voltage I' (02) begins to change to a low voltage, and the output signal voltage V (Ol) begins to change to a high voltage (two voltages), as shown in Figure 6. , the output signal voltages V(02) and V(0+
) are set to low voltage and high voltage, respectively. In this way, a digital signal input circuit using a differential amplifier circuit has input 4? When the number J changes, it is necessary to change to a new state while canceling the output signal A that has been output up to that point, and for this reason, a relatively long operation +1-IF period is required. In addition, in order to make such a circuit operate at two speeds, another differential amplifier circuit that inputs the output of the differential amplifier circuit described above is added, and the output signal of the first stage differential amplifier circuit is output with a relatively small amplitude. Conventionally, a method has been adopted in which the output signal of the first stage that was previously output is easily canceled out.However, this method has the disadvantage of increasing power consumption during operation.

In other words, with conventional technology, it has not been possible to amplify minute voltages at high speed with low power consumption.

OBJECTS OF THE INVENTION In order to solve the drawbacks of the prior art, the present invention uses a plurality of amplifier circuits alternately (binary), and performs high-speed processing of the state in the amplifier circuit during periods of use. The purpose is to realize a digital signal input circuit that can input minute signals at high speed, with low power consumption, and with little power.

Examples of the invention FIG. 4 shows a circuit diagram of the first embodiment of the present invention.

The same symbols as in FIG. 2 indicate the same parts. In this embodiment, n differential amplification circuits @ 1-1, 1-2, -., 1-n,
Oscillation circuit 2.27L N-channel transistors Qμf
11゜Qpt+2+ Qu2+ + QA122 +・
・°r QArty, (%?Mn, 2 (hereinafter referred to as QM
+++ QAI+2 + Qar2+ + Qu2
It is written as 2+ −+ Qhtn+ + Qun2. ). The differential amplifier circuit 1-1 includes a P-channel transistor Q+o (hereinafter referred to as QI) in the differential amplifier circuit shown in FIG.
It is written as o. ) is added, and 'I'IO
The source of Qlo is connected to the source of Q5 and the drain of Qf, and the output signal o11 is taken out from this connection node.The drain of Qlo is connected to the source of Qo and the drain of Q8, and the output signal o11 is taken out from this connection node. Signal”!2
It is configured to take out the '1' IO gate and Q
This circuit is the same as the conventional digital signal input circuit shown in FIG. 2, except that the gate of oscillation circuit 2 is connected to this connection node, and the signal φ711 generated by the oscillation circuit 2 is supplied to this connection node. Other differential amplifier circuits such as 1-2, 1-6°, etc.
-1, but instead of the signal φni supplied from the oscillation circuit 2, the signal φni is supplied to the differential amplifier circuit 1-i.
is supplied and the output (t'1 is Oi
, , The difference is that it is Oi2. (Here t is 2,3
．． 4. ...I+, ) Output signal of each differential amplifier circuit OI+ + 012 r 021 + 022 +...
・.

On l t o7L 2 is Qptl, t Qpt+2
+ QArt+ + Qt, 22+ ”' + Qat
Output signal O! through n+ +Qun2! Or connect h to 02
'Qhrn + Qui2t Qpt2+
t '1'J122 +..., + QMnl + Qh
tn2 is a signal φn1.tn2 generated by the oscillation circuit 2. φM2.
..., φA(n is supplied to the gate, and the signal φi
h'ti is configured such that when t i is a high voltage, the output signal Oi is connected as the output signal OL, and the 1'' i power signal Oi2 is connected as the output signal 02. (Here t is 1.
2, 3. ..., n. )φD.

, φD2 +..., φD are signals that change with a period T, and the signal φrm is different from the signal φD+,
i is a signal whose phase is delayed by time ts with respect to the signal φni+1+2. (Here 2 is 1; 2.3.・
...nj. ) signal φ7) Itφ7) 2 +...
・φInn becomes a high voltage (2) and becomes a low voltage after time 1, +15 has elapsed. Here, 1A is the voltage of the differential amplifier circuit 1-1.
1-2. ..., 1-n operation time. tP=7'
-(tA+ts), time 1. A low voltage period continues during this period. - As an example, FIG. 5 shows the time variation of the voltage in the case of the signal φ7)IsφJ)2+φD3. Signal φJfl,
φM2 +...φun are signals φDl and φ71, respectively.
2. . . . is a signal that becomes a high voltage with a delay of the operating time tA of each differential amplifier circuit and simultaneously becomes a low voltage.

In explaining the operation of the embodiment @1, the operation of the differential amplifier circuit included therein will first be explained by taking the differential amplifier circuit 1-1 as an example. When the vehicle pressure V (φ711) of the signal φ month is a low voltage, Q9 is in a non-conducting state and QIO is in a conducting state, so the output signal voltage V (O, □) and L/'(0
12) is equal to DC voltage VD7) or it (=near FI
When the heavy pressure V (φDt) is set to a high voltage, QIo becomes non-conductive, and Qo becomes conductive.
state, and a differential amplifier circuit similar to that shown in Fig. 2 is formed, but since the output signal voltages V(QH) and V(012) are initially set to be equal, it is necessary to cancel the previous output signal. No output signal 0. The time required to determine l, 0.2 is approximately 1/2 that of the case shown in FIG. Differential amplifier circuits other than the differential amplifier circuit 1-1 also sequentially perform similar operations with a time ts shift. This first embodiment is designed so that the operating time (2) of each differential amplifier circuit is equal, and when this operating time is completed, the operating time of each differential amplifier circuit is equal. Output signals OIl, O1□,・
. . , 0rL1, 0TL2 are the output signals 0. ．． Cbtn*QM as 02
I2 v...

It is conveyed through QMnl + QMn2. By performing the above-described operation, in the case of this embodiment, the human input signal I changes and the output signal 0. ．． The time it takes for 02 to change is tA+t5 in the worst case, and it is clear that the circuit operates faster than the conventional circuit. In the first embodiment, the number of differential amplifier circuits may be any number greater than or equal to 2. 1- The oscillation circuit 2 of the first embodiment receives the signal φD1. φ/12. ..., φ/In, φAI++φ
This is a circuit that sequentially generates M2+..., φprn, and uses an oscillation circuit such as a Sung oscillator to generate l!i'l.
It can be arranged as a funeral. Furthermore, when a plurality of digital signal input circuits are mounted on one integrated circuit, the oscillation circuit 2 does not need to be provided in each digital signal input circuit, and may be shared by the plurality of digital signal input circuits. 1st above
Example (2) Output signal OL.

The node for extracting 02 and the output node of each differential amplifier circuit are connected with N-channel transistors, but they may also be connected with P-channel transistors, or both N-channel transistors and P-channel transistors may be used, so-called 0MO8). It may also be used as a transfer gate. The second embodiment of the present invention is based on Q)4+1 and QhtI of the first embodiment.
Replace the connection circuit configured with t with the circuit shown in Figure 6,
Other CJtit, Qhtit (' = 2, 3,
. . . n) is also constructed by replacing it with a similar circuit. In this embodiment, for example, QM I I +
I-P chattle transistor QA instead of QM I2
f +' * Q'kr 3 + 9M number, Q shift,
(1 tB (hereinafter Q111 g Qj/3 * Q'
It is written as M4 r QM'r + QJ18. ), and an N-channel transistor Q'Mt+Q'ua +
Qpt6+ Q'bto * QJ/l. (hereinafter QM2
g QJ/! l v Q'M8 gQN9, Qxrt
It is written as o. ) is provided, and Q'ht + t Q
pt 2 &ma DC voltages VDD and VSS are used as power supplies,
It constitutes an inverter whose input is signal φA11,
Its output 1 is supplied to the gates of QU3 and Q'kI7, and Qat6 and Qxtx.

The signal φJfl is applied to the gate of , the output signal O1 of the gate C of Q'y
yo gate (the two are supplied with the 1 old force signal O1l, respectively, and Qyq'* has bt< v Q'u* * Q'h
rs is connected in series, its both ends (the second is DC voltage Vl)
I) and Vss are supplied, and the output signal OL is taken out from the connection node force of Q'M4 and Qua.

Is the lJA chi language number 02 also the same as the output signal 01? e
Qua y QM 9 + Q Karasu.

Let's take it out from the midpoint of the series connection of (2 and ν).

When signal φj/I is high voltage, QJ16 I Q:+
to * Q; ts * (Since Jt7 is all conductive, one inverter is formed by QJ114 + Q嘗5, and another inverter is formed by Q'hts and Q-0, and the output An output signal 01 is generated as an inverted signal of the signal O1t, and an output signal 02 is generated as an inverted signal of the output signal 011.On the other hand, when the signal φM1 is a low voltage, the above inno(-) is not formed, and each The output end of is in a bloating state.

Output signal o of differential amplifier circuits other than differential amplifier circuit 1-1,
, , o, , o8. , o3. ,・,,o
rL, . ...
, φJHL output signal 0. ．．
The signal can be extracted as 02.

In the first and second embodiments described above, a differential amplifier circuit equipped with a P-channel transistor as a load was used.
In short, the circuit may be configured to synchronously dwarf and amplify the input signal according to the signal generated from the oscillation circuit 2, and it is possible to use a so-called latch type circuit. Conventionally, this type of digital signal input circuit needs to constantly output an output signal corresponding to an input signal, and a latch type circuit cannot be used. In the case of the digital signal input circuit of the present invention, a plurality of amplifier circuits are sequentially operated and their outputs are combined, so that a latch type circuit can be used as the differential amplifier circuit. The latch type circuit is
It is known that this differential amplifier circuit consumes less power and is faster than the differential amplifier circuit shown in FIG. Figure 71, Figure 8, Figure 9
The figure shows an example of this type of latch type circuit, and the same symbols as in FIG. 4 indicate the same parts. The differential amplifier circuit in FIG. 7 is replaced by the differential amplifier circuit 1-1.1-2 in FIG. . . , 1-n is replaced with the third embodiment of the present invention. In the differential amplifier circuit shown in FIG. 7, the input signal I is applied to the gate of Q6, the reference voltage T'JI is applied to the gate of Q5, the gate of Qγ is connected to the drain of Q8, and the gate of Q6 is connected to the drain of Q8.
The configuration is the same as that of the differential amplifier circuit 1''1.1-2... in FIG. 4, except that the gate of , and the drain of Q'r are connected. In this configuration, the output signal 012゜011 is Q
7. Because it is fed back to the Q8 gate,
It has a data latch effect and can operate at high speed.
．． A digital signal input circuit with higher performance than the second embodiment can be provided. Further, the differential amplifier circuit may be configured as shown in FIG. In this case, Qa, Q
A signal φDj (i=1.2...,n) is also applied to the gate of a.
is supplied, input signal I and reference voltage V
R represents the N-channel transistor Q11 and transistor 2 (hereinafter 'I') installed between Q7 and Qa and the output signal extraction node.
It is written as 'll*QI2. ) is configured such that the signal φni is supplied from the gate of
! + + (+'a + Qro becomes conductive, precharges the output signal extraction node, and when signal φni becomes high voltage, Q becomes conductive, input signal I (7)
? I3: The output voltage is quickly output as output signals Oi, Oi, according to the magnitude of the voltage and the reference voltage VR. The differential amplification circuit of FIG. 9 includes P-channel transistors QI3 + Q14 + in the differential amplification circuit of FIG.
It is configured by adding Q141 (hereinafter referred to as Qls l Qr4 + 'i' + s), Q, , , Q,
, whose gates and drains are connected to each other, and whose connection node is connected to the output signal extraction node, 'l'ls t
DC voltage VDI is applied to the source of Q14 via Qr6)
is supplied, and C,! A signal φni is applied to the gate of +a.
The configuration is such that a signal dlni of the opposite logic is supplied. In the differential amplifier circuits shown in FIGS. 8 and 9, there is no DC-like current path between the voltage V7) D supply node and the DC voltage Vss supply node, resulting in low power consumption and high-speed operation. It is possible.

In the above embodiment (2), the output signal of each differential amplifier circuit is selectively outputted as the output signal 0..02 of the digital signal input circuit by a switch circuit controlled by the oscillation circuit 2. .r(xi
In an embodiment of the present invention, QMII t of the first embodiment
QN+2 + '...t Qhtnl, Qptn2
Instead of diodes D, , , D! 2. ,,,
, Dn, , 1), ,2, and 45 (,1
Signal φM1. from 1V circuit 2. φM2. ..., φpt
The output node of No. 1 0°, 02 (P channel transistor Qt + as a resistor for the two
Qr2 (hereinafter referred to as '2L11 Qr, 2). In the case of this embodiment, only when the output signal 0 is a low voltage and the output signal Q is 1j-jl''111 voltage (t=1.2..., n,, no 1.2) Current flows through the diode Di, and no signal is transmitted.
, only when one of the output signals of the differential amplifier circuit is determined to be the low 71L voltage, that signal becomes the output signal 0. ．． 02, so the first. Sheath, 2. As in the second embodiment, Shinyumi φ
There is an advantage that the moon, φ+12+...φun are not required. It goes without saying that the diode of the fourth embodiment may be replaced with a transistor whose gate and drain are connected to the phase tr, which has an equivalent circuit operation, as is generally well known.

Also, the output signal Oth e 021 + 031 v...,
The logical product of OTL and OTL is output as an output signal O1, and output signals 0, 2, 02 . .

03□,...,0. It goes without saying that an embodiment of the present invention may also include a means for outputting the logical product of L2 as the output signal 02.

In the above embodiment, even if the N-channel transistor is replaced with a P-channel transistor, and the P-channel transistor is replaced with an N-channel transistor, and the DC voltage Vnn is compared with the DC voltage Vs~C and becomes a lower voltage, the polarity of the voltage simply changes. It is obvious that the digital signal input circuit of the present invention can be constructed using the following, and this is an example included within the scope of the present invention.

As explained above, although the present invention amplifies minute amplitude digital signals asynchronously without depending on the external metro signal or -b signal, the internal differential amplifier circuit operates sequentially and synchronously. Since the output signals can be synthesized, a high speed, low power consumption digital signal input circuit can be realized.

The present invention is mainly used as a signal input circuit for asynchronous MOS memory LSIs and Alas logic LSIs that aim for high-speed operation, and converts signals such as TTL and CL input from outside the chip to A40S level 4n used internally. It is highly effective when applied to circuits that

[Brief explanation of drawings]

1 and 2 are circuit diagrams of a conventional digital signal input circuit, FIG. 6 is an operation waveform diagram of the conventional digital signal input circuit of FIG. 2, and FIG. 4 is a diagram of the conventional digital signal input circuit of the first embodiment of the present invention. circuit diagram,
Figure m5 is an operating waveform diagram of the first embodiment of the present invention, Figure 6 is a partial circuit diagram of the second embodiment of the present invention, and Figure 7 is used for the fifth embodiment of the present invention. Circuit diagram of amplifier circuit, No. 8
9 is a circuit diagram of another embodiment of the present invention (a binary amplifier circuit), and FIG. 10 is a circuit diagram of a fourth embodiment of the present invention. 1-1.1-2 ...1-n...differential amplifier circuit, 2
...Oscillation circuit, (Jl, Qs + Qs, Q
6t Q'M1. Qus + Q'at+ + Qx
txQ′J+swQ+. + '1s I '14 t
Qr6 + Qr, I+ Qr, t...P-channel transistor, 'l'2 + Q, r Q7 + Q8
r Q* + Q,, f1+ + Qpt12+...
. Qprn+ + to l! Al71.2 + Q)42
+ QSt* + G); t. , Qsto r Q2t
, or Qllll'Q+2...N channel transistor, I...Input signal, "l+02...Output signal, VR...Reference voltage, Vs,, ,VDD
, VG...1 [current'' voltage, φM++φM7....φ
M) L, φD+ +φD2. ...φnjL + "'
Signal, D++ + DI2 + ”'Dn, + + D
rt2"' diode, φnt, φD... trust'ri
(t = 1.2.-・-, tL) 1 person patented
Japan' City Telephone Public Corporation Agent Patent Attorney Tama G, 1 Kugobe (6 others) Figure 1 Figure 2 Whistle Figure 3 Karima

Claims (2)

[Claims] (1) Synchronize the amplification of an externally applied digital signal with a signal other than that signal! ``<In a continuous input circuit, a plurality of amplifier circuits to which the digital signal is input, a connection circuit that connects each of the amplifier circuits to the output terminal of the input circuit, and a state within the amplifier circuit is reset. a reset circuit, the amplifier circuit, a connection circuit,
The circuit is equipped with a six-mark gyroscope control circuit for controlling the operation of each circuit of the reset circuit, and the plurality of amplifying circuits perform an amplifying operation after being sequentially reset, and after the amplifying operation or during the amplifying operation (two times). A digital signal input circuit characterized in that the output of the amplifier circuit is outputted to the output terminal by the connection circuit. (2) The connection circuit comprises a diode connected between the output terminal of the amplifier circuit and the output terminal of the digital signal input circuit, or a field effect transistor whose gate and source are interconnected. The digital signal input circuit according to range 1.