JPS5961957A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent a semiconductor memory device from an erroneous write by a method wherein ''O'' write action is performed by making a parasitic bi- polar tansistor to ON. CONSTITUTION:At the sequence of ''O'' write action, a word line voltage (VWLS) drops to an electric power source voltage (VSS) from an electric power source voltage (VCC) at time tO, and a write line voltage (VWTL) is dropped to VSS from a voltage VM (=1/2VCC) at time t1 in succession. Then the word line is cut off from the electric power source voltage VSS once at a peripheral circuit other than the memory cell, and after then, when the voltage of the word line is forced down to VSS or less according to a capacitor, an N<-> type layer becomes also to VSS. Then, when the voltage of the write gate WTL is dropped to VSS, the voltage of a P<-> type surface layer is dropped also. At this case, because the punch through withstand voltage is sufficiently high, at least a part of the N<-> type layer remains to VSS at it is, the P<-> type surface layer and a P type substrate are isolated according to built-in potential phiB, and no implantation of holes is generated. Then the voltage of the word line WLS is made to VSS. Namely, when the voltage of the N<-> type layer is made to VSS or less according to the word line WLS to eliminate the barrier of the N<-> type layer, and to implant holes to the P<-> type surface layer from the P type substrate SUB, a ''O'' write to a selected cell is attained.

Description

Detailed Description of the Invention (1) Technical Field of the Invention The present invention relates to a tapered isolated RAM (Tape
r l5olated Random AccessSM
memory), and in particular, how to write the data.

(2) Technical Background Tapered isolated (hereinafter simply referred to as TI) memory cells have a one-transistor, one-capacitor format, but actually do not have a capacitor with electrodes facing each other like traditional one-transistor cells. For example, ■1979 IEFJ In
international 5old-8tate C
1rcuits Conference:l5SCC7
9/WEDNESDAY, FEBRUARY 14,
1979/GRANDBALLROOM/11:45
A, M, , P, 22, 23 or ■
It is known in U.S. Patent J, 4,291,391. This TI memory cell has a large j (U (
Since it does not require a jt capacitor, it is expected to be used as a highly integrated and large capacity memory. However, sufficient studies have not yet been conducted, and there are many points that need to be improved before commercialization. The present invention also refers to an improved proposal.

(3) Prior Art and Problems FIG. 1 is a circuit diagram showing a part of the Tl-RAM. In this figure, shoes are word lines, BL are bit lines, and a TI memory cell TC is connected to each intersection of these lines. This memory configuration itself is no different from general memory. This memory cell TC is a transistor, and the dirt is filled with rocks #i! WTL is connected.

FIG. 2A is an enlarged plan view showing the specific structure of the portion surrounded by the dotted line in FIG. 1. Note that the same constituent elements are indicated with the same reference symbols throughout all the drawings. In FIG. 2A, the bit line BL is made of N+ type diffusion j*, the word line WL is made of, for example, aluminum wiring, and the write line WTL is made of, for example, polysilicon. A transistor forming a memory cell TC is formed at the intersection of the word line WL and the bit line BL, and its source (N+) is connected to the contact window cw.
It is connected to word line WL via.

Figure 2B is a cross-sectional view of 2B-2B in Figure 2A, and Figure 2C.
The figure is a 2C-20 sectional view in FIG. 2A. 2nd B
In the figure, S and D are the source and drain of the transistor, and the N+ type drain D is the pit MB.
It is formed integrally with L.

Directly below the dirt of this transistor (same as the write line WTL), a thin P-type surface layer P- is provided via an insulating layer Is.
There is a thin N-type intermediate layer N- directly below it. This intermediate layer N- is surrounded by the surface layer P- and the substrate P'' to form a so-called junction FET. All the above-mentioned components are formed in or above the P-type semiconductor substrate SUB. In Figure 2C, CC is P
A channel-cut region of the shape separating the intermediate layer N- from the others.

Data "'1#" in TI memory cell TC.

The storage of '0# is done in the surface layer P-. surface layer P
- If there is a hole in this memory cell TC
The retained data is 10", and if there is no hole, it is "1".
It is. '1# of data like this.

“0” is maintained because the surface layer P− is completely surrounded by the fox or N”-type diffusion layers (S, D, N−) and the insulating layer IS. Depending on the presence or absence of holes in the layer P-, the value of the current flowing from the drain D to the source S in the intermediate layer N- of the junction FET differs (the value of the current flowing from the drain D to the source S is high for data @0'', and high for data ``1#''). Data is read here.This is a general operation at the time of reading, including the time of writing, the word mWL,
Table 1 below shows voltage condition statements ld and electrical conditions for each part of the bit line BL and write line wTL.

Table 1 (However, vcc, vss are power supply voltage, pressure, H2 &amp; high impedance, vM is 2 V (indicates an IC).) Figure 3 shows the series of operations of reading, 11"1-writing, and "0" writing. This is a waveform diagram that is easy to understand, and corresponds to the diagrammatic representation of Table 1t above.
2) The column is related to the write line WTL, R is read, W″1″ is writing data @1#, W″′0# is including 1 of data “′0”, and other periods are This is a period in which the word line is not selected (corresponding to "hold" in Table 1 above).

Since the present invention mainly refers to the 1-convolution method in TI memory, we will provide a little more information about this convolution. In the case of @1'' write, the word line WL is set to ``ss'' to select it first, and then the 1''+ line WTL is set to Vcc to release holes from the surface layer P- (holes are released from the data ``'1''). #Write) because the substrate SUB is in vs8. In this case, the surface layer P- is P type, the middle layer N-
is N-type, and the substrate SUB is P-type (see Figure 2B).
, forming a parasitic pi-I-latrannosta of PNP between them. That is, the surface layer P- is a collector, the intermediate layer N- is a paste, and the substrate SUB is an emitter. In this bipolar transistor, in the state of "1# write, the pace is VBBC because the current word) ljjWL (that is, the source S) is VB8), the emitter is V88, and the collector (surface layer P-) is V.C. (due to capacitor coupling with write line WTL rising to vcc), the collector paste junction is forward biased and turned on.

This on-off hole escapes from the surface layer P- (collector) to the intermediate layer N''- (pace). There is no problem with this @1# rock inclusion.

However, writing '0' has a problem. Writing '0' means injecting holes into the surface layer P- (as described above).
. Then, as shown in Table 1 and FIG. 3, the write line WTL is lowered to VB8. That is, this is done by lowering the potential of the surface layer P- which couples with the dovetail line WTL and the capacitor 7+1-. At this time, the parasitic bipolar transistor has A? punch through
h through) occurs, and this punch-through causes holes to be injected into the surface layer Pl collector). In general, the Nokunchi-through effect means that as the pressure applied in the reverse direction of the collector paste increases, the width of the space charge layer at the collector junction expands into the paste region, and when it finally reaches the emitter junction, the emitter and collector become short-circuited. It is well known that The collector-emitter voltage that causes this punch-through is called the punch-through voltage, and it is known that its value varies greatly depending on manufacturing conditions. Considering these variations,
Uniform writing cannot be expected. Finally, when the no-kunchi through voltage is high and fluctuates, it becomes difficult to write "0" and "1" into even the selected TI memory cell. On the other hand, when the through voltage is low and varies, "O#■" is applied not only to the selected TI memory cell but also to unselected TI memory cells (details will be explained later). This is a technical problem.

(4) Purpose of the Invention Therefore, in view of the above-mentioned problems, the purpose of the present invention is to solve the problem.

(5) Structure of the Invention In order to achieve the above object, the present invention is characterized in that the 0" write operation is performed by turning on the parasitic bipolar transistor instead of using the iP pinch-through in the parasitic bipolar transistor. The ON condition at this time is that the write line is V.
B2, the board is vl! 8. Intermediate JPN- is "ss-." V2O- means below Vss.

(6) Embodiment of the Invention FIG. 4A is a schematic diagram showing a general layout in which the central portion of FIG. 2B is cut vertically and placed horizontally. In this figure, C, B, and E represent the parasitic pie 7? - Indicates the collector, pace and emitter of each transistor. The meanings of the other symbols have already been explained.

In addition, FIG. 4B is a potential diagram showing the potential φHeV(
electron delt). Also, since we are dealing with holes here, we will use a valence bant.
d) @Draw. The solid line in Figure 4B shows the potential distribution of each part at the time of reading @), and the dotted line shows the potential distribution at the time of reading 'o'6 (
The potential distribution of each part of W"0') is shown.

φ8 is the built-in PN junction (between EB)
n),]? It is a tensile. During reading, holes are not injected from the substrate SUB into the surface layer P- due to this barrier of φ8. Next, in the "0# write (W'0"), the write line WTL drops to "ss" as shown in Table 1 and FIG. 3, so the potential of the surface layer P- also drops due to capacitor coupling. Holes are injected into the collector C (surface layer p-) of the parasitic bipolar transistor by the knee-through technique.At this time, the write curve (the 4-line curve in FIG. 4B) becomes a barrier. φ5 is not formed. This is because the potential of the N layer is also lowered due to the decrease in the potential of the surface layer P- (punch-through). The OH1 loading operation is for a conventional TI memory cell, and the above operation is described for a selected TI memory cell TC.

By the way, regarding the unselected TI memory cell TC, the case (even line W) of the other unselected TI memory cell TC (so-called half-selected TC) on the selected bit line BL
At the same time, a voltage changing from 1VCC to Vss is also applied to TL). On the other hand, Vcc is applied to the word line WLK of these unselected TI memory cells TC, and "cc" is applied to the pace B (intermediate layer N-) in the unselected cells TC.However, in reality, the pace B V.C is not applied uniformly over the entire (intermediate layer N), and "cc" decreases as the distance from the source S (word line WL) increases. In this state, when these non-selected cells migrate to 1 (as the WTL of the selected cell TC decreases from 2 vCC to vss), these non-selected cells T
The original barrier φB of C becomes smaller, and the hole flow (S
UB to P″″). This is a writing error.

This erroneous writing will be explained in more detail using the potential diagram shown in FIG. 4C. Figure 4C is similar to Figure 4B, and Figure 4A is similar to Figure 4B.
It is a potential diagram in which each part of the layout of the figure is made to correspond. The solid line is the TI in the completely unselected state (that is, the held state)
It shows the potential of the cell. Although the N layer has a lower value than υV as described above, it is still sufficiently higher than v88 and sufficiently functions as a barrier against the surface layer P-.

Next, consider the case where "0# write is performed to another selected cell connected on the same bit line BL. At this time, the write line WTL of the unselected cell also changes from 1Vcc to vl]8
decreases to The write line WTL of the cell, that is, the dart v
With the decrease to Ss, the potential of the surface layer also decreases,
The potential of the N layer is also lowered and lowered. The potential at this time is shown by the dotted line.

Even if the potential of the N layer decreases in this way, there is a need for the N layer to sufficiently act as a barrier against the surface layer P- in non-selected cells +p4. For this purpose, it is impossible to lower the no-en-chill withstand voltage in the parasitic bipolar transnosta. This is because if the punch-through breakdown voltage is low, holes will be injected from the substrate SUB to the surface layer P- by Q punch-through in the half-selected state, resulting in an erroneous I (include) result.

Therefore, it is necessary to delicately set the munch through voltage. switching, the potential of pace B of unselected cell TC is vcc
Even if the potential of its collector C drops (1 (the wire WL falls below Lvc
c), parasitic bind j
? -Is it definitely for La Transosta? It is a punch-through voltage that does not cause punch-through, and even if the potential of the pace B of the selected cell TC is at v88 and the potential of its collector C drops (because WTL drops from 1!-voc to V2O) ) is a punch-through voltage that always causes punch-through in the parasitic bipolar transistor.

However, it is extremely difficult to delicately set the through voltage in this way due to variations in manufacturing conditions, and the yield rate also deteriorates.

Therefore, the present invention adopts a completely new method that does not make the 0'' pledge operation dependent on punch-through.The structure of the TI memory cell remains unchanged.The punch-through voltage at this time is set to a sufficiently high value. Unselected memory cell T
The above-mentioned misdirection and confusion in C cannot occur. However, if the punch-through voltage is set high enough, there seems to be an inconvenience that "0" cannot be written to the selected cell TC, which should originally be "ON" programmed. However, this inconvenience does not occur. This is because the "0" ancestor 4-inclusive no longer relies on such A' through.

The conditions for read, write, and hold operations in the present invention are as shown in Table 2 below, which is different from Table 1 above.

The following Puhaku Table 2 differs from Table 1 in the parts marked with *, and when
BB-'fc applied to word line WL. ■88- is Vs
S or less. When writing “1”, V8 is used as before.
Even the size of s is good, but "1" is included in the data.

It is troublesome to switch between vs8- and Vss according to "1", and even if "8g-" is set when "1" is included, there is no problem in emitting holes from the surface layer P-. No.

As described above, the present invention determines whether 1 is included or not by turning on and off the parasitic bipolar transistor, rather than by turning on or through. Therefore, the pace B (intermediate layer N''-) is set to a depth < (
Vss-), basically VCClvss
It will operate with 3 power supplies of 8B-. However,
Introducing such a 3' source is clearly disadvantageous, and it would be advantageous to be able to generate v8s- isometrically to the size of a conventional two-power source. FIG. 5 is a sequence diagram showing a preferred example of the "tall write operation" according to the present invention. In this figure, curve VWL8 is the voltage of the selected word line, curve VWL i is the voltage of the unselected word line, and vwTL is the write line. The voltage of W'I'L is shown over time. Time t.

Then, the word line voltage (vwLS) drops from Vcc to vss. And following this, write W%t, pressure (Vv
VrL) is dropped from "M(-2"cC) to vss at time t1.

Next, in the peripheral circuits other than the cell, the word line is temporarily connected to the power supply V.
Disconnect 9 from 8s, then connect "ss" with a capacitor.
Press down below. This technology is dynamic MO8RA
This can be achieved using the same bootstrapping technique commonly used for M. As described above, it is sufficiently possible to substantially lower the word line WL to V8s- without using the V8s- power supply by applying the well-known technique.

FIG. 6 is a potential diagram in a selected cell when the layout of FIG. 4A and the operation sequence of FIG. 5 are taken, and the times to, t, and t in FIG.
The potential distributions at the time of reading (R) and when copper is included (W"0") in 2 are shown.

The potential at the time of reading (R) of the selected cell is shown by a solid line. By lowering the word line WLg to 'C''ss, N
Even more V8s. At this time, the built-in potential φ
8, the surface layer P- and the substrate P are sufficiently separated. Next, the process moves to a "0" write operation. 1. Lower the 11+ read gate wTL to Vss. As a result, the surface layer P-
can also be lowered. At this time, in conventional cells, the N-layer is pulled down and holes are injected through punch-through, but in the case of the present invention, as shown by the potential shown by the dotted line, the P-punch-through withstand voltage is sufficiently high, so holes are still injected into the N-layer at least. The surface layer P- and the substrate P are separated from each other by the built-in potential φB, and no holes are injected. This is WTL in unselected cells.
Even if Vss is set to 0, it shows that there is no malfunction due to abuse.

Next, WLs is set to "ss." More precisely, "ss-" is set to φ6 or less. This case is shown by the potential of the □ line. In other words, the N layer is set below Vss by the word line WL≦, the barrier of the N layer is eliminated, and holes are injected from the P type substrate SUB into the surface r@P-.

This is achieved by lowering the pace of the parasitic P-N-P bipolar transistor lower than the emitter potential. - This corresponds to turning on a transistor.

Here, holes are smoothly injected into the surface layer from the substrate SUB, and 'Os4 incorporation into the selected cell is achieved.

(7) Detailed Description of the Invention As described above, according to the present invention, a TI memory is realized in which data "0" can be correctly written only to a selected TI memory cell especially when writing "0".

It is clear that the present invention can be applied not only to so-called TI memory cells but also to semiconductor memory devices in general based on the same operating principle to achieve the above-mentioned effects.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a part of the Tl-RAM, Fig. 2A is an enlarged plan view showing the specific configuration of the part surrounded by a blank in Fig. 1, and Fig. 2B1'5A is 2B-2B sectional view in Figure 2A, Figure 2C is 2C-2B in Figure 2A.
2C is a sectional view, FIG. 3 is a waveform diagram that clearly shows the series of operations of reading, "1" writing, and "0" writing, and FIG. 4A is a waveform diagram obtained by vertically cutting the center part of FIG. FIG. 4B is a potential diagram corresponding to each part of the layout in FIG. 4A, FIG. 4C is a potential diagram corresponding to each part of the layout in FIG. 4A, and FIG. FIG. 6 is a sequence diagram showing a preferred example of the "0" loading operation according to the present invention, and FIG. 6 is a potential diagram corresponding to the layout of FIG. 4A and the operation sequence of FIG. 5. WL...・Word line, BL...Bit line, TC...
TI memory cell, w″rL...Write line, D...Drain, S...Source, P-...Surface layer, N-...
・Intermediate layer, SUB...semiconductor substrate, IS...insulating layer, B...base, C...collector, E...emitter. Patent Applicant: Fujitsu Limited Patent Attorney Akira Aoki Patent Attorney Kazuyuki Nishidate 1) Yukio Patent Attorney Akiyuki Yamaguchi Figure 1 Figure 2A Figure C4-1 Figure 3 - 1" 4B Figure 40

Claims (1)

[Claims] 1. A reverse conductivity type drain region connected to a word line formed in a 4'f[ type semiconductor substrate, a reverse conductivity type drain region connected to a bit line, and a reverse conductivity type drain region formed between these source and drain regions. Further, a surface layer of one conductivity type forming a data holding portion, an intermediate layer of an opposite conductivity type formed immediately below the surface layer so as to surround the surface layer, and an insulating layer above the surface layer of the semiconductor substrate. In a semiconductor memory device having a plurality of memory cells each having a word line formed through a single word line, when writing at least one of data "0" or data "1", the word line is connected to the word line 111 in a selected memory cell. The level of the surface layer is set to be lower than that of the semiconductor substrate, and the level of the surface layer is lowered due to the change in the previous HI2f'+input line'1 (1), the surface layer becomes the collector, the intermediate layer becomes the base, iI
A semiconductor memory device characterized in that the data is written by injecting carriers of one conductivity type into the surface layer by turning on a parasitic pibora transnoster having the semiconductor substrate as an emitter.