CN106062878A

CN106062878A - Write assist sram circuits and methods of operation

Info

Publication number: CN106062878A
Application number: CN201580011001.9A
Authority: CN
Inventors: H·栾; B·贝特曼; V·阿克赛尔拉德; C·程; C·谢瓦利尔
Original assignee: Kilopass Technology Inc
Current assignee: Kilopass Technology Inc
Priority date: 2014-09-25
Filing date: 2015-09-25
Publication date: 2016-10-26
Also published as: EP3149736A4; EP3149736A1

Abstract

A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Description

Write auxiliary SRAM circuit and operational approach

Cross reference to related applications

Present patent application is entitled " the Two-Transistor SRAM Circuits submitted on January 27th, 2015 And Methods of Operation " the continuation application of U.S. Patent application No.14/607,023；It is January 6 in 2015 Entitled " the Cross-Coupled Thyristor SRAM Circuits and Methods of Operation " that day submits to The continuation application of U.S. Patent application No.14/590,834.Entitled " the Six-Transistor that it relates to same date submits to SRAM Circuits and Methods of Operation " U.S. Patent application No.14/740,209, each of which It is desirable that the priority of 582, it is together with the application in U.S. Provisional Patent Application No.62/055 of JIUYUE in 2014 submission on the 25th In other lists of references whole of quoting be collectively incorporated into herein.

Technical field

The present invention relates to the IC-components with memory function, in particular to static random accesP storage Device (SRAM) device.

Background technology

Since generation nineteen fifty end invention integrated circuit, circuit design is evolving always, especially for integrator Part, is consistent with exploitation semiconductor technology.Technology in early days is bipolar technology, compared with integrated circuit technique later, its Occupy the big quantity space on semiconductor substrate surface and it needs to substantial amounts of electric current and thus produce high power consumption.Field effect after a while Answer technology, particularly MOS (metal-oxide semiconductor (MOS)) technology, use transistor, little compared with their ambipolar opponent Many, there is reduced-current, thus there is low-power consumption.CMOS (complementary MOS) technology further reduces the electricity in integrated circuit Stream and power consumption.Current nearly all large scale integrated circuit has had turned to complementary metal oxide semiconductors (CMOS) (CMOS) technology.

For semiconductor memory bipolar technology the most for many years.But this research is generally focused on single storage Device unit, and obtain memory cell can be array a part conclusion after stop.Bipolar memory cell array Further research and development be hampered by CMOS memory unit and occupy little space than any bipolar memory unit and consume Less power, and any bipolar memory cell array is the most necessarily not as the long-term conviction of CMOS array.Progress in recent years Depend on the continuous dimensional contraction of semiconductor processing technology, thus contract for bigger current densities and the higher speed of service The little size of memory cell.

It is SRAM with the integrated circuit that CMOS technology is implemented, its memory cell uses bi-stable latch circuit Circuit, as long as power supply is applied to unit, it becomes possible to make SRAM memory cell be maintained at logical one or logical zero state. Two cross-linked phase inverters have employed decades, and each all includes source transistor and complementary load crystal Pipe, and two selection transistors, form six transistor CMOS sram cells.Currently used many integrated circuits need to combine High-performance memory on CMOS logic circuit and chip.Modern high performance processor and SOC(system on a chip) (SoC) application program need Want more on-chip memory, to meet the requirement of performance and handling capacity.Such as, an integrated circuit can be included on chip CMOS SRAM as the 32MB of caching.Due to the VDD of 0.9 volt and the leakage current of every memory cell 25 nanoampere, such Circuit only memory array just consumes 7 amperes, does not the most consider the power consumption of the logical gate of chip.Additionally, due to this electricity The size on road is shunk by being used for manufacturing constantly the reducing of Technology of circuit, and the stability of memory cell and power consumption are Through becoming one of limiting factor of process costs and circuit complexity so that the designer of these chips is unwilling to use up-to-date Technology.

CMOS SRAM in this equipment is generally of the access time of 200 picosecond level, and standard deviation is 30 skins Second.Thus in order to obtain 6-σ Sigma reliability, the additional margin of 6x 30 psec is necessary, result in permission 380 psecs Access the requirement of memory cell.Faster bipolar technology is used to be generally limited by SRAM memory in such devices Drive circuit, even if use, also uses increasingly complex bipolar CMOS (BiCMOS) manufacturing process, needs extra heat to follow Ring, the manufacture making MOS device is more difficult and expensive.

But along with semiconductor technology narrows down to a nano level generation, compared to equal size bipolar transistor current, pass through The leakage current of MOS transistor and watt current are particularly susceptible to the biggest change.Prediction shows, due to the packaging density increased With the statistic bias of electric current, the operation existing problems of following CMOS SRAM device.Wish to find interchangeable method.

The invention provides a kind of SRAM memory cell, it is based on IGCT, and it is the bipolar technology of a kind of form, past Represent toward by the bipolar transistor of two couplings.Memory cell is very suitable for many changes, consequent SRAM collection Become circuit can be designed for high-speed cruising, if or need the low cruise of less power, or the most higher integrated, If needing the SRAM integrated circuit of compact package.Additionally, SRAM memory cell can be kept away by Conventional CMOS technology manufacture Exempt from the development cost of new technique.

Summary of the invention

In the integrated circuit with at least one logic circuit, logic circuit operate in logic circuit voltage range and Being connected to the multiple memory cells being arranged in the array on substrate interconnected by multipair paratope line and wordline, the present invention carries Supply each memory cell, including the IGCT of pair of cross coupling；A pair bipolar transistor, each ambipolar crystalline substance Body pipe is respectively provided with the base region being connected to wordline, is connected to the emitter region of an IGCT and is connected to paratope line centering The collector area of；And accommodate the electric isolution bucket of cross-couplings IGCT pair, described bucket in the substrate and electrical bias so that Obtain voltage on an off bipolar transistor pair in the wordline in logic circuit voltage range, with by cross-couplings IGCT with Paratope line is to being connected and disconnected from.

Form pair of cross coupling bipolar transistor and include step with the process constituting above-mentioned IGCT, form insulation The annulus of material, in the upper surface of the Semiconductor substrate extending to the first conduction type, to limit bucket on substrate, and introduces The adulterant of films of opposite conductivity to form buried regions in the bottom of bucket.Then the first conductivity type dopant is injected into described bucket In, form the deep-well region extending to buried regions.Next opposite conductivity type adulterant is injected to form shallow well.Then at integrated circuit On other positions in the same process of the grid that forms field-effect transistor, bucket is formed two grids and is used as to cover Film, to implant a dopant in bucket, forms the emitter and collector for cross-couplings bipolar transistor pair.Finally, will Electrical connection is supplied to every a pair cross-couplings bipolar transistor, but is not applied to gate electrode.

Obtained semiconductor structure provides the first kind and the cross-coupled pair of opposite types bipolar transistor, its In, annular insulation layer extends to surround the Part I of the upper surface of substrate in substrate, with the first conduction type opposite conductivity The buried regions of type is arranged in the substrate under the Part I of upper surface.The bonding pad of the first conduction type extends to buried regions to incite somebody to action Electrical connection is supplied to it.Inside bucket, the shallow well district of films of opposite conductivity is in the Part II that upper surface is less than Part I Extend to substrate from upper surface.The base contact of the first conduction type extends in bucket outside the Part I of upper surface.? Virtual field effect transistor gate is provided, to realize the emitter region adjacent with grid and the autoregistration of collector area in shallow well district Inject.In the structure shown here, buried regions provides the emitter stage of first kind bipolar transistor, and is coupled to the first power supply.With grid Adjacent the first conductivity regions, side provides the emitter region of opposite types bipolar transistor, and is coupled to the second electricity Source.Bucket provides base stage and the collection of opposite types bipolar transistor of first kind bipolar transistor in shallow well below portion Electrode, shallow well provides base stage and the colelctor electrode of first kind bipolar transistor of opposite types bipolar transistor.

After considering further detail below and accompanying drawing, other objects of the present invention, feature and advantage can become aobvious and Being clear to, in the accompanying drawings, similar reference marker represents similar feature in whole accompanying drawings.

Accompanying drawing explanation

Using identical reference marker the most in different figures, wherein, the element of numbering plays identical or phase As function, and help the theme described in reader understanding.

Figure 1A is the circuit diagram of IGCT；And Figure 1B shows the circuit of the cross-couplings IGCT forming memory cell Figure.

Fig. 2 is exemplified with the array of SRAM memory cell.

Fig. 3 A is the circuit diagram of the cross-couplings IGCT memory cell with ambipolar selection transistor；And Fig. 3 B is There is the circuit diagram that MOS selects the memory cell of transistor.

Fig. 4 A is the circuit diagram of the cross-couplings memory cell not selecting transistor；Fig. 4 B is exemplified with the storage of Fig. 4 A The crosspoint array of device unit, has the voltage on the bit line and wordline of write operation；And Fig. 4 C is exemplified with the storage of Fig. 4 A The crosspoint array of device unit, has the voltage on the bit line and wordline of read operation；Fig. 4 D shows at a knot Structure is connected to the low-power write operation of the cross-couplings IGCT memory cell array of paratope line and wordline；Fig. 4 E be The representative sequential chart of multiple points of memory cell in Fig. 4 D；Fig. 4 F shows for being connected in Fig. 4 D inverse structure mutually The low-power write operation of the cross-couplings IGCT memory cell array of cover line and wordline；Fig. 4 G is memorizer in Fig. 4 F The representative sequential chart of multiple points of unit；And Fig. 4 H is to support the SRAM memory array for one embodiment of the present of invention The representative diagram of circuit block.

Fig. 5 A is the block diagram of the array of sram cell, has current source so that memory cell to be maintained at standby mould line by line In formula；Fig. 5 B is the circuit diagram of current source in Fig. 5 A；Fig. 5 C is the cross-couplings IGCT for having crosspoint structure The circuit diagram in the standby current source of sram cell, wherein, the negative electrode of IGCT is connected to paratope line, and anode is connected to wordline； And Fig. 5 D be cross-couplings IGCT to bit line and wordline connect contrary circuit diagram.

Fig. 6 is the circuit diagram of the current source being used for SRAM block being maintained in standby mode by memory cell.

Fig. 7 A is the circuit diagram of the cross-couplings IGCT SRAM memory cell having and writing auxiliary transistor and capacitor； With 7B exemplified with the crosspoint array of the memory cell of Fig. 7 A, there is the voltage on the bit line and wordline of read operation；Figure 7C, exemplified with the crosspoint array of the memory cell of Fig. 7 A, has the voltage on the bit line and wordline of write operation；Fig. 7 D It it is the circuit diagram with the cross-couplings IGCT SRAM memory cell that PMOS writes auxiliary transistor；Fig. 7 E is exemplified with Fig. 7 D's The crosspoint array of memory cell, has the voltage on the bit line and wordline of read operation；Fig. 7 F deposits exemplified with Fig. 7 D's The crosspoint array of storage unit, has the voltage on the bit line and wordline of write operation.

Fig. 8 A is the circuit diagram with the monocrystalline brake tube SRAM memory cell selecting transistor；And Fig. 8 B is not select The circuit diagram of the monocrystalline brake tube SRAM memory cell of transistor.

Fig. 9 A writes the monocrystalline brake tube SRAM of auxiliary transistor for PMOS and NMOS of crosspoint array deposit exemplified with having Storage unit；Fig. 9 B shows that anode and negative electrode connect contrary another monocrystalline brake tube memory cell being similar to Fig. 9 A； And Fig. 9 C is the circuit theory diagrams in the standby current source of monocrystalline brake tube SRAM memory cell in crosspoint array, Fig. 9 D shows Having shown the circuit diagram of monocrystalline brake tube SRAM memory cell, its anode is connected to bit line, and its negative electrode is connected to wordline, has PMOS Write auxiliary transistor；Fig. 9 E shows the crosspoint array of the memory cell of Fig. 9 D, has the bit line for read operation and word Voltage on line；Fig. 9 F and 9G shows the crosspoint array of the memory cell of Fig. 9 D, has the position for two-stage write operation Voltage on line and wordline；Fig. 9 H shows the circuit diagram of monocrystalline brake tube SRAM memory cell, and its anode is connected to wordline, its Negative electrode is connected to bit line, has PMOS and writes auxiliary transistor；Fig. 9 I shows the crosspoint array of the memory cell of Fig. 9 H, tool There is the voltage on the bit line and wordline of read operation；Fig. 9 J and 9K shows the crosspoint array of the memory cell of Fig. 9 H, There is the voltage on the bit line and wordline of two-stage write operation；Fig. 9 L shows and is connected to bit line and word in a structure The low-power write operation of the monocrystalline brake tube memory cell array of line；Fig. 9 M is the generation of multiple points of memory cell in Fig. 9 L Table sequential chart；And Fig. 9 N shows the monocrystalline brake tube memorizer list being connected to bit line and wordline in the inverse structure of Fig. 9 L The low-power write operation of element array；And Fig. 9 O is the representative sequential chart of multiple points of memory cell in Fig. 9 N.

Figure 10 is exemplified with complementary metal oxide semiconductors (CMOS) (CMOS) technique of prior art.

Figure 11 A and 11B is exemplified with the process for forming shallow trench isolation region.

Figure 12 is exemplified with vertical bipolar transistor.

Figure 13 is the flow chart of the process for manufacturing structure shown in Figure 12.

Figure 14 A-14D illustrate in more detail some steps of Figure 13.

Figure 15 is exemplified with lateral bipolar transistor.

Figure 16 is the flow chart of the process for manufacturing structure shown in Figure 15.

Figure 17 A-17D is exemplified with the process for forming combination type NMOS-NPN structure.

Figure 18 A and 18B is exemplified with the cross section of sram cell.

Figure 19 is the top view of structure shown in Figure 18 A and 18B.

Figure 20 A-20D is exemplified with the part of the process of the sram cell for forming Figure 18 and 19.

Figure 21 A and 21B is exemplified with the cross section of the sram cell with ambipolar selection transistor.

Figure 22 is the top view of structure shown in Figure 21 A and 21B.

Figure 23 A-23E is exemplified with the process steps of the structure for manufacturing Figure 21 and 22.

Figure 24 is exemplified with the cross section of the SRAM cell structure using deep n-type trap to be formed.

Figure 25 is the cross section of three layer transistor SRAM units.

Figure 26 is the top view of the layout of three layer transistor SRAM units shown in Figure 25.

Figure 27 A and 27B is exemplified with the cross-sectional view of four layer transistor SRAM unit.

Figure 28 is the top view of structure shown in Figure 27 A and 27B.

Figure 29 A and 29B is exemplified with the cross-sectional view with the four layer transistor SRAM unit writing auxiliary FET.

Figure 30 is the top view of structure shown in Figure 29 A and 29B.

Figure 31 is the cross-sectional view of two transistor sram cell.

Figure 32 is exemplified with the details of manufacture process.

Figure 33 is the curve chart exemplified with the Typical dopant concentrations for vertical bipolar transistor.

Detailed description of the invention

I. circuit and the explanation of operation thereof

A. the explanation of IGCT and operation

As previously observed, along with semiconductor technology reduces, the statistics variations of MOS transistor increases.Use ambipolar Transistor is but not the case.It is true that in certain point, it is considered to have the processing procedure of 55nm critical dimension, generally quilt Being referred to as " 55nm processing procedure ", MOS transistor disappears relative to many traditional advantages of bipolar transistor.That is, bipolar transistor There is the scale equal with MOS transistor, transmit the electric current fewer than their MOS transistor opponent's statistics variations.Therefore, this A bright observation is, uses the processing procedure of 55nm or less, and SRAM memory array is more suitable for bipolar technology.

The SRAM memory cell of the present invention is based on IGCT.IGCT, also referred to as silicon controlled rectifier (SCR), be generally used for Power is applied.IGCT is four layers (PNPN), three node device, is generally of two terminals, an anode and a negative electrode.? In power application, usual 3rd terminal, it is referred to as controlling end, for controlling the electric current between anode and negative electrode.Figure 1A is by two The circuit diagram of the IGCT that bipolar transistor represents, PNP transistor 10 and NPN transistor 11, they are formed when merging PNPN IGCT.The emitter terminal 12 of PNP transistor 10 forms anode, and the emitter terminal 13 of NPN transistor 11 forms the moon Pole.In order to completely, control end and be shown by dotted line in the accompanying drawings.

By at such as voltage V_DDAnd V_SSTwo supply voltages between the IGCT of suitable power supply, IGCT can be located In one of two states, or " conducting " and conduction electric current, or " shutoff " and non-conductive.If the IGCT conduction in Fig. 1, The collector area (being represented by reference marker 14) of the base region/PNP transistor 10 of NPN transistor 11 is height, i.e. transistor 11 Base-emitter junction forward bias.The base region of the collector area/PNP transistor 10 of NPN transistor 11 is (by reference marker 15 Represent) be low, i.e. the base-emitter junction of transistor 10 also forward bias.The two transistor 10 and 11 is in saturation mode, Electric current flows through IGCT.If IGCT " turns off ", the collector area of the base region/PNP transistor 10 of NPN transistor 11 is Low, i.e. the base-emitter junction of transistor 11 not forward bias.The base of the collector area/PNP transistor 10 of NPN transistor 11 Polar region is high, i.e. the base-emitter junction of transistor 10 the most not forward bias.The two transistor 10 and 11 is off mould Formula, does not has electric current to flow through IGCT (in addition to leakage current).

In the scale of integrated circuit, IGCT is compatible with the most traditional CMOS fabrication technology, description below, and makes us Surprised is adapted to different circuit structures, emphasizes speed, power and collection to require according to the application of SRAM memory user Become, either as SRAM integrated circuit still as a part of integrated circuit.

B. the explanation of cross-couplings IGCT and operation

In a preferred embodiment of the invention, a pair IGCT cross-couplings, as shown in Figure 1B, to form memorizer Unit, each IGCT 16A, 16B are formed by PNP transistor 10A, 10B and NPN transistor 11A, 11B.At memory cell In the case of selecting transistor, p-type emitter terminal 12A, 12B of two transistors 10A, 10B are connected at V_DDElectricity Source pressure-wire, memorizer high power supply voltage, and N-type emitter terminal 13A, 13B of transistor 11A, 11B are connected at V_SS? Two power lines, memorizer low supply voltage.Two IGCT 16A and 16B are by the N-type base stage of the transistor 10A merged and crystal The colelctor electrode of pipe 11A is to the p-type colelctor electrode of transistor 10B and the connection of the base stage of transistor 11B that merge and the crystal merged The base of the N-type colelctor electrode of pipe 11B and the base stage of the transistor 10B p-type colelctor electrode to the transistor 10A merged and transistor 11A The connection cross-couplings of pole.It is connected to the N-type base stage of transistor 10A merged with the terminal 17A of the colelctor electrode of transistor 11A For the selection transistor (not shown) of memory cell, to N-type base stage and the transistor 11B of the transistor 10B merged The second terminal 17B of colelctor electrode be connected to the second selection transistor for memory cell.

In operation, described cross-couplings IGCT memory cell core may be at one of two logic states, and one Individual it is referred to as " 1 " and another is referred to as " 0 " by arbitrary.The circuit of use Figure 1B is as example, if IGCT 16A conducting, brilliant Body pipe 10A is in saturation mode, and the p-type colelctor electrode of the transistor 10A of merging and the base stage of transistor 11A are high (with forward bias Put base-emitter junction).It is high by cross-couplings, the colelctor electrode of transistor 11B and the base stage of transistor 10, IGCT 15B In transistor 10B base-emitter junction can not forward bias to turn off transistor 10B.IGCT 15B turns off.On the contrary, as Really IGCT 15B conducting, IGCT 15A just turns off.

Multiple SRAM memory cell being arranged and provide integrated circuit storage in an array, it can be with other circuit In conjunction with, such as logic circuit.Memory cell is interconnected by the set of the conductor wire advanced in vertical direction.Fig. 2 is exemplified with tool Having a this common layout of the array 20 of sram cell 27, each unit has cross-couplings IGCT core.One Organize horizontal wordline 24 and one group of vertical bit lines 23A, 23B interconnect sram cell.Each unit 27 is all connected to level in the drawings The wordline 24 advanced, and the bit line 23A that vertically travels in the drawings and paratope line 23B thereof.Under normal circumstances, bit line is understood to It is to and from memory cell and transmits data, a bit information.Wordline is understood to activate memory cell, for by data transmission In memory cell, write operation, or transmit data, read operation from memory cell.In write operation, bit line 23A and 23B passes Send complementary voltage, represent Digital Logic " 1 " or " 0 " state, to be written in selected memory cell 31 for storing.? In read operation, bit line 23A and 23B starts at equal voltage, depends on the digital signal of storage in memory cell 27 subsequently And overturn high or low.The signal that the signal that bit line 23B transmits and bit line 23A are transmitted is complementary, if so that bit line 23A exists " high " voltage, bit line 23B is just at " low " voltage, and vice versa.If memory cell 27 is not the most write, the most do not read, Memory cell is at standby, under they are maintained at stable status condition whereby, with the logic maintaining each of which to store State.

C. there is cross-couplings IGCT and select the sram cell of transistor

In arranging at one, select transistor for cross-couplings IGCT is connected to bit line.This illustrates in figure 3 a, Wherein, identical with Figure 1B reference marker is used for cross-couplings IGCT 16A and 16B.Bipolar transistor 32A and 32B is used for To the selection transistor of cross-couplings IGCT 16A and 16B, to form sram cell.

The emitter region of NPN selection transistor 32A is connected to the colelctor electrode of the NPN transistor 10A of the merging of IGCT 16A The base region of district/PNP transistor 11A, is also connected to the base region/PNP crystal of the NPN transistor 11B of the merging of IGCT 16B The collector area of pipe 10B.NPN selects the collector area of transistor 32A to be connected to the base region of bit line 23A and transistor 32A even Receive wordline 24.In a similar fashion, NPN selects the emitter region of transistor 32B to be connected to the NPN of merging of IGCT 16B The base region of collector area/PNP transistor 10B of transistor 11B, is also connected to the NPN transistor of the merging of IGCT 16A The collector area of base region/PNP transistor 10A of 11A.NPN select transistor 32B collector area be connected to bit line 23B and The base region of transistor 32B is connected to wordline 24.Emitter region for powered memory unit, PNP transistor 10A and 10B It is connected at voltage V_DDHigh power supply, the emitter region of NPN transistor 11A and 11B is connected at voltage V_SSLow power supply.

In order to sram cell is properly functioning, memory cell needs the voltage higher than standard logic core voltage, i.e. SRAM The voltage that the logic circuit of the integrated circuit belonging to unit is used.It is that the standard Core logic circuit of CMOS is typically from 0 Operate in the range of 1 volt.This SRAM memory supply voltage requires can be by using the higher electricity for SRAM power supply Pressure meets, the voltage V such as used by the input/output circuitry of integrated circuit_ddIOOr from V_ddIOThe voltage obtained.But It is in one embodiment of the invention, the requirement for additional circuit can be avoided.In the structure of memory cell, SRAM Memory cell can be arranged in the p-type bucket in deep n-type trap in the semiconductor substrate.See Figure 31 and deep n-type trap structure and The related description of technique.By p-type bucket negative bias, so that ambipolar selection transistor 332A and 32B can use standard logic Core voltage.Therefore, when typically at the high power supply voltage V of sram cell_DDWith low supply voltage V_SSBetween drive the feelings of wordline Under condition, in one embodiment of the invention, it is connected to select the voltage swing office of the wordline of bipolar transistor 32A and 32B It is limited to V_SS(=0V or ground) goes up 0.5V and relative to V_DD1.5V.This layout achieves circuit, and it drives from core logic electricity The wordline that road directly constructs, i.e. need not the voltage conversion circuit between two parties between core logic and bit line.

Field-effect transistor can be used for selecting transistor, as shown in Figure 3 B.NMOS (FET) transistor 33A and 33B divides Wordline 23A and 23B are not connected to cross-couplings IGCT 16A and 16B, as shown in Figure 3 B, have many identical with Fig. 3 A Reference marker.The source/drain regions of NMOS selection transistor 33A is connected to the NPN transistor 11A's of the merging of IGCT 16A The base region of collector area/PNP transistor 10A, be also connected to the base region of the NPN transistor 11B of the merging of IGCT 16B/ The collector area of PNP transistor 10B.NMOS selects another source/drain regions of transistor 33A to be connected to bit line 23A, crystal The grid of pipe 33A is connected to wordline 24.In a similar fashion, NMOS selects a source/drain regions of transistor 33B to be connected to The base region of collector area/PNP transistor 10B of the NPN transistor 11B of the merging of IGCT 16B, is also connected to IGCT The collector area of base region/PNP transistor 10A of the NPN transistor 11A of the merging of 16A.Another source electrode of transistor 33B/ Drain region is connected to paratope line 23B, and the grid of transistor 33B is connected to wordline 24.For powered memory unit, PNP is brilliant The emitter region of body pipe 10A and 10B is connected at voltage V_DDHigh power supply, the emitter region of NPN transistor 11A and 11B connects To at voltage V_SSLow power supply.Below (Figure 26 and following etc.) we illustrate how to implement and manufacture the circuit of Fig. 3 B.

It is that the selection transistor that ambipolar or field-effect transistor are used as memory cell depends on multiple design " power Weighing apparatus ".Field-effect transistor is less than bipolar transistor, obtains desired less unit size.But FET is used as selector There is bigger shortcoming in part.(1) they to limit the access speed of memory cell identical with CMOS opponent.It addition, as choosing The FET selecting device limits the electric current of the voltage in order to be raised and lowered on bit line capacitance that can be provided by memory cell Amount.Ambipolar NPN selector can provide much bigger electric current, thus swings the voltage on bit line quickly.(2) by elder generation Enter the FET change at random by height between cells of technique manufacture, as previously mentioned.It reduce the behaviour of memory cell Making surplus, it generally has to by circuit design special in wordline and bit line drive circuit or by increasing memorizer list Transistor size in unit is offset, thus increases unit size.Change at random in NPN selector is much smaller.(3) not Select the standby current undesirable leakage control by the FET device " turned off " in memory cell of memory cell.? In the device that advanced technologies manufactures, this leakage becomes very large.Use and there is MOS based on IGCT memory cell selection The source of this unwanted leakage current is incorporated in unit design by transistor, and NPN selector avoids this and is not required to The leakage current wanted.

D. there is cross-couplings IGCT but not there is the sram cell selecting transistor

In another embodiment of the invention, SRAM memory cell is not in order to the selection crystal accessing memory cell Pipe.On the contrary, cross-couplings IGCT 46A and 46B is directly connected to wordline 44 and bit line 43A, 43B, as shown in Figure 4 A, is formed and hands over Crunode memory cell array.In this is arranged, it is connected to high SRAM supply voltage V on paper_DDIn the case of, IGCT The anode of 35A and 35B, the emitter region of PNP transistor 40A and 40B is connected respectively to bit line 43A and 43B, connects on paper Receive low SRAM supply voltage V_SSIn the case of, the negative electrode of 35A and 35B of IGCT, the emitter stage of NPN transistor 41A and 41B District connects wordline 44.These lines owing to wordline and bit line are powered to memory cell, in the array of this memory cell On voltage-operated must be well-designed.With reference to not there is the array of the SRAM memory cell 47 selecting transistor so that this to be described A little operations.Unit is interconnected, as shown in Figure 4 B and 4C by bit line 43A, 43B and wordline 44.

It shall yet further be noted that and give voltage and current value in this article, preferably to explain the present invention, these values should be considered It it is approximation.Voltage and current can change or change, to adapt to the electrical characteristic of the certain device used on the integrated. As example, Fig. 4 H shows the SRAM integrated circuit based on IGCT of block level.The array of sram cell is by being generally used for battle array Row wordline the signal from row decoder block and be generally used for array bit line from column decoder, write and put with reading The signal addressing of big device block.These address signals and control signal are transmitted by address block address, control and I/O wordline, and it will Signal is sent to row pre decoder block and row pre decoder and controls block.These blocks process signal, and are sent by their signal To row decoder block and column decoder, write and sense amplifier block, as known to the skilled person.Arrow in Fig. 4 H It is shown as pointing to array, because this exemplary operation is addressing operation, selects the particular memory cell in array at this, no Opinion is for reading or write operation.

For conducting thyristor, the voltage applied the most between the anode and cathode across IGCT should be at least forward bias PN Knot is plus the summation of the collector emitter voltage of saturated PNP transistor.Therefore, the change in voltage of applying is very big, from about 0.8V and bigger beginning.The voltage applied is the biggest, and IGCT is fully on the fastest.As shown at figure 4h, 1.4V is chosen as In best the trading off that suitable low-voltage responds for optimal IGCT.But around the block of array together with CMOS logic circuit Operation, current CMOS logic voltage range is about from 0 to 1.0 volts.Allow row decoder block and column decoder, write and put with reading The mode that CMOS logic circuit in big device block suitably connects is by the CMOS logic voltage range in row decoder block Raise to 0.4 volt or mobile.That is, although CMOS logic circuit still operates in the range of 1.0 volts, but scope 0.4 to 1.4 volts it Between extend.This is realized by the voltage level shifting block being expert between pre decoder block and row decoder block.Level shift block The special voltage of other blocks of I/O (input/output) block freely can be used.

For memory cell array based on IGCT and row decoder block and column decoder, write and sense amplifier Another mode that CMOS logic circuit in block suitably connects is that array is biased in desired voltage.Example at Fig. 4 H Property voltage in, array and column decoder, write can be by negative 0.4 volt of biasings with sense amplifier block, according to above in regard to tool There is the mode selected described in the cross-couplings IGCT of transistor and the material relevant with Figure 31.By suitable biasing, it is not necessary to Level shift block in Fig. 4 H, but need another level shift block for column signal, so that+1.0V scope will be arrived described 0 In voltage swing be moved down into-0.4 to+0.6V scope.These alternatives consume the most commensurability circuit resource, such as cloth Situation is amassed, and it is that the designer of SRAM integrated circuit must take into and balances.

Return to the operation of cross-couplings IGCT memory cell array self, in standby, bit line 43A, 43B and word Line 44 is maintained at the memory cell so that array and maintains the voltage of its logic state stored indefinitely, i.e. each is deposited Storage unit all " holding lives ", does not has transition status.In write operation, by the paratope line of selected memory cell and Wordline drives high and low, to be arranged in desired logic state by selected unit.Not selected memory cell Bit line and wordline be maintained at standby voltage to keep constant.Difficulty occurs at the memory cell being " semi-selection ", i.e. they Bit line or their wordline (but not being the two) be connected to the memory cell of selected memory cell.Deposit selected On storage unit, the voltage for write operation must be sufficiently large, in order to selected unit is driven into desired logic shape State, but be not very big, to such an extent as to change the logic state of half-selected cell.

In read operation, for selected memory cell, the paratope line of selected memory cell is driven height, will The wordline of selected memory cell drives low, to allow the state of unit to overturn the voltage of paratope line, in order to differential amplification Device reads memory cell state.On the other hand, bit line and the wordline of non-selected memory cell is maintained at standby voltage with dimension Hold constant.For semi-selective memory cell, on selected memory cell, the voltage for read operation must be sufficiently large, So that the state of selected memory cell can affect the voltage on bit line.But this voltage should not be too high and to affect them Bit line or their wordline (but not being the two) be connected to other memory cells of selected memory cell, semi-selective Unit, logic state.

Fig. 4 B exemplified with write operation, such as, is connected to the wordline shown in Fig. 4 A and position by the array of memory cell 47 Line.In this illustration, first in the first row to be write and the 3rd memory cell, depend on state to be write, will It is respectively driven to 1.6V (or 0.8V) and 0.8V (or 1.6V) for bit line 43A and 43B of selected memory cell.To be used for The wordline 44 of selected memory cell drives as little as 0V from 0.4V, so that in memory cell selected by each Individual IGCT applies the biasing of 1.6V, and the second IGCT stands the biasing of 0.8V simultaneously.These voltages are correspondingly by memorizer list Unit is driven into desired state.Unselected memory cell stands on its bit line 43A, 43B 0.8V, in its wordline 44 The standby voltage of 0.4V.Unselected memory cell is kept it in current state by the 0.4V voltage produced.On the other hand, Semi-selective memory cell stands the voltage of 0.8V for the unit being connected to the wordline identical with selected unit, or right 1.2V (1.6-0.4V) or the voltage of 0.4V (0.8-0.4V) is stood in the unit being connected to the bit line identical with selected unit. These undertensions are with " upset " or the state that changes semi-selective memory cell.

In read operation, all it is driven into 1.3V for bit line 43A and 43B of selected memory cell, for selected The wordline 44 of memory cell is driven into 0V.The state of selected memory cell " overturns " bit line in this or another manner Voltage on 43A and 43B, in order to memory cell can be read.Protect for bit line 43A and 43B of non-selected memory cell Stay 0.8V, for the wordline 44 of non-selected memory cell at 0.4V, so that these memory cells are maintained at current state In.The semi-selective memory cell being connected to the wordline identical with selected memory cell stands the voltage of 0.8V, and connects The semi-selective memory cell receiving the bit line identical with selected unit stands the voltage of 0.9V.These voltage neither ones Be enough to " upset " or change the state of memory cell.

It is compromise that above voltage is interpreted as between speed of operation and power consumption.Such as 0.8V voltage is slightly above 0.7V silicon knot Cut-in voltage, can cause during read or write by some leakage currents of semi-selective memory cell.But optimize Speed.Higher biasing causes higher speed, but causes higher leakage (power consumption) on selected line.For SRAM's Application-specific aids in determining whether the balance between speed and power consumption.Furthermore, it is possible to adjust for selected memory cell With the wordline of non-selected memory cell and the shifted relative of bit line so that revealing minimum or optimizing and the holding concurrently of other circuit Capacitive.Such as in read operation, the wordline being used for non-selected memory cell is being maintained at 0.4V, same at 0.8V of bit line Time, the wordline for selected memory cell may be set in 0V, and bit line is at 1.3V, or wordline is at 0.3V, and bit line is at 1.6V. The two operating parameter is the most possible, but they cause the different electric leakages of the wordline by selected memory cell and bit line Stream.If read multiple unit simultaneously, then in the wordline and bit line of selected memory cell, transmit extra electric current.Permissible Adjust for wordline and bit line to be offset so that voltage declines minimum or maximum by the electric current of memory array lines.In conjunction with Figure 34 and following etc., we illustrate structure and the manufacture of all unit as shown in Figure 4 A.

Should also be understood that above in relation to wordline and bit line and cross-couplings IGCT memory cell anode and negative electrode it Between a layout of connection give explanation and magnitude of voltage.Connection shown in Fig. 4 A can invert, i.e. the anode of IGCT is even Receiving wordline, negative electrode is connected to paratope line pair, the connection inverted with reflection by the corresponding operation changed and voltage.

E. the write operation of the power reduction of cross-couplings IGCT sram cell it is used for

In above write operation explanation, it is connected in memory cell to be write the bit line guarantor of the IGCT " turned off " Hold height, to guarantee to receive during IGCT is during write operation pulse persistance capitalization voltage with " conducting " IGCT.Once store Device unit, the IGCT i.e. " turned off " " turns on ", and its cross-linked corresponding part " turns off ", and the bit line at IGCT keeps While height, new maximum " conducting " electric current of " conducting " IGCT conduction.Which increase the power consumption during write operation.More important , wordline must send away electric current by all unit from this row, so that this electric current is the biggest.This may result in by The notable voltage along wordline in the resistance of circuit declines, and causes the instability in memory array.

This situation can be changed by the bit line to " shutoff " IGCT being precharged as height before write pulse Kind, mode is similar to above-mentioned read operation shown in Fig. 4 D.Fig. 4 E is the voltage of multiple positions of the memory cell at Fig. 4 D Represent figure.After precharging, turn off precharge and " float " with permission bit line, until memory cell rollover states.At this point, lead to Bit line is dragged down (being similar to read operation) by the electric current crossing new " conducting " IGCT.Along with bit-line voltage declines, across the pressure of IGCT Fall reduces, and electric current keeps electric current to decline to minimum.This has three benefits.First, peak point current reduces, because bit-line voltage is being deposited Begin to decline before the builtin voltage of storage unit " conducting " IGCT completely.Secondly, present short duration current is (in figure E I_ThyLShape shown in) power that consumes in reduction write operation.3rd, due to from the perspective of statistics, when different Between upset be written into the multiple unit in row, peak point current in wordline reduces and extends in bigger time interval, enters One step makes the undesirable voltage along wordline decline minimum.

Fig. 4 F is exemplified with the low-power write operation for cross-couplings thyristor cell, wherein, compared to Fig. 4 D, to word The connection of line and bit line is contrary.That is, the memory cell of Fig. 4 F has the anode being connected to wordline and is connected to respective bit line Negative electrode.Fig. 4 G is the expression figure of the voltage of multiple positions of the memory cell at Fig. 4 F.In this illustration, write pulse it Before, the bit line to " shutoff " IGCT is precharged as low (being similar to read operation).Subsequently, precharge path is turned off to allow bit line " float ", until memory cell rollover states.At this point, bit line is drawn high (similar by the electric current of new " conducting " IGCT In read operation).Along with bit line raises, the pressure drop across IGCT reduces, and electric current keeps electric current to decline to minimum.Achieve and leading portion Described in identical benefit.First, peak point current reduces, because bit-line voltage " is led completely at the builtin voltage of memory cell Logical " start to raise before IGCT.Secondly, the present short duration current (I in figure G_ThyLShape shown in) reduction writes behaviour The power consumed in work.3rd, owing to, from the perspective of statistics, being written into the multiple lists in row in different time upsets Unit, peak point current in wordline reduces and extends in bigger time interval, further such that undesirable along wordline Voltage declines minimum.

F. the standby operation of the power reduction of cross-couplings IGCT sram cell it is used for

It not to use fixed voltage (between 0.3V to 0.8V) to be kept by the memory cell (seeing Fig. 4 A) of array In its multiple states between read and/or write, interchangeable scheme by current source regulation voltage with by memorizer list Unit is maintained in standby mode.The memory cell that current source is all connections provides enough electric currents and is sufficient so that the most weak depositing The electric current that storage unit " does not overturns ".Memory cell array is divided into partial array.Owing to generally reading many along wall scroll wordline Individual unit, as shown in Figure 5A, divides array along word-line direction.In memory array 50, bit line 53A and 53B to the most front institute That states intersects with wordline 54 in SRAM memory cell.Be parallel to wordline 54 is high power line 56, and it is connected to SRAM storage Device unit；Wordline 54 and power line 56 to being connected to current source circuit 55.Electric current control is set along wordline, in order to along read Wordline or a plurality of wordline make a choice.

Fig. 5 B shows current source circuit 55 in greater detail.When the address signal to the decoder represented by NAND gate is connected During wordline 54, the identical output signal from NAND gate turns on PMOS transistor, its short circuit current source 58.Power line 56 is pulled upward to V_DDATo read the memory cell connected.Otherwise, when wordline 54 turns off and does not select the row of memory cell, PMOS is brilliant Body pipe turns off, at voltage V_DDACurrent source 57 provide necessary electric current so that memory cell 57 to be maintained at its respective logic State.In view of current technology, for the required electricity from current source 57 of the single file of the memory cell in standby mode Stream is in every bit 1-10pA scope.

What Fig. 5 C showed the memory cell 57 for having cross-couplings IGCT in crosspoint array treats electromechanics Stream source is arranged.In this embodiment, the negative electrode of IGCT is connected to paratope line to 53A, 53B, the anode connection of IGCT To wordline 54.Current source 51 is connected to wordline 54 by PMOS transistor 59.In standby mode, PMOS transistor 59 turns on, electricity Maintenance electric current is supplied to memory cell 57 by wordline 54 and is flowed out by bit line 53A, 53B by stream source 51.When to by NAND When the address signal conducting PMOS transistor 56 of the decoder that door represents and shutoff PMOS transistor 59, current source 51 and wordline 54 Disconnect, wordline 54 is increased to wordline and selects voltage, by V_{WL_SE}L represents, for read or write.

Fig. 5 D shows the memorizer list for having cross-couplings IGCT in crosspoint array being similar to Fig. 5 C Another standby current source of unit 57 is arranged.But in this embodiment, the anode of IGCT be connected to paratope line to 53A, 53B, the negative electrode of IGCT is connected to wordline 54.Current source is current sink 52 now, is connected to wordline 54.At standby mode In, PMOS transistor 59 turns on, and current sink 57 pulls maintenance electric current from bit line 53A, 53B by memory cell 57 to be passed through Unit 57 also exports wordline 54.When turning on PMOS transistor 56 to the address signal of the decoder represented by NAND gate and turning off During PMOS transistor 59, current sink 52 disconnects with wordline 54, wordline 54 is increased to wordline and selects voltage, be used for reading or writing Operation.

It should be noted that the layout shown in Fig. 5 C and 5D provides the electric current more than a wordline in crosspoint array Source/absorber.On the contrary, current source/absorber can be used for the block with many wordline.In a similar fashion, Fig. 6 show for There is the current source circuit of the block of the memory cell of fixed power source voltage.See Fig. 5 B.In figure 6, current source 68 is in block The multirow of memory cell provides electric current.When selecting particular row, i.e. during wordline 64, the second MOS transistor 69 turns off with by electric current Source 68 disconnects with power line 66, and the first MOS transistor 66 turns on to move power line 66 to voltage V_DDA.Do not selecting During particular row, the first MOS transistor 66 turns off, and power line 66 is connected at voltage V by the second MOS transistor 69_DDACurrent source 68.Current source 68 supplies current to the block of several row of non-selected memory cell；At the present art, total current is about 1 μ Α.Compared to the current source in 1nA scope, this current source is relatively easy to design.

G. there is the cross-couplings IGCT sram cell writing auxiliary circuit

In order to accelerate the operation of memory cell based on IGCT, memory cell can be added to by writing auxiliary circuit In.In the example of Fig. 7 A, the anode of the cross-couplings IGCT of memory cell 77 be connected respectively to paratope line to 73A and 73B, the negative electrode of IGCT connects wordline 74.Two PMOS transistor 76A and 76B are connected respectively to PNP transistor 70A and 70B Emitter region and collector area.That is, the source/drain regions of PMOS transistor 76A (76B) is connected to PNP transistor 70A (70B) emitter region, i.e. the anode of cross-couplings IGCT, or one part, the of PMOS transistor 76A (76B) Two source/drain regions are connected to the collector area of PNP transistor 70A (70B), or one part.PMOS transistor 76A and The grid of 76B is connected to write boost line 75.It is connected to write boost line 75 additionally, two capacitor 78A and 78B each have Terminal；Other terminals of each capacitor 78A and 78B are connected respectively to the base region/NPN of PNP transistor 70A and 70B The collector area of 71A and 71B of transistor.

When the signal write in boost line 75 is low, the p-type emitter region of PMOS transistor 76A short-circuit transistor 70A And collector area.Equally, the p-type emitter region of PMOS transistor 76B short-circuit transistor 70B and collector area.N-type carrier from The base region of transistor 70A and 70B is respectively driven to capacitor 78A and 78B.Write auxiliary transistor 76A and 76B to provide from each crystalline substance The anode of brake tube is to its P type trap zone (PNP transistor 70A, the collector area of 70B and the base region of NPN transistor 71A, 71B) Conductive path.If IGCT " turns off ", then its shallow well, PNP transistor 70A, the base region/NPN transistor 71A of 70B, The collector area of 71B be in high voltage-close to but the voltage that needs not be equal on anode.It is high enough that to obtain V_beBase stage- The value of emitter voltage conducts greater than background leakage insufficient for PNP transistor 70A, 70B.Equally, P type trap zone, PNP The collector area of transistor 70A, 70B and the base region of NPN transistor 71A, 71B be in low-voltage-close to but need not be equal to Voltage on negative electrode.It is of a sufficiently low so that V_beValue insufficient for NPN transistor 71A, 71B conduct greater than background leakage Electric current.In order to make IGCT " turn on ", or the voltage of shallow n-type trap must be reduced to turn on PNP transistor 70A, 70B, or The voltage of p-type trap must be raised to turn on NPN transistor 71A, 71B.A kind of method is by voltage between the anode and cathode Increase to bigger value.Which increase the background leakage by PNP and NPN transistor, ultimately result in an IGCT composition Transistor " turns on ", and then device is sucked " conducting " state completely by the feedback circuit in IGCT.But this method needs big Anode-cathode voltage (can provide higher than cmos circuit) or (operate institute than SRAM executing the alive long write time The length needed).

Therefore, PMOS transistor 76A, 76B are added to assist the write operation of " conducting " state.When executing from anode to negative electrode Add normal operating voltage (about 1.2～1.4V), and the voltage on the grid of MOS transistor is of a sufficiently low to turn on PMOS transistor Time, at anode voltage and p-type trap, between PNP transistor 70A, the collector area of 70B and the base region of NPN transistor 71A, 71B Conducting path is provided.Voltage on p-type trap is pulled upward to anode by this conducting path, and leads when it reaches normal PN-diode During energising pressure, NPN base-emitter junction (p-type trap is to negative electrode) starts conduction, turns on NPN transistor 71A, 71B, subsequently brilliant lock It is played into " conducting " state completely by the feedback of pipe.

If IGCT is in " conducting " state, shallow n-type trap, PNP transistor 70A, the base region/NPN transistor of 70B The voltage of the collector area of 71A, 71B is relatively low (being enough to be arranged in " conducting " state PNP transistor 70A, 70B), and P Type trap, the base region of PNP transistor 70A, the collector area of 70B and NPN transistor 71A, 71B is of a relatively high (is enough to NPN brilliant Body pipe 71A, 71B are arranged in " conducting " state).

In order to IGCT being transformed into " shutoff " state it may first have to by the voltage between anode and negative electrode is reduced to Of a sufficiently low voltage is to eliminate the base of PNP (NW is to anode) transistor 70A, 70B and NPN (PW is to negative electrode) transistor 71A, 71B " conducting " forward bias of pole-emitter junction stops the DC current flows by IGCT.But this is inadequate.Although it is logical Cross the electric current flowing of IGCT to stop due to the voltage that reducing between anode and negative electrode, but be stored in PNP transistor The N-type base of 70A, 70B and PNP transistor 70A, a large amount of electric charges (minority carrier) of p-type base region of 70B, it is intrinsic Hold them in and be very close to but slightly below PNP and the V of NPN device_beFiring point.If anode-cathode voltage increases again Greatly, these knot forward bias the most again, IGCT returns " conducting ".Therefore, in the case of there is no " auxiliary ", brilliant lock Pipe preferably must be held in this and " turns off " state, the time look the most all storage electric charge by background leakage and restructuring dissipate.

Write auxiliary pmos transistor 76A, 76B to help from IGCT p-type trap, PNP transistor 70A, 70B collector area/ Electric charge is removed in the base region of NPN transistor 71A, 71B.In " being written as turning off " operation, the voltage on negative electrode is driven high to close Or the even above voltage on anode.By the electric charge being stored in p-type trap, this passes through Capacitance Coupled by the electricity in p-type trap Pressure is shifted onto higher than the voltage on anode.Thus, when the drop-down grid writing auxiliary pmos transistor 76A, 76B and capacitor turn on Time, the electric charge that be will be stored in p-type trap by PMOS transistor 76A, 76B is discharged to anode, and it makes between p-type trap and anode Pressure drop be significantly less than NPN base-emitter conducting voltage V_be.At shallow n-type trap, PNP transistor 70A, the base region/NPN of 70B The collector area of transistor 37A, 37B still stores electric charge to be dealt with.But p-type trap is put by PMOS transistor 76A, 76B Electricity, the overall redistribution help of the voltage in PNPN IGCT lamination shortens shallow n-type trap and reaches IGCT remains " pass Disconnected " voltage needed for time.

The memory cell of Fig. 7 A has two cross-couplings IGCTs, and the shallow n-type trap of an IGCT is connected to another Individual p-type trap.In this structure, IGCT " turns on " all the time and another IGCT " turns off " all the time." turn on " crystalline substance " low " voltage of p-type trap during " low " shallow n-type trap strengthens " shutoff " IGCT in brake tube, vice versa.Writing to memory cell Operation actually includes carrying out two IGCT writes simultaneously-by arranging complete access voltage and " conducting " " shutoff " across it IGCT, meanwhile, by being positioned proximate to 0V and the IGCT of " shutoff " " conducting " across it.Store at cross-couplings IGCT In this example of device unit, wordline 74 is connected to two negative electrodes, and BL/BL_N line 73A, 73B are connected to respective anode.Connect Bit line 73A, 73B to " conducting " IGCT anode is low, and bit line 73A, 73B of being connected to " shutoff " IGCT anode are height. This arranges maximum available conducting voltage across " shutoff " IGCT, across " conducting " IGCT arrange of a sufficiently low pressure drop (～ 0.2-0.3V) to turn off the flowing of its electric current.Meanwhile, drop-down 2 PMOS write the voltage on the grid of auxiliary transistor 76A and 76B So that they can operate as discussed above.But by increasing the cross-couplings of two IGCTs, exist for removing storage The extra path of the electric charge in " shutoff " IGCT-i.e., by the interconnection of the IGCT to conducting.Almost with above-mentioned Accurate way connects " shutoff " IGCT.PMOS writes the conducting of auxiliary transistor 76A, 76B and provides for by " low " p-type trap Move the path of anode voltage to, turn on NPN transistor 71A, 71B.This actually spends slightly long-time, because this PMOS crystal Pipe now has to not only pull up the p-type trap in " shutoff " IGCT, in cross-connect cable to be passed through pull-up " conducting " IGCT Shallow n-type trap.But in doing so, eliminate the electric charge being stored in this shallow n-type trap.Thus, in order to turn on " shutoff " NPN Transistor 71A, 71B temporal little beyond brought in order to eliminate be stored in " conducting " IGCT PNP transistor 70B, The temporal big improvement of the electric charge in the base stage of 70A.Along with " shutoff " NPN transistor 71A, 71B turns on, its collector current Drop-down " shutoff " PNP transistor 70A, the base stage (shallow n-type trap) of 70B, turn on PNP transistor 70A, 70B, subsequently its colelctor electrode electricity Stream is supplied to the base stage of NPN transistor 71A, 71B, strengthens " conducting " state (i.e.-IGCT feedback circuit).Meanwhile, newly turn on " high " p-type trap of collector current the most drop-down " conducting " IGCT of NPN transistor 71A, 71B, remove the electric charge of its storage And strengthen the achievement of " shutoff " this IGCT completely.The cross-couplings of all two IGCTs solves the single crystalline substance of above-mentioned separation Writing rate problem in brake tube.

Capacitor, such as shown in Fig. 7 A, it is also possible to be used in and write auxiliary operation.As shown in capacitor 78A and 78B, Write the shallow n-type well region of boost line 75 and IGCT, PNP transistor 70A, the current collection of base region/NPN transistor 37A, 37B of 70B Electric capacity is added between polar region.In theory can be by voltage shift dynamic condenser being coupled from the conversion that rises or falls writing boost line 75 These capacitors are utilized in shallow n-type trap.Write boost line 75 decline conversion with write auxiliary 75 lines on voltage change one A little percentage ratios will be pushed into low voltage under shallow n-type trap.This percentage ratio is total with what shallow n-type trap was stood by writing auxiliary grid electric capacity The ratio of electric capacity determines.If IGCT is in " shutoff " state, on shallow n-type trap, this coupling downwards of voltage increases PNP transistor 70A, the V of 70B_beAmount, this can aid in conducting thyristor, causes IGCT from " shutoff " to " conducting " shape The conversion of state.

On the contrary, if IGCT is in " conducting " state, writes the rising in boost line 75 and change with some percentage ratios (as above Described) voltage is coupled up in shallow n-type trap.Voltage between anode and the negative electrode of " conducting " IGCT has been decreased to Close to 0V or even negative voltage, and in the write operation that stopped of the electric current flowing through " conducting " IGCT, IGCT is not true Just " turn off ", because electric charge is still stored in shallow n-type well region (PNP transistor 70A, the base stage of 70B) and P type trap zone (NPN transistor The base stage of 71A, 71B) in.After the flowing cut-out of DC electric current, the effect upwards coupled of shallow n-type trap voltage assists in removing and is stored in Some electric charges in shallow n-type trap, thus help real " shutoff " IGCT.

Exemplified with the read and write operation of crosspoint array of memory cell 77 of Fig. 7 A in Fig. 7 B and 7C.Also imply example Show for standby condition.In these exemplary operations, digital " 0 " and " 1 " read from respectively and write the first of array In row first and the 3rd memory cell 77.Being similar to the memory cell of Fig. 7 A, Fig. 7 D shows for crosspoint array Cross-couplings IGCT memory cell.In this illustration, the anode of cross-couplings IGCT is connected to wordline 74, brilliant lock The negative electrode of pipe is connected respectively to paratope line 73A, 73B.Exemplified with the memorizer voltage 77 for Fig. 7 D in Fig. 7 E and 7F The read and write operation of crosspoint array, digital " 0 " and " 1 " read from respectively and write in the first row of array first and the 3rd Memory cell 77.Also, it should be noted that shown magnitude of voltage represents the scope of numerical value, for the most preferably operation shown in illustration. Optimum depends on the concrete property of the device of integrated circuit.

Figure 36 and following etc. exemplified with structure and the manufacture method with the memory cell writing auxiliary MOS (FET).

H. there is the sram cell of monocrystalline brake tube

The memory cell including single IGCT can also be used.Fig. 8 A and 8B shows monocrystalline brake tube SRAM memory Some base structures of unit.Fig. 8 A shows one embodiment of the present of invention, and wherein, memory cell has by being connected to V_DD High power supply voltage line with at V_SSLow supply voltage line between PNP transistor 80 and NPN transistor 81 represent IGCT. Single bit line 83 is connected to the current collection of the base region/NPN transistor 81 of PNP transistor 80 by selection NMOS (FET) transistor 82 Polar region.The grid of nmos pass transistor 82 is connected to wordline 84.Fig. 8 B shows an alternative embodiment of the invention.In the case Eliminate selection transistor, so that the emitter region of PNP transistor 80 is directly connected to wordline 84, sending out of NPN transistor 81 Emitter region is connected to bit line 83.

I. there is the monocrystalline brake tube sram cell writing auxiliary transistor

Monocrystalline brake tube memory cell can be arranged in many structures.Fig. 9 A shows monocrystalline brake tube memory cell, Wherein, IGCT anode is connected to bit line, and negative electrode is connected to wordline.In order to speed operations, write auxiliary MOS transistor for two and connect To IGCT.PMOS writes auxiliary transistor 96 and has the source/drain of the anode being connected to IGCT, and is connected to PNP crystal Second source/drain of the base region of the collector area/NPN transistor 91 of pipe 90.Its MOS transistor grid is connected to write auxiliary Line 95B.NMOS writes the base region that auxiliary transistor 98 is connected to the collector area/PNP transistor 90 of negative electrode and NPN transistor 91 Source/drain.Its grid is connected to another and writes boost line 95A.Fig. 9 B shows another monocrystalline lock being similar to Fig. 9 A Pipe memory cell.In this illustration, the anode of IGCT is connected to wordline, and negative electrode is connected to bit line.Two MOS crystal Pipe, PMOS transistor and nmos pass transistor, it is connected to IGCT, serves as and write auxiliary transistor, such as the memorizer list for Fig. 9 A Described in unit.

The memory cell of Fig. 9 D shows monocrystalline brake tube, and its anode is connected to bit line, and negative electrode is connected to wordline.Have even Receive the source/drain of anode, and be connected to the second source of the base region of the collector area/NPN transistor 91 of PNP transistor 90 Single PMOS transistor 96 of pole/drain electrode is served as and is write auxiliary transistor.The grid of PMOS transistor 96 is connected to singly write boost line 95. It is contrary that Fig. 9 H shows that another monocrystalline brake tube memory cell, its anode and negative electrode connect compared with Fig. 9 D.

J. the standby operation of the power reduction of monocrystalline brake tube sram cell it is used for

In crosspoint array, the operation of single thyristor cell is very similar to aforesaid cross-couplings IGCT memorizer list The operation of unit.In standby, single bit line 93, BL, be maintained at its " be pre-charged " level (if it is 0V that BL is connected to negative electrode, as Really BL is connected to the anode of IGCT is array " high " voltage (～1.4V)).Wordline 94, WL, keeps medium voltage, and it be enough to tie up Hold " conducting " state " turning on " IGCT in memory array, but of a sufficiently low will be flowed by the electric current of " conducting " IGCT It is maintained at the floor level in the scope of a few micromicroampere of every bit or tens micromicroamperes.This is the most tractable, because Cancel the electric current that in selecting, cancellation select row draws and be now dependent on the quantity of " conducting " unit comprised in this row.By intersection Coupling thyristor cell, each unit has " conducting " IGCT and " shutoff " IGCT all the time, and all row are treated Dynamo-electric stream is the most identical, and this allows to preset, with foregoing, the standby current that constant-current source provides necessary.

By single thyristor cell, the memory cell with digit order number D=1 has single " shutoff " IGCT, has The memory cell of digit order number D=0 has single " conducting " IGCT, all standby in the total current drawn be now dependent on depositing Storing up the data pattern in being expert at, therefore the constant-current source described in other parts cannot correctly work.If constant-current source is for protecting row Hold in standby, it is provided that if constant current must sufficiently large to provide the whole unit in row all " turn on " time required electricity Stream, otherwise, the voltage in wordline can be pulled too far to bit-line voltage by the Current draw of whole unit, at least some list on row Unit can lack electric current, is finally turned to " shutoff " state.If but the current source supplying standby middle wordline is sent in whole unit Electric current required when " turning on ", there will be problem when many unit actually turn off.In the electric current being to provide more than by " leading Logical " electric current of unit pull-out, this makes WL voltage away from BL voltage, increases the pressure drop of unit in row.This is not result in Standby current draws problem, because the electric current under worst case when total current " turns on " still equal to whole unit.On being expert at only Only a few or be likely not to have when unit is in " conducting " state and go wrong.In the case, word line voltage is moved to always The supply voltage being connected to the opposite side of current source (if bit line is connected to memory cell negative electrode, is about～the battle array of 1.4V Row " high " voltage, if or bit line be connected to memory cell anode, for 0V).This can tolerate in a period of time (perhaps microsecond more than 100, but be exposed to this complete pressure drop across unit the most for a long time and ultimately result in " shutoff " unit It is turned to " conducting " state, disturbs the data in memory array.

Therefore, by single thyristor cell, if current source is to control waiting condition (i.e.-wordline WL voltage), then By must provide for some species of " clamp " on the line of driven with current sources, its prevent the standby voltage in wordline increase (if word Line WL is connected to the IGCT anode of unit) or reduce (if wordline WL is connected to the IGCT negative electrode of unit) exceed holding Minimal disturbances voltage during little or no " conducting " unit in unit group in standby.This " clamps " by some grid ground cloudy Ground type device (FET or BJT) composition, its conducting when standby voltage strides across appointment threshold value, shunting subsequently is fallen by standby constant-current source The unwanted currents provided.Such as, Fig. 9 C shows that standby current source is arranged, for having monocrystalline brake tube in crosspoint array Memory cell.In this embodiment, the negative electrode of unit IGCT is connected to bit line 93, and the anode of IGCT is connected to wordline 94.Current source 100 is connected to wordline 94 by PMOS transistor 99.In another embodiment (not shown), unit line and word The anode of line and negative electrode connect contrary.The method of another more strength employs analog voltage actuator, such as operational amplifier, By standby voltage compared with reference voltage, and activate shunting transistor (FET or BJT) when exceeding reference voltage.

K. the read and write operation in single thyristor cell

In read operation, the operation of single thyristor cell is identical with cross-couplings thyristor cell.Before selecting wordline WL, Bit line precharge BL (if wordline is connected to memory cell IGCT anode, it is low (participating in Fig. 9 B and 9H), if wordline It is connected to IGCT negative electrode then for high (participating in Fig. 9 A and 9D)), keep subsequently floating.Select wordline WL subsequently.If it is selected Unit is " shutoff ", just keeps floating at pre-charge voltage by bit line BL.If selected unit is " conducting ", just by selected Bit line BL is pulled to WL voltage by " conducting " IGCT selecting unit.Participate in Fig. 9 E and 9I, be respectively used to the memorizer of Fig. 9 D and 9H The representative voltage of some of the read operation of array.

In write operation, it is written as conducting operation and is connected to " shutoff " IGCT in cross-couplings IGCT memory cell Bit line BL identical.It ((if wordline is connected to IGCT anode, is low that bit line BL is driven into the voltage contrary with wordline WL (participating in Fig. 9 B and 9H), if wordline is connected to IGCT negative electrode, is high (participating in Fig. 9 A and 9D)), write boost line by reduction On voltage and turn on PMOS and write auxiliary transistor 96 (participating in Fig. 9 D).Unit is turned to conducting state, just as describe above As.

Operation is turned off for being written as in single thyristor cell, in order to help electric charge in removal cross-couplings thyristor cell Useful cross-couplings effect no longer exist.It practice, be written as turning on and be written as to turn off operation to be isolated into two independent electricity Pressure bias scheme.It is being written as turning off in operation, selected bit line BL is being driven and selects voltage (if wordline is even to normal character line WL Receiving unit anode is then～1.0V, if wordline is connected to unit cathodes, to be～0.2V), as cross-couplings IGCT list Element array is the same.Difference is, also selected wordline WL is driven to close to or at the medium voltage of standby level.This is across list Unit is applied with negative anode-cathode voltage, so that leakage current is maximum, it is intended to dissipate and be stored in shallow n-type trap, PNP transistor Electric charge in the collector area of the base region/NPN transistor 91 of 90.PMOS writes auxiliary transistor 96 allows work with from above-mentioned crystalline substance The p-type trap of brake tube, electric charge is removed in the base region of the collector area/NPN transistor 91 of PNP transistor 90.

Therefore, perform the write operation in data pattern to row in two stages, in a single stage, wordline WL is driven Move selection voltage, selected bit line BL is driven into pre-charge level, so that " shutoff " unit is overturn as " conducting ".Subsequently, Wordline WL is converted to complete switch off voltage (being not only standby level), and bit line BL selected by " another " is driven into and is pre-charged electricity Flat contrary voltage, to overturn " conducting " unit as " shutoff ".When writing " conducting " on selected bit line, non-selected bit line (including the BL being written as " shutoff " subsequently) needs are driven into close to WL level to prevent non-selected " shutoff " unit on row from turning over Transfer " conducting " to.Subsequently, when writing " shutoff " on bit line selected by " another ", non-selected bit line (includes just being written as " leading Logical " BL) need to be driven into pre-charge level to prevent non-selected " conducting " unit upset on row for " shutoff " state.At this In the case of individual second, wordline WL voltage is set close to some intermediate level of standby voltage, so that in " conducting " unit Enough electric currents are had to run with the holding unit when writing auxiliary higher level and turning on.This is cross point memory " semi-selection " situation.

Fig. 9 F and 9G shows some representativenesses of the described two benches write operation of the memory cell array for Fig. 9 D Voltage.Fig. 9 J and 9K shows some representative electricity of the described two benches write operation of the memory cell array for Fig. 9 H Pressure.

L. the write operation of the power reduction of monocrystalline brake tube sram cell it is used for

Can have benefited from the write operation that the monocrystalline brake tube memory cell of " shutoff " " turns on " being previously described for intersection coupling The write operation of the power reduction of synthetic brake tube sram cell.In above write operation illustrates, it is connected to be written as " conducting " state The bit line of " shutoff " IGCT memory cell remain height, to guarantee that IGCT receives during write operation pulse persistance Capitalization voltage is with " conducting " IGCT.Once IGCT " turns on ", while the bit line of IGCT remains height, new " conducting " IGCT maximum " conducting " electric current of conduction.Which increase the power consumption during write operation.The more important thing is, wordline must be from this All unit on row send away electric current so that this electric current can be the biggest.This may result in the edge of the resistance due to line The notable pressure drop of wordline, and may result in instability in memory arrays.

This situation can be changed by the bit line to " shutoff " IGCT being precharged as height before write pulse Kind, mode is similar to above-mentioned read operation shown in Fig. 9 L.Fig. 9 M is the voltage of multiple positions of the memory cell at Fig. 9 L Represent figure.After precharging, turn off precharge and " float " with permission bit line, until memory cell rollover states.At this point, lead to Bit line is dragged down (being similar to read operation) by the electric current crossing new " conducting " IGCT.Along with bit-line voltage declines, across the pressure of IGCT Fall reduces, and electric current keeps electric current to decline to minimum.This has three benefits.First, peak point current reduces, because bit-line voltage is being deposited Begin to decline before the builtin voltage of storage unit " conducting " IGCT completely.Secondly, present short duration current is (in Fig. 9 M I_ThyLShape shown in) power that consumes in reduction write operation.3rd, due to from the perspective of statistics, when different Between upset be written into the multiple unit in row, peak point current in wordline reduces and extends in bigger time interval, enters One step makes the undesirable voltage along wordline decline minimum.

Fig. 9 N is exemplified with the low-power write operation for single thyristor cell, wherein, compared to Fig. 9 L, to wordline and position The connection of line is contrary.That is, the memory cell of Fig. 9 N has the anode being connected to wordline and the negative electrode being connected to bit line.Fig. 9 O is The expression figure of voltage of multiple positions at the memory cell of Fig. 9 N.In this illustration, before write pulse, to " shutoff " The bit line of IGCT is precharged as low (being similar to read operation).Subsequently, turn off precharge path and " float " with permission bit line, until Memory cell rollover states.At this point, by the electric current of new " conducting " IGCT, bit line is drawn high (being similar to read operation).With Bit line to raise, the pressure drop across IGCT reduces, and electric current keeps electric current to decline to minimum.Achieve identical with described in leading portion Benefit.First, peak point current reduces, because bit-line voltage is before builtin voltage " conducting " IGCT completely of memory cell Start to raise.Secondly, the present short duration current (I in Fig. 9 O_ThyLShape shown in) merit that consumes in reduction write operation Rate.3rd, owing to, from the perspective of statistics, being written into the multiple unit in row, in wordline in different time upsets Peak point current reduces and extends in bigger time interval, further such that the undesirable voltage along wordline declines minimum.

II. integrated circuit structure and the explanation of manufacture

Above-mentioned memory cell can use existing manufacturing technology manufacture.

Without new semiconductor manufacturing operation, eliminate the expense relevant to new process exploitation step and complexity.As One starting point, Figure 10 is exemplified with the basic step in currently commonly used CMOS technology.Figure 10 is exemplified with using p conduction Known prior art complementary metal oxide semiconductors (CMOS) (CMOS) technique of type substrate.In the discussion below, shown in Figure 10 Process be referred to herein as " standard CMOS process." process starts from the formation of the annulus (not shown) of insulant, typically It is silicon dioxide, in order to semiconductor region is isolated from each other before forming transistor in the substrate.(discuss this mistake below in conjunction with Figure 11 Journey.) Figure 10 is exemplified with such isolation area.The most as shown in step 1, at one layer of dioxy of P conduction type silicon Grown SiClx, it is provided that field oxide.

It follows that in step 2, utilize traditional semiconductor fabrication, the field oxide upper limit fixed one layer photic anti- Erosion agent (not shown), removes field oxide with the real position being now to be formed N-conductivity trap.Subsequently, ion implanting or other public affairs The technology known, injects substrate to limit N-type trap by N-conductivity impurity.

As shown in following step 4, perform another mask operation to expose the position of substrate and nmos pass transistor to be formed Put.Gate oxide is formed subsequently in this part and N-type trap of substrate.The outward appearance of structure in this stage of process Shown by step 5.As illustrated in step 6, the surface of quasiconductor deposits one layer of polysilicon.This layer will eventually become complementation The grid of MOS transistor.

Use another mask operation, many to be formed for the source electrode of complementary MOS transistor and the position etching of drain electrode Crystal silicon layer and gate oxide level are to remove them.The outward appearance of this structure shows in step 7.It follows that in the operation separated The source electrode of transistor that formed will be used for and the N-conductivity of drain electrode and P conductive-type impurity inject in substrate.This shows in step 8.

On body structure surface, deposit the such as dielectric layer such as silicon dioxide or silicon nitride subsequently, and etch, to expose for arriving The position of the ohm contact of source electrode and drain electrode.These operations show in step 9 and 10.As shown in step 11, subsequently in structure The metal level of such as aluminum or other conductive materials is deposited, to provide source electrode and drain electrode and the electrical connection of grid on surface.? After, as designated by step 12, etching metal is to provide the metal interconnection of CMOS transistor.

A. shallow-trench isolation

Figure 11 is exemplified with the known processes for forming shallow trench oxidation thing isolation area in integrated circuits.At the most many figures In show these regions.Such as, the region 111 in Figure 13.Process as shown in figure 11, and similar change, commonly referred to as For shallow-trench isolation, and it is preferable over the technology being commonly called local oxidation of silicon (LOCOS) in the past.In shallow slot technique, at silicon The upper surface of substrate forms the thin layer of silicon dioxide, is followed by silicon nitride layer thereon.Use photoresist subsequently, to limit The region of shallow slot to be formed.The composite bed of silicon oxide, silicon nitride and photoresist is illustrated as the monolayer 170 in Figure 11 A.Uncommon Hope position etching groove 171 for isolation area in substrate, as shown in Figure 11 B.Oxygen before chemical-mechanical planarization subsequently Change groove, with silica-filled it.For the sram cell of the present invention, the conventional trench isolation process being modified slightly can be optional Ground preferably isolates between the buried N-type trap serving as IGCT negative electrode.The most each at this depositing conformal oxide or nitride Anisotropy etches with the wall 172 forming silicon dioxide on the sidewalls of the trench.If it is required, by optional P conductivity type With the p type island region that offer is buried in impurity 173 injecting structure, for improving the isolation of " bucket " that formed between groove.This mistake Journey is followed by conventional groove and fills and planarization.

B. bipolar transistor

Next explanation develops from the collateral line of above-mentioned sram cell based on IGCT.Following sram cell preferably employs Bipolar transistor, is typically embodied by the IGCT formed by the PNP merged and NPN bipolar transistor.To this end, we are first Preferred implementation for bipolar transistor and its process of manufacture are described.Figure 12 is exemplified with using CMOS technology manufacture Semiconductor structure in the cross section of bipolar transistor/IGCT.Use CMOS technology to manufacture bipolar transistor pair at this Advantageous particularly in preferred embodiment.This method achieves and forms CMOS logic electricity on conventional substrate with high speed bipolar type SRAM Road, such as, provide the cache memory for this logic circuit, it is not necessary to more complicated and expensive BiCMOS technique skill Art.

Structure shown in Figure 12 includes the P type substrate 110 with shallow trench isolation region 111.

Annular shallow slot shading ring shown in the cross section of Figure 12, around the region 121 of substrate, wherein arranges ambipolar crystalline substance Body pipe.The cross section of other isolation areas of the front and back of shown in not being shown that in fig. 12, they will be partly This district of conductor isolates with other parts of chip.Isolation 121 defines the side of " bucket " in substrate, has by buried N The bottom of the bucket that conductive type well 112 limits.Buried N-conductivity trap 112 preferably injects substrate by silicon and trench isolations 111 In.Bucket 121 electric isolution is formed at therein active or passive device.

Note, in the embodiment shown, can be formed into hidden by a part of isolation area of extension 111 N-type layer below Burying the electric contact 114 of N-conductivity trap 112, to engage more highly doped n-type region 114, it provides trap from semiconductor surface The electrical contact of 112.In alternative embodiments, in contact 11 is arranged on ring-shaped groove isolation area 111.In isolation area 121 Also this contact of buried N-conductivity trap 112 it is formed into.

The N-type region 115 of strong doping provides the emitter stage of vertical bipolar transistor, and region 113 provides base stage, region 112 Colelctor electrode is provided.Hard contact 119,118 and 120 is provided respectively to the electrical connection of emitter stage, base stage and colelctor electrode.Region 117 It is untapped (virtual) CMOS gate district, the separation spacing in each assembly limiting bipolar transistor shown in Figure 12. The purpose in these dummy gate districts it is discussed further below in conjunction with accompanying drawing.

Figure 13 is the flow chart exemplified with the step manufactured during the semiconductor structure shown in Figure 11.This process starts The formation of the channel separating zone in step 125, above in conjunction with described in Figure 11.It follows that in step 126, perform relatively In the operation 1 and 2 described in Figure 10.Shelter as shown in step 127 subsequently and inject buried N-type trap 112.In Figure 14 A in more detail The step for of showing, injecting exemplified with photoresist mask 114 and N-type trap, it provides wordline (or other merits the most at last Can).Perform step 128 subsequently with implanting p-type trap 113, the most as shown in Figure 14 B.

It follows that as shown in step 129, perform to form field-effect transistor grid according to each step 5 in Figure 10,6 and 7 The traditional cmos process of pole.In the illustration of Figure 14 C, thus the grid formed includes gate oxide 136, conductive electrode 137 (typical polysilicon) and nitride spacer layer 138.Gate regions includes residual nitrogen SiClx 138, and it is sheltered in known manner And remain in after etching away nitration case on the sidewall of gate electrode 137.

But it is essential that the FET grid formed by this process and gate oxide after a while need not during us Make gate electrode.On the contrary, grid is used for providing " hard mask ", and it is later used to realize emitter bipolar transistor and transistor The autoregistration doping of base contact.As shown in Figure 14 C, photoresist mask 134 is for protecting the side of gate regions, and sends out Emitter injection is incorporated into the opposite side of grid 137.With N-type source and the leakage forming MOS transistor on the same integrated circuit The most identical operation is injected this N-conductivity bipolar emitter 115.Note, grid 137 hard mask formed provides The left hand edge of photoresist 134, its position in have wide tolerance limit, i.e. this left hand edge can on grid anyly Side is sagging, but still protection base stage contact regions 116 protects against the N type dopant of emitter stage 115.In following multiple embodiments In, use " virtual " gate electrode to limit the interval between not same district.But can be appreciated that, be actually not necessarily forming grid electricity Pole.On the contrary, it is possible to use silicon dioxide/silicon nitride sandwich, or other layers.Use gate electrode an advantage be with On the integrated the identical process operations of the grid that other positions form CMOS logic forms this electrode.

With reference to Figure 14 D, in the step 131 of Figure 13, introduce the pickup injection 116 of p-type base stage.Owing to using emitter stage doping, Use dummy gate realizes the big tolerance limit of the position of the right hand edge of photoresist 139.Bipolar base connect as in Figure 14 by Shown in base contact district 116.Traditional cmos process is used subsequently to provide in multiple districts as required metal electrical connection.Following example Show the example that these metals connect.

C. lateral bipolar transistor

Replacing vertical bipolar transistor, Figure 15, exemplified with one embodiment of the present of invention, which provides horizontal NPN double Bipolar transistor.This realizes with the collector area 140 being additionally formed in Figure 15, just now by using identical N-type to inject Procedure described above is injected by this N-type and forms emitter stage 115.In the outside of shown ring-shaped groove isolation or except figure This district of cross section beyond shown in 15 one is internally formed the electric contact of p-type trap base region.

Owing to they need more substrate surface area, lateral bipolar transistor has the base width of increase, therefore It is generally of more worse performance than vertical bipolar transistor.But it is in some application that the quantity of masking steps is important, horizontal It is favourable to bipolar transistor.

Figure 16 is exemplified with the process for forming structure shown in Figure 15.In the case of figure 16 and the most all follow-up attached In figure, do not illustrate to be formed the step of trench isolations, but carry out before the process shown in flow chart in the drawings.Additionally, this In no longer illustrate such as to be formed the conventional steps of the CMOS technology of hard contact, as shown in Figure 10.

The bipolar transistor that d.NMOS FET merges

Figure 17 A-17D is exemplified with the process for forming the nmos pass transistor merged with vertical NPN bipolar transistor.This Individual structure may be used in the many application in addition to SRAMs, such as, and voltage controlled oscillator, phase-locked loop circuit, amplifier etc.. PMOS and/or the NMOS structure cognizing merged arrives, when we use at the CMOS NFET/PFET self-aligned source/drain electrode of standard When making surface connection (the P+ anode, N+ shallow N-trap connects, and P+P-trap connects) that sequence is limited to bipolar junction transistor in order, at BJT Consequent " the unexpected FET " formed between terminal may be advantageously used with the operation-in this paper institute strengthening BJT circuit When stating, assist the write operation of IGCT as above.

With same way described above, Figure 17 A is exemplified with the injection of the buried N-type trap by becoming NPN collector, figure 17B is to provide the injection of the shallow p-type trap of NPN base stage.In Figure 17 C, having formed FET gate regions, it plays the effect of mask, For nmos source and the injection of the N-type impurity of drain electrode.As shown in figure 17d, this N type dopant also forms vertical bipolar crystal The emitter stage 163 of pipe and collector driving point 161.Dividing between collector driving point and emitter stage is set up in virtual mos gate pole 162 From.Region 163 and 165 is nmos pass transistor source electrode and drain electrode, has (function) grid 164.Inject 166 offers vertical to being formed The connection of the p type island region of the base stage of NPN transistor.NPN collector 167 is provided by buried N-type trap.

E. there is FET and select the sram cell of transistor

Figure 18 A and 18B is exemplified with the sram cell of cross section, and its circuit theory diagrams illustrate in figure 3b.Sram cell by Two pairs of cross-couplings bipolar transistors select transistor composition with the MOS being coupled to wordline.Structure shown in Figure 18 A is formed In the bucket isolated by shallow trench isolation region, and the structure shown in Figure 18 B is formed in adjacent bucket.Between two buckets Connect the metal interconnection shown by the top of each at Figure 18 A and 18B to provide, and according to by the double-headed arrow between them Generally connect indicates.In Figure 18 A, the supply voltage V that first layer metal 182 provides_DDAnd between PNP emitter region 186 Connection.Other Disengagement zone of first metal 182 provide the connection 188 between transistor base.Buried N-type well region 184 The connection of the emitter stage of NPN transistor is provided to.Electrically connecting by this region 185 on the left of figure to this buried N-type trap Separation contact provides, and at this, buried trap extends under channel separating zone.

Second metal level 181 provides the electrical connection of shallow n-type trap, shallow n-type trap provide NPN transistor 186 base stage and NMOS selects a node of transistor 187.Second metal level 181 is additionally provided in the base stage of PNP transistor 188 and selects with NMOS Another between another node of transistor 189 connects (in the unshowned cross section of Figure 18 A or 18B).Metal three Layer 180 provides the bit line of sram cell to connect, and the bit line shown in Figure 18 A is coupled to the one of the ambipolar centering of cross-couplings Individual, in Figure 18, the bit line shown in B is coupled to another of the ambipolar centering of cross-couplings.Figure 19 is the top view of sram cell, Exemplified with its layout on the integrated.

Figure 20 A-20D is exemplified with the more detailed part for forming the process of sram cell shown in figure 18 above and 19.As Shown in Figure 20 A, forming buried N-type trap to provide V_SSAfter connection, by the opening implanting p-type in photoresist mask PR Trap.Subsequently, as shown in fig. 20b, use another mask, perform N-type and inject to generate shallow n-type trap.As shown in Figure 20 C, in shape Become the dummy gate district of ambipolar (left) side for structure and behind the functional gate district of FET (right) side of structure, lead with N Electricity type impurity injects N-type source and the drain electrode of NPN bipolar emitter pole FET in one operation.After this step, such as Figure 20 D Shown in, perform the suitable injection sheltering to realize P-type dopant, to form other electrodes of ambipolar (IGCT) device. The step for other positions the most on the integrated form PFET source electrode and drain electrode.Result is compact quick sram cell, It uses FET as selecting transistor.

F. there is the sram cell of ambipolar selection transistor

Figure 21 A and 21B is exemplified with the cross section of sram cell, wherein, by the bipolar transistor transistor that elects. (Fig. 3 A is the circuit theory diagrams of this unit.) as, in draw above, the device shown in the cross section of Figure 21 A is formed at In one bucket, the device shown in the cross section of Figure 21 B is formed in adjacent bucket, has therebetween metal interconnection.Figure 21 A and The left part of 21B is corresponding to bipolar structure (wherein, the MOS transistor crystal that elects described in Figure 18 A and 18B Pipe).The right part of Figure 21 A and 21B replaces the FET shown in Figure 18 A and 18B exemplified with the ambipolar selection transistor of use. Those shown in these ambipolar selection transistors circuit theory diagrams corresponding to Fig. 3 A.In Figure 21 A and 21B, select crystalline substance Body pipe is vertical NPN bipolar transistor.Emitter stage 200, base stage 201 and colelctor electrode 202 form a NPN and select transistor. Strong doping N-conductivity region is for providing the connection of buried N-type trap 202, and it also provides for bit line.Certainly, vertical PNP is ambipolar Transistor or lateral bipolar transistor are also used as selecting transistor.

Figure 22 shows the top view of the sram cell of Figure 21 A and 21B.Can use relative to Figure 18 and following etc. Described technological process operation manufactures sram cell.Figure 23 A-23E shows in greater detail and specifically shelters and implantation step. As shown in fig. 23 a, after forming shallow trench isolation region, deep buried N-type trap is injected.Subsequently, as shown in fig. 23b, behaviour is suitably being sheltered After work, perform shallow p-type trap and inject.It follows that as shown in fig. 23 c, shallow n-type trap is injected only in of one of shallow P type trap zone In Fen, thus it it is the contact leaving space to p-type trap after a while.As shown in fig. 23d, other positions on the integrated are formed After virtual FET grid and function FET grid, performing suitable masking steps, N-type is injected and is used for the ambipolar crystalline substance of vertical NPN that adulterates The emitter stage of body pipe, and the source electrode of the nmos pass transistor of other positions and drain electrode on substrate.Subsequently, as shown in Figure 23 E, separately After one masking steps, implanting p-type adulterant is to form the p-type emitter stage of PNP bipolar signal transistor and to be positioned on substrate The source electrode of the PMOS transistor of other positions and drain electrode.

E. the sram cell in deep trap

Figure 24 is exemplified with an alternative embodiment of the invention, wherein, uses deep n-type trap to form SRAM cell structure.In order to More effectively operating, ambipolar sram cell is preferably above the voltage of standard logic core voltage, as previously mentioned.Realize its one Individual method is to use such as the high voltage of SRAM power supply, such as V_DDIOOr it is obtained from V_DDIOVoltage, i.e. use 28 current nanometers The about 1.5-2.5 volt of the technology of design rule.Figure 24 is exemplified with another scheme.In this scheme, in substrate 220 Deep p-type trap in deep n-type trap 221 is formed sram cell.This allows negative bias p-type trap 222.By ambipolar selection crystal Pipe, this scheme allows word line driving circuit to use core logic level, such as, from the voltage swing of 0 volt to 1.0 volt. Deep strong doped region 223 is for providing the electrical contact of deep n-type trap 221.It is firstly introduced into deep n-type trap and injects 221, doped p-type subsequently Trap 222 forms the structure shown in Figure 31.Semiconductor processes as above can form sram cell subsequently.In process one In the individual suitable stage, heavily doped injection is for providing the connection 223 of deep n-type trap 221.

F. three layer transistor SRAM unit

Figure 25 is the cross section of 3 layer transistor SRAM units, and its circuit theory diagrams illustrate in fig. 8 a.This unit has friendship Fork coupling NPN and PNP bipolar transistor, they are shown in figure left part.MOS selects transistor to show on the right side of diagram Side.Power supply V_DD230 emitter stages being coupled to PNP transistor, and connect through buried N-type trap 232 and be coupled to NPN transistor Colelctor electrode.Wordline 233 is coupled to the grid of MOS transistor, and bit line 234 is coupled to an electrode of MOS transistor.First The N-type base stage of PNP transistor is coupled to another electrode of MOS transistor by the connection 235 in layer metal.Show on the right side of figure For being close to the wordline 236 of the sram cell of shown sram cell.

Figure 26 is the top view of the layout of 3 layer transistor SRAM units shown in Figure 25.Give corresponding with shown in Figure 26 The reference marker that the region in the region in Figure 25 is identical with Figure 25.

G. four layer transistor SRAM unit

Figure 27 A and 27B is the cross-sectional view of two positions at 4 layer transistor SRAM units.This structure with relative to Figure 18 Described is almost identical.But with that Structure Comparison, the structure of Figure 27 A and 27B uses buried N-type trap 240 to provide wordline, only Need double layer of metal rather than three layers.Fig. 4 A shows the circuit diagram for 4 transistor units.Bit line (Figure 27 B) and Paratope line (Figure 27 A) is coupled to the emitter stage 242 of PNP bipolar transistor.The arrow of labelling " M1 " illustrates to use first Layer metal provides between the base stage and the colelctor electrode of NPN transistor of PNP transistor and at the base stage of NPN transistor and PNP Cross-couplings between the colelctor electrode of transistor.Figure 28 is the top view of structure shown in Figure 27 A and 27B.

H. there is the four layer transistor SRAM unit writing auxiliary FET

Figure 29 A and 29B assists FET exemplified with having additionally writing described in circuit diagram shown in front combination Fig. 7 The cross-sectional view of 4 layer transistor SRAM units of 250.Write auxiliary FET 250 (PMOS transistor 46A in Fig. 7 and 46B) in conducting Time, colelctor electrode is shorted to the base stage of lateral PNP bipolar transistor.Figure also illustrates that and above-mentioned writes auxiliary capacitor 251 (capacitor 47A and 47B in Fig. 7).Figure 30 is the top view of structure shown in Figure 29 A and 29B.

G. two transistor sram cell

Figure 31 is the cross-sectional view of two bipolar transistor memory cells, it is provided that write auxiliary FET with the shortest Connect bipolar transistor for writing data.Element circuit is discussed above relative to Fig. 9 B.Upper PNP transistor bag in Figure 31 Including emitter stage 281, base stage 282 and colelctor electrode 283, having can the grid (PFET) 284 of short circuit emitter and collector.Similar Ground, lower NPN transistor includes colelctor electrode 284, base stage 285 and emitter stage 286.Grid (NFET) can be with short circuit emitter stage and current collection Pole.Noting, PNP base stage 282 is cross-coupled to NPN collector 284 by shallow n-type trap, and p-type trap is by NPN base stage 285 cross-couplings To PNP emitter stage 281.Buried N-type trap 288 and the coupling 289 to the second metal level thereof provide bit line, and wordline is coupled to PNP Emitter stage.In wordline alternate embodiment on bottom, wordline is coupled to NPN collector.Structure shown in Figure 31 The process being relevant to described in Figure 18 can be used to manufacture.

I. manufacturing process details

Figure 32 is exemplified with the details of the manufacturing process used in whole above-mentioned multiple embodiments.Specifically, use CMOS technology, during the grid of MOS transistor may be used for forming bipolar transistor.CMOS technology is used to limit Fixed grid polar region, is not used as grid, and these districts may be used for limiting the interval in multiple bipolar transistor area under control.In Figure 32, the One " virtual " grid 260 is for being arranged on the interval between n-type doping emitter stage 261 and neighbouring p-type doped region 262.With class As mode, another " virtual " grid 263 is for being limited to for the p-type doped contact district 264 of trap and p-type doped region 262 Between interval.This technology allows to use CMOS technology technology to form bipolar transistor, but still makes those ambipolar District is other desired region autoregistrations multiple with integrated circuit.

Figure 33 is the song of the Typical dopant concentrations exemplified with the vertical bipolar transistor being relevant to described in the figures above Line chart.The figure illustrates the net doping in multiple regions for forming the bipolar transistor in the preferred embodiments of the present invention.

Propose this explanation of the present invention for the purpose of illustration and description.It is not intended to exhaustive or will The present invention is limited to described precise forms, according to above teaching, many modifications and variations are possible.Select and illustrate Embodiment is to explain the principle of the present invention and actual application thereof best.This explanation makes those skilled in the art can be many Utilize best and put into practice the present invention in individual embodiment and by the multiple amendments being suitable for specific use.The scope of the present invention It is determined by the claims that follow.

Claims

1. in there is the integrated circuit of array of the memory cell interconnected by multiple bit lines and wordline, each memorizer list Unit all includes:

At least one IGCT, at least one IGCT described have the first quasiconductor terminal region and the second quasiconductor terminal region with And first middle semiconductor region and the second middle semiconductor region, described the first terminal district is connected to bit line or wordline, and described Second terminal region is connected to described wordline or described bit line, and the first mesozone adjoins described the first terminal district, and described second Mesozone adjoins described first mesozone and described second terminal region, described terminal region and described mesozone and has pole alternately Property；

Mosfet transistor, described mosfet transistor has: be connected to the gate terminal of control line；It is connected to described IGCT The first terminal district or first source/drain regions of part in the first terminal district of described IGCT；Be connected to and institute State mesozone that the first terminal district of IGCT do not adjoins or adjacent with the first terminal district of described IGCT described in Second source/drain regions of the part of mesozone；

Wherein, described mosfet transistor provides power path, for charging and discharging, described IGCT district to accelerate State the write operation of memory cell.

Memory cell the most according to claim 1, wherein, described multiple bit lines includes multiple paratope line pair, and Wherein, described memory cell farther includes:

Second IGCT, described second IGCT has in the first quasiconductor terminal region and the second quasiconductor terminal region and first Between semiconductor region and the second middle semiconductor region, described the first terminal district is connected to paratope line or wordline, and described second Terminal region is connected to wordline or described paratope line, and the first mesozone adjoins in the middle of described the first terminal district, and described second District adjoins described first mesozone and described second terminal region, and described terminal and mesozone have polarity alternately, and described first Mesozone is connected to the second mesozone of described first IGCT, and described second mesozone is connected to described first IGCT The first mesozone so that described first IGCT and described second IGCT cross-couplings；

Second mosfet transistor, described second mosfet transistor has: be connected to the gate terminal of control line；It is connected to institute State the first source/drain of the part in the first terminal district of the second IGCT or the first terminal district of described second IGCT District；Be connected to the mesozone that do not adjoins with the first terminal district of described second IGCT or with described second IGCT Second source/drain regions of the part of the described mesozone that the first terminal district is not adjacent；

Wherein, described second mosfet transistor provides power path, for the first IGCT district described in charging and discharging and described Second IGCT district, to accelerate the write operation of described memory cell.

Memory cell the most according to claim 2, wherein, the first terminal district of two IGCTs includes anode, and Second terminal region of two IGCTs includes that negative electrode, the anode of described first IGCT are connected to a position of paratope line centering Line, the anode of described second IGCT is connected to another bit lines of described paratope line centering, and described first IGCT It is connected to described wordline with the negative electrode of the second IGCT.

Memory cell the most according to claim 3, wherein, described first mosfet transistor and the 2nd MOSFET crystal Pipe includes PMOS transistor.

Memory cell the most according to claim 4, farther includes:

First capacitor, described first capacitor be connected to the first mesozone of described first IGCT and described control line it Between；And

Second capacitor, described second capacitor be connected to the first mesozone of described second IGCT and described control line it Between.

Memory cell the most according to claim 1, wherein, described at least one IGCT facing by 55nm or finer Ungraduated ruler cun limits.

Memory cell the most according to claim 2, wherein, the first terminal district of two IGCTs includes anode, and It is described that second terminal region of two IGCTs includes that negative electrode, the anode of described first IGCT and described second IGCT are connected to Wordline, the negative electrode of described first IGCT is connected to a bit lines of paratope line centering, and the moon of described second IGCT Pole is connected to another bit lines of described paratope line centering.

Memory cell the most according to claim 7, wherein, described first mosfet transistor and the 2nd MOSFET crystal Pipe includes PMOS transistor.

Memory cell the most according to claim 1, wherein, the first terminal district of at least one IGCT described includes sun Pole, and the second terminal region of at least one IGCT described includes that negative electrode, described anode are connected to described bit line, and described Negative electrode is connected to described wordline.

Memory cell the most according to claim 9, wherein, described mosfet transistor includes PMOS transistor.

11. memory cells according to claim 9, farther include:

Second mosfet transistor, described second mosfet transistor has: be connected to the gate terminal of the second control line；Connect To the second terminal region of described IGCT or the first source/drain regions of the part of the second terminal region of described IGCT； The mesozone not adjoined with the second terminal region being connected to described IGCT or the second terminal region of described IGCT are not Second source/drain regions of the part of adjacent described mesozone.

12. memory cells according to claim 11, wherein, described second mosfet transistor includes NMOS crystal Pipe.

13. memory cells according to claim 11, wherein, the first terminal district of at least one IGCT described includes Anode, and the second terminal region of at least one IGCT described includes that negative electrode, described anode are connected to described wordline, and institute State negative electrode and be connected to described bit line.

14. memory cells according to claim 13, wherein, described mosfet transistor includes PMOS transistor.

15. memory cells according to claim 13, farther include:

Second mosfet transistor, described second mosfet transistor has: be connected to the gate terminal of the second control line；Connect To the second terminal region of described IGCT or the first source/drain regions of the part of the second terminal region of described IGCT； The mesozone that do not adjoins with the second terminal region being connected to described IGCT or the second terminal region with described IGCT Second source/drain regions of the part of not adjacent described mesozone.

16. memory cells according to claim 15, wherein, described second mosfet transistor includes NMOS crystal Pipe.

17. 1 kinds of methods writing sram cell, for having the SRAM memory list interconnected by multiple bit lines and a plurality of wordline The integrated circuit of the array of unit, each sram cell has at least one IGCT, and in cross point is arranged, each is brilliant Brake tube all has anode and the negative electrode being connected to bit line and wordline；First mesozone adjacent with described anode；With described The second mesozone between one mesozone and described negative electrode, described anode, negative electrode and mesozone have polarity alternately, described side Method includes:

Select at least one sram cell；

Selected sram cell will be written in response to logic state, the described bit line of selected sram cell and described word will be connected to Line is driven into voltage betwixt, with at least one IGCT described in sram cell selected by or off；And

During actuation step, it is provided that the conducting pathway between the described anode and the second mesozone of at least one IGCT described Footpath, so that electric charge is injected in described second mesozone, or removes electric charge from described second mesozone；

Thereby assist in: make at least one turn on thyristors described in selected SRAM or shutoff, and accelerate selected SRAM The write of unit.

18. methods according to claim 17, wherein, in described array, the anode of each sram cell is all connected to position In line, and described array, the negative electrode of each sram cell is all connected to wordline.

19. methods according to claim 17, wherein, the anode of each sram cell in described array is all connected to The negative electrode of each sram cell in wordline, and described array is all connected to bit line.

20. methods according to claim 17, wherein, conducting path provides step to include: described in making to be connected at least one Mosfet transistor conducting between described anode and described second mesozone of individual IGCT.

21. methods according to claim 20, wherein, described mosfet transistor includes PMOS transistor.

22. methods according to claim 17, wherein, described multiple bit lines includes multiple paratope line pair, and wherein, Each sram cell has the second IGCT further, and described second IGCT has: be connected to paratope line or wordline Anode and be connected to wordline or the negative electrode of described paratope line；First mesozone of described second IGCT be connected to described at least Second mesozone of one IGCT；And the second mesozone of described second IGCT is connected at least one IGCT described The first mesozone so that two IGCT cross-couplings, the method for said write sram cell farther includes:

Selected sram cell will be written in response to logic state, with in selected sram cell described at least one is brilliant The described paratope line and described wordline that are connected to selected sram cell simultaneously, are driven into and are used for institute by the actuation step of brake tube State the bit line in the actuation step of at least one IGCT and wordline voltage complementary, voltage therebetween so that selected SRAM Described second IGCT in unit turns off or conducting；And

Conducting path is provided between the anode and the second mesozone of described second IGCT, so that will during actuation step Electric charge removes from the second mesozone of described second IGCT or charges injection into described the second of described second IGCT Mesozone.

23. methods according to claim 22, wherein, the anode of each sram cell in described array is all connected to The negative electrode of each sram cell in bit line or its paratope line, and described array is all connected to wordline.

24. methods according to claim 22, wherein, the anode of each sram cell in described array is all connected to The negative electrode of each sram cell in wordline, and described array is all connected to bit line or its paratope line.

25. methods according to claim 22, wherein, conducting path provides step to include: make to be connected to described second brilliant The second mosfet transistor conducting between anode and described second mesozone of brake tube.

26. methods according to claim 25, wherein, described second mosfet transistor includes PMOS transistor.

27. methods according to claim 2, wherein, the anode of an IGCT is connected to described paratope line centering One bit lines, the anode of another IGCT is connected to another bit lines of described paratope line centering, and two IGCTs Negative electrode be all connected to described wordline.

28. methods according to claim 2, wherein, the anode of two IGCTs is all connected to described wordline, a brilliant lock The negative electrode of pipe is connected to a bit lines of described paratope line centering, and the negative electrode of another IGCT is connected to described paratope line Another bit lines of centering.