CN102971797B

CN102971797B - The semiconductor memory component floating body transistor containing conducting, semiconductor memory component has non-permanent and permanent function and operational approach

Info

Publication number: CN102971797B
Application number: CN201180017951.4A
Authority: CN
Inventors: 于妮尔图·维佳佳; 子威·霍巴赫
Original assignee: Zeno Semiconductor Inc
Current assignee: Zeno Semiconductor Inc
Priority date: 2010-02-07
Filing date: 2011-02-07
Publication date: 2016-12-14
Anticipated expiration: 2031-02-07

Abstract

A kind of semiconductor memory cell, is made up of following assemblies: be configured to be charged to the floater area of an instruction state of memory cells level；The firstth district of making electrical contact with is carried out with above-mentioned floater area；The secondth that make electrical contact with and spaced apart with the firstth above-mentioned district district is carried out with above-mentioned floater area；Grid between the firstth above-mentioned district and the secondth district.Said units is multilevel-cell.Also disclose the memory cell array for manufacturing memory subassembly.The method additionally providing operation memory element.

Description

Semiconductor memory component-containing the floating body transistor of conducting, semiconductor memory component-tool There are non-permanent and permanent function and operational approach

Cross reference

This patent benefits from US provisional patent No.61/302129 (date of filling on February 7th, 2010), and the U.S. SProvisional Patent No.61/425820 (date of filling 2010 on December 22)；Above-mentioned patent is included in this specially the most by reference of text In profit, according to United States code (U.S.C.) volume 35, the 119th chapter, we enjoys the priority for above-mentioned patent.

This invention patent also quotes in full: patent number No.12/797320 (date of filling on June 9th, 2010), The patent of entitled " semiconductor memory-contain conducting floating body transistor "；Patent number No.12/797334 (date of filling 2010 6 The moon 9), the patent of entitled " holding semiconductor memory-contain the method turning on floating body transistor state "；Patent number No.12/ 897528, the patent of entitled " the compact semiconductor device containing lesser amt contact, operation and manufacture method "；Patent number No.12/897516, the patent of entitled " containing the semiconductor subassembly of conducting floating body transistor "；And patent number 12/897/538, The patent of entitled " containing the semiconductor memory component of conducting floating body transistor ".

The field of this invention

This invention is relevant with semiconductor memory technology.Specifically, this invention with containing conducting floating body transistor it Semiconductor memory component is relevant, and this semiconductor memory component contains impermanency memory function and permanent storage function.

The background of this invention

Semiconductor memory assembly is specifically used to store data.Static and dynamic random stores (SRAM and DRAM) to be had extensively Application.SRAM generally includes 6 transistors, and chip size is bigger.But, different from DRAM, it need not by fixed Phase refresh operation keeps the storing state of self.Tradition dram chip is a transistor and the knot of an electric capacity (1T/1C) Structure.Due to constantly reducing of 1T/1C storage chip, constant just the becoming of capacitance keeping required is increasingly difficult to.

The most just propose the floater effect that can conduct electricity based on DRAM (see " the 1T-DRAM chip without electric capacity " 85-87 Page, S.Okhonin etc., IEEE electronic building brick communication, in February, 2002, volume 23, second；And " on SOI, use one The storage design of individual transistor drain chip " the 152-153 page, technical digest (Tech.Digest), within 2002, the IEEE world is solid State circuit meeting, in February, 2002).Above-mentioned storage eliminates the electric capacity of tradition 1T/1C storage chip, thus is easier to obtain more Little unit sizes.It addition, this storage chip is compared with the 1T/1C storage chip of tradition, it is possible to realize less chip chi Very little.But, different from SRAM, this DRAM storage chip need nonetheless remain for refresh operation, because the electric charge of storage can produce in time Raw leakage.

The 1T/1C DRAM refresh operation of tradition includes the state first reading storage chip, then uses identical data Storage chip re-writes.Therefore, two steps should be needed by " read-write " refresh operation: read and write.During refreshing, store core Sheet is to access it.One is had " automatically to refresh " method, it is not required that first to read the state of storage chip, in United States Patent (USP) Disclosed in No.7170807 (Fazan etc.).But this operation need nonetheless remain for, when refreshing chip, interrupting the access to chip.

It addition, after read operation repeatedly, the electric charge in buoyancy aid DRAM storage chip can reduce accordingly.This minimizing Situation caused by electric charge pump (charge pump) effect of buoyancy aid electric charge, buoyancy aid electric charge attracted to surface gathering and connects Mouthful.(see " the instantaneous charge pump charging principle of partially depleted SOI MOSFET " the 279-281 page, S.Okhonin etc., IEEE telecommunications, volume 23 the 5th, in May, 2002)

Therefore, just someone will need a kind of semiconductor memory assembly and operational approach so that need not interrupt reading to store core The access of sheet, it becomes possible to keep the storage chip state of semiconductor memory assembly.

The most just may require that a kind of semiconductor memory assembly and identical operational approach so that store up after read operation repeatedly The state depositing chip still can keep.

Persistent storage component, such as flash memory erasable can programming read-only storage (flash eprom) assembly, even can Enough holding data in the case of power-off.But, compared with impermanency storage assembly, persistent storage component generally operates relatively Slowly.

Flash memory storage assembly, typically utilizes the floating gate polysilicon storage as permanent data.Thus existing it On standard MOS (CMOS) Process ba-sis, add extra processing step.In United States Patent (USP) 2010/ In 0172184 asymmetric monomer polymerization MOS permanent storage chip, (the artificial Roizin of license etc.) describe a kind of single The forming method of body polymerization persistent storage component.Similar with a lot of persistent storage component, this chip stores than impermanency Assembly operation is slower.It addition, persistent storage component has been only capable of the limited working cycle, i.e. there is the limit of exhaustion run System.

Corresponding it, people are also desirable to produce a kind of universal storage assembly, it is possible to have concurrently impermanency and The advantage of persistent storage component；Compare favourably as speed of operation can store with impermanency, if power-off, it is possible to lasting guarantor Deposit data.It addition, desirably can produce a kind of versatility storage assembly, size can't be more impermanent than corresponding Property or permanent big to accepting, the most also there is storage volume quite.

This invention i.e. disclosure satisfy that the demand, as detailed below.

This invention summary

In this invention, on the one hand need a kind of method, it is possible to do not interrupt the access to storage chip, and keep storage Deposit the state of chip；The method includes: applying a reverse bias on chip, the electric charge balancing out chip buoyancy aid is let out Leakage, the current potential of buoyancy aid is i.e. the state of storage chip；Access chip simultaneously.

In at least one example, being biased and include to one of chip electrode applying reverse biased, this electrode is not Addressing for chip.

In at least one example, the reverse biased of applying is constant positive bias.

In at least one example, the reverse biased of applying is recurrent pulses form positive voltages.

In at least one example, the maximum potential that can store in buoyancy aid has become big (owing to being applied with instead to chip To bias) so that bin window is the biggest.

In at least one example, the reverse biased of applying has carried out keeping operation on chip, and concrete grammar includes same Time on chip, perform read operation (keeping operation simultaneously).

In at least one example, chip is multilamellar, and buoyancy aid, by storing multiple positions, is set so as to show multiple shape State, method particularly includes: determine chip status by detection chip electric current.

On the other hand, in this invention, it is proposed that a kind of method of operation storage arrays, storage arrays is by going storage core Sheet and row storage chip composition, the most each storage chip has a floating body region, is used for storing data；Method particularly includes: At least to selected chip not same a line or with string all chips perform keep operation；Then selected core is accessed Sheet, and perform read or write on selected chip, simultaneously the most at least to all with selected chip not same a line or with string it Chip performs to keep operation.

In at least one example, operation is kept to include: to perform to keep operation on all chips, simultaneously at selected chip Upper execution read or write (includes reading selected chip).

In at least one example, keeping operation to realize by applying reverse biased on electrode, this electrode is not stored up Deposit chip addressing to use.

In at least one example, electrode is after segmentation, it is allowed to the selected part of storage chip array is carried out independence Reverse biased control.

In at least one example, the execution of operation is kept to include: on all chips outside selected chip, to perform guarantor Hold operation, selected chip performs read or write (being wherein included on selected chip the operation of write " 0 ")；Simultaneously in choosing When determining to write " 0 " on chip, all with selected chip with the electrode of a line, the chip being connected is also carried out writing " 0 " operation.

In at least one example, in write " 0 " operation performing this individual digit, keep operation including one, I.e. carrying out keeping operation on all non-selected chips, carrying out read or write on selected chip (is included in selected core simultaneously " 0 " is write) on sheet.

In at least one example, operation is kept to include: to perform to keep operation on all non-selected chips, simultaneously in choosing Determine on chip, to perform read or write (being included on selected chip write " 1 ").

In at least one example, maintain operation in all unit (except on chosen unit) and carry out, simultaneously in choosing Carry out read or write (write operation is multilamellar write operation) on fixed unit, operate with and be alternately written into and verification algorithm.

In at least one example, operation is kept to include: to perform to keep operation on all non-selected chips, simultaneously in choosing Determine on chip, to perform a read or write (being included on selected chip the write operation performing a multilamellar), this multilamellar write operation Including: apply a ramp voltage to selected chip, perform write operation；Read by the curent change of the selected chip of detection Chip status；The curent change once selecting chip reaches predetermined value, just removes ramp voltage.

In at least one example, operation is kept to include: to perform to keep operation on all non-selected chips, simultaneously in choosing Determine on chip, to perform a read or write (being included on selected chip the write operation performing a multilamellar), this multilamellar write operation Including: apply a slope current to selected chip, perform write operation；By the selected chip bit line (bit line) of detection and Change in voltage between source line (source line), reads chip status；The change in voltage once selecting chip reaches predetermined Value, just removes slope current.

In at least one example, multilamellar write operation allows digital stage to select one of selected chip numeral.

In at least one example, operation is kept to include: to perform to keep operation on all non-selected chips, simultaneously in choosing Determine to perform on chip a single/multiple read or write, the wherein each layer in the single or multiple lift on selected chip Execution write operation includes: apply a ramp voltage on selected chip to realize write operation；Being selected by detection can on chip The electrode of addressing reads the state of selected chip；Benchmark storage chip is used to verify the state of write operation.

In at least one example, concrete grammar includes: before performing write operation, uses " reading then checking " operation The state of benchmark storage chip is set.

In at least one example, the state arranging benchmark storage chip is included in setting when powering to storage chip array State.

On the other hand, in this invention, it is proposed that a kind of method of operation storage arrays, storage arrays is by going storage core Sheet and row storage chip composition, the most each storage chip has a floating body region, is used for storing data；Concrete grammar bag Include: at least refresh the state of one of them storage chip；At least access wherein another one storage chip, wherein another is stored The access of chip will not be refreshed operation disruption, and refresh operation does not attaches and carries out instead read and write operation.

In at least one example, at least a storage chip is Multi-layer Store chip.

On the other hand, in this invention, it is proposed that a kind of method of operation storage arrays, storage arrays is by going storage core Sheet and row storage chip composition, the most each storage chip has a floating body region, it is proposed that a kind of operation storage arrays it Method, storage arrays is made up of row storage chip and row storage chip, and the most each storage chip has a floating body region, uses In storing data；Concrete grammar includes: access the selected chip in storage chip；Selected storage chip performs one simultaneously Individual write and verification operation, and do not carry out instead read and write operation.

In at least one example, selected storage chip is Multi-layer Store chip.

In at least one example, the checking in " reading then checking " operation, part is by sensing the row side of storage arrays Curent change upwards realizes, and these row are connected with selected chip.

In at least one example, reading the checking in then verification operation, part is by sensing storage arrays trip side Curent change upwards realizes, and this row is connected with selected chip.

In at least one example, the part of writing of " writing then checking " operation includes using drain or grid ramp voltage.

In at least one example, the part of writing of " writing then checking " operation includes using drain slope voltage.

In this invention, it is proposed that a kind of integrated circuit, wherein contain a semiconductor memory chip chain/string, its In each storage chip comprise a floating body region, be used for store data；Chain or string comprise at least one contact, with storage chip At least one control row and be connected, the wherein quantity of contact and the quantity of storage chip is identical or fewer than number of chips.

In at least one example, the quantity of contact is less than the quantity of storage chip.

In at least one example, after semiconductor memory chip-in series, constitute string.

In at least one example, after semiconductor memory chip parallel connection, constitute chain.

In at least one example, integrated circuit manufactures on SOI (SOI) substrate.

In at least one example, integrated circuit manufactures on body silicon substrate.

In at least one example, the quantity of contact is 2, then the quantity of semiconductor memory chip is more than 2.

In at least one example, storage chip also includes the first and second conductive regions, is connected with floating body region.

In at least one example, the first and second conductive regions are shared by adjacent storage chip, due to each storage Chip all has adjacent storage chip.

In at least one example, each storage chip also includes first, second, and third conductive region, with floating body region It is connected.

In at least one example, each storage chip also includes a door, insulate with floating body region.

In at least one example, at least a storage chip is contactless storage chip.

In at least one example, major part storage chip is all contactless storage chip.

In at least one example, multibyte data is stored by storage chip.

On the other hand, in this invention, the integrated circuit of proposition includes paired contactless semiconductor memory chip, often Individual semiconductor memory chip includes: a floating body region, stores for data；First and second conductive regions, with floating body region It is connected；One door, is positioned on floating body region surface；And an insulating regions, door is insulated with floating body region.

In at least one example, contactless storage chip is connected.

In at least one example, contactless storage chip is in parallel.

In at least one example, integrated circuit includes at least one semiconductor memory chip, and this chip has one and touches Point, the sum of contact is less than the sum of storage chip, and storage chip includes storage chip and the oncontacting at least containing a contact The storage chip of point.

On the other hand, in this invention, integrated circuit includes: the semiconductor memory chip of pair of series, each partly leads Body storage chip includes: a floating body region, stores for data；First and second conductive regions, are connected with floating body region；One Individual door, is positioned on floating body region surface；And an insulating regions, door is insulated with floating body region.

In at least one example, at least a semiconductor memory chip is contactless semiconductor memory chip.

In at least one example, at least a contactless semiconductor memory chip includes another one conduction region Territory, is connected with floating body region.

On the other hand, in this invention, integrated circuit includes paired parallel semiconductor storage chip, each quasiconductor Storage chip includes: floating body region, stores for data；Conductive region, is connected with floating body region；One of on conductive region Door；Insulating regions, insulate buoyancy aid substrate regions with door；At least one of which semiconductor memory chip is contactless partly leading Body storage chip.

In at least one example, major part semiconductor memory chip is all contactless semiconductor memory chip.

In at least one example, integrated circuit includes a part of contact, and number of contacts is less than or equal to the number of storage chip Amount.

In at least one example, each storage chip also includes second conductive region, is connected with floating body region.

In at least one example, storage chip also includes second and the 3rd conductive region, is connected with floating body region.

On the other hand, in this invention, integrated circuit includes paired in parallel contactless semiconductor memory chip, each Semiconductor memory chip includes: a floating body region, stores for data；First and second conductive regions, with floating body region phase Even；One door, is positioned on floating body region surface；And an insulating regions, door is insulated with floating body region.

On the other hand, in this invention, integrated circuit includes: one stores string or chain, comprises one group of oncontacting and lead thirty Body storage chip；First contact, is connected with the first additional semiconductor memory chip；The most contactless semiconductor memory chip is permissible Accessed by the first contact.

In at least one example, integrated circuit also includes second contact, with the second additional semiconductor memory chip phase Even；The most contactless semiconductor memory chip can be accessed by the second contact.

In at least one example, contactless semiconductor memory chip becomes to be connected in series with additional semiconductor memory chip.

In at least one example, storage chip string or chain include the first storage chip string or chain, and by first group of group One of one-tenth group, integrated circuit also includes: second stores string or chain, comprise second group of contactless semiconductor memory chip；The Two contacts, are connected with the second additional semiconductor memory chip；Wherein second group of contactless semiconductor memory chip can be by the Two contacts access.

In at least one example, storage chip string or chain include the first storage chip string, and are formed it by first group One (storage chip) group, integrated circuit also includes: the second storage chip string, including second group of contactless semiconductor memory core Sheet；3rd contact, is connected with the 3rd additional semiconductor memory chip；4th contact, with the 4th additional quasiconductor storage Deposit chip to be connected；Wherein second group of contactless quasiconductor is slightly deposited chip and can be accessed by the third and fourth contact；Wherein first Organizing contactless semiconductor memory chip, the first additional semiconductor memory chip and the second additional semiconductor memory chip becomes series connection even Connect；And second group of contactless semiconductor memory chip, the 3rd additional semiconductor memory chip and the 4th additional semiconductor memory During chip is gone here and there second, one-tenth is connected in series.

In at least one example, integrated circuit also includes first electrode, is connected with the first contact and the 3rd contact； And second electrode, it is connected with the second contact；The 3rd electrode and the 4th contact is also had to be connected.

In at least one example, semiconductor memory chip is substantially made up of 2 dimension semiconductor memory chips.

In at least one example, semiconductor memory chip is substantially made up of fin, 3 D semiconductor storage chip.

In at least one example, first group of contactless semiconductor memory chip, with second group of contactless semiconductor memory Chip, side-by-side alignment；In first string, including first group of insulated part (the storage chip insulation by adjacent in first group), and Second group of insulated part (the storage chip insulation by adjacent in the first string and the second string)；Second string includes the 3rd group of insulated part (storage chip insulation adjacent in going here and there second)；And the 4th group of insulated part is (by storage adjacent in the second string and the first string Deposit chip insulation).

In at least one example, the first contact and the second contact lay respectively at the first and second ends of storage chip string.

In at least one example, a semiconductor memory chip includes: a floating body region, stores for data；The One and second conductive region, it is connected with floating body region；One door, is positioned on floating body region surface；And an insulating regions, Door is insulated with floating body region；And have a word line electrode, it is connected with door.

On the other hand, in this invention, integrated circuit includes paired buoyancy aid storage chip, serial or parallel connection.In storage Deposit the connection between chip for reducing the number of contacts of whole circuit.Owing to multiple storage chip are carried out serial or parallel connection, Need a small-sized storage chip array.

This feature of this invention and other features, for the people being familiar with related process, be clear and easy to understand it；Collection Circuit, string, chain storage chip and constructive method is become all to will be explained in greater detail below.

In this invention, semiconductor memory chip includes: substrate is the first conduction type；Electrode of substrate and substrate phase Even；First area embeds in substrate in the primary importance of substrate, has the second conduction type (N-type) simultaneously；One bit line electrode It is connected with first area with a source line electrode；In the second position of substrate, embedded in a second area, there is the second conduction Type, meanwhile, has the first conduction type, between the first and second positions, as non-the part (at least) of substrate The buoyancy aid of permanent storage, it is achieved data store；Bit line electrode additionally is connected with second area with source line electrode；The first He On the second position and substrate surface, there is a capture layer；Capture layer includes the first and second storage locations, is set to each The permanent data of independence stores, and wherein the first and second storage locations are respectively provided with for receiving the number of storage in impermanency According to；One is had to control door on capture layer.

In at least one example, surface includes a topsheet surface, and chip also includes an embedding layer, be positioned at substrate it Bottom, embedding layer is the second conduction type；There is an embedded type trap electrode, be connected with embedding layer.

In at least one example, buoyancy aid is surrounded by topsheet surface, the first and second regions and embedding layer completely.

In at least one example, the first conduction type is " p " type, and the second conduction type is " n " type.

In at least one example, semiconductor memory chip also includes insulating barrier, surrounds the side surface of substrate.

In at least one example, chip is used as multilayer chiop.

In at least one example, in the first and second storage locations at least one arrange satisfied: one of them storage Deposit position and can store the data more than a byte respectively.

In at least one example, arranging of buoyancy aid is satisfied: can store the data more than a byte wherein.

On the other hand, in this invention, the operational approach of chip needs: a storage chip device, have paired it Storage chip, and each storage chip is containing a buoyancy aid, it is possible to store as impermanency data, in addition it is also necessary to one Capture layer, has the first and second storage locations, stores as permanent data, specifically includes: when being energized to storage chip, Storage chip is stored as impermanency and operates；Disconnecting after storage chip power supply, reset in storage chip forever For a long time property stores, and to predetermined state, then performs shadow mirror image operation, is downloaded to containing within impermanency storage chip forever During property stores for a long time.

In at least one example, the method also includes: close storage chip assembly, when closed, storage chip assembly As flash memory, erasable, can the read-only storage of programming.

In at least one example, the method also includes: again recovers the power supply of storage chip, when restoring electricity, holds One recovering step of row, is downloaded to containing within permanent storage in permanent storage chip.

On the other hand, in this invention, operation storage chip assembly includes: storage assembly needs possess a pair storage core Sheet, each storage chip has a buoyancy aid, stores as impermanency data, the most also has a capture layer, is used as forever Property data store for a long time；And one of them storage chip is used as impermanency storage chip, with another one permanent storage core Sheet does not interfere with each other.

In at least one example, operation includes: apply a voltage, this chip surface in one of chip surface region Adjacent with the storage location of permanent storage.

In at least one example, at least one example, apply voltage and include: apply a forward voltage, chip Buoyancy aid there is P-type conduction type.

In at least one example, operation includes: operation impermanency stores, it is achieved one of read and write/holding operation Individual.

In at least one example, the method also includes: perform a reset operation, gives permanent storage one initial State.

In at least one example, method also includes: performs shadow mirror image operation, loads impermanent in permanent storage The content of property storage.

On the other hand, in this invention, semiconductor memory chip includes: floating body region, as the impermanency of data Store；One capture layer, as the permanent storage of data；The data being wherein stored in impermanency stores and permanent storage The data being stored in depositing are orthogonal, and floating body region can operate independent of capture layer, and capture layer can be independent of Floating body region performs operation.

In at least one example, floating body region is the first conduction type, is embedded in layer and surrounds, and embedding layer has second leads Electricity type is different from the first conduction type.

In at least one example, floating body region is bought in insulant and is surrounded.

In at least one example, floating body region builds on substrate, and chip also includes the insulating barrier surrounding substrate side surfaces.

In at least one example, chip is used as multilayer chiop.

In at least one example, capture layer includes the first and second storage locations, and the first and second storage locations are each It is configured to independently store data, as permanent storage.

In this invention, there is a poly floating door semiconductor memory chip, including: a substrate；One buoyancy aid Region, is positioned at the surface of substrate, is set to impermanency storage；One poly floating door, is set to store permanent data； One insulating regions, insulate floating body region and this poly floating door；First and second regions be positioned at respective position it Surface rather than the surface of floating body region；Wherein floating boom is positioned to allow for receiving the data from impermanency storage.

In at least one example, the first and second regions are asymmetric arrangement, and wherein the first area defines the firstth district The surface in territory, and second area defines the surface of second area, the first area is not equal to second area simultaneously.

In at least one example, there is higher coupling in one of first and second regions on above-mentioned surface with floating boom, Higher with coupling of floating boom than another one.

In at least one example, chip includes the embedding layer of base plate bottom, the conduction type of embedding layer and floating body region Conduction type different.

In at least one example, buoyancy aid is surrounded by topsheet surface, the first and second regions and embedding layer.

In at least one example, insulating barrier has surrounded the side of substrate.

In at least one example, the insulation material layer of embedment is positioned at the bottom of substrate.

In at least one example, buoyancy aid is by topsheet surface, the first and second regions, and embedded type insulation material layer.

In at least one example, floating boom covers one of buoyancy aid surface block area, in capped surface and first area Between second area, there is a space.

In at least one example, select door adjacent with independent multi-crystal silicon floating bar.

In at least one example, door is selected to overlap with floating boom.

On the other hand, in this invention, semiconductor memory chip includes: a substrate；One floating body region, is set to Impermanency stores；One grid permanent storage that changes, including a floating boom (adjacent with substrate), a control gate is (with floating boom phase Adjacent) so that floating boom can be arranged between control gate and substrate；One selects grid, adjacent with substrate and floating boom.

In at least one example, buoyancy aid is positioned at the surface of substrate, and chip also includes: the first and second regions are respectively positioned on respectively From surface rather than the surface of floating body region of position；Wherein, the first and second regions are asymmetric arrangement, first Amassing and define the first area area on surface, second area defines the second area area on surface；And the first area is not Equal to second area.

In at least one example, base plate bottom has an embedding layer, the conduction type of embedding layer to lead with floating body region Electricity type is different.

In at least one example, buoyancy aid is by the embedding layer bag of topsheet surface, the first and second regions and insulant Enclose.

On the other hand, in this invention, an independent polysilicon floating semiconductor storage chip includes: substrate, uses Floating body region, single polysilicon floating boom (as the permanent storage of data) is stored in the impermanency storing data；Wherein float Body region is used as the impermanency of data and stores, and the permanent storage independent of data works, and single polysilicon floating boom is then made For the permanent storage of data, independent of impermanency storage work.

On the other hand, in this invention, the operational approach of chip needs: a storage chip device, have paired it Storage chip, and each storage chip is containing a buoyancy aid, it is possible to store as impermanency data, in addition it is also necessary to one Floating boom, stores as permanent data, specifically includes: when being energized to storage chip, storage chip is stored up as impermanency Deposit into row operation；After disconnecting storage chip power supply, reset the permanent storage in storage chip, to predetermined state, so Rear execution shadow mirror image operation, is downloaded to containing within impermanency storage chip in permanent storage.

On the other hand, in this invention, operation storage chip assembly includes: a storage chip assembly, including a pair Storage chip, each storage chip contains a buoyancy aid, stores as impermanency data, and a floating boom, as permanent number According to storage, a control gate；And impermanency storage chip can be carried out data in integrated operation, with permanent storage without Close.

In at least one example, the method also includes: control gate is applied a voltage, makes to be positioned at the letter of floating boom bottom Region, road inverts, not by storing affecting of electric charge in floating boom.

In at least one example, the method also includes: apply one on the region that one of substrate is connected with floating boom Positive voltage, buoyancy aid is " p " conduction type.

In at least one example, the operation to storage chip entirety has included one of read and write/holding operation.

This feature of this invention and other features, for the people being familiar with related process, be clear and easy to understand it；Have Pass method, assembly and array all will be explained in greater detail below.

Brief description about drawing

Fig. 1 is the schematic diagram of storage chip in this invention example.

Fig. 2 is the schematic diagram constituting a storage assembly in this invention example after multiple chipsets synthesis array.

Fig. 3 is n-p-n dipole elements schematic diagram of molding in storage chip in this invention example.

Fig. 4 A displaying is in this invention example, the electrode of substrate segmentation in an array.

Fig. 4 B show is the multiplexer in this invention example, and multiplexer is applied to segmentation substrate electricity for determining The bias extremely gone up.

Fig. 4 C displaying is the voltage generator circuit of use in this invention example, and this circuit just inputs to multiplexer Bias.

Fig. 5 displaying is in this invention example, is stored in the maximum charge in a storage chip buoyancy aid, this maximum electricity Lotus amount can increase by increasing the forward bias of electrode of substrate.

Fig. 6 A is the floating body potential (for the function of buoyancy aid electric current) in this invention example and substrate potential.

Fig. 6 B is the floating body potential (for the function of buoyancy aid electric current) in this invention example and embedment trap.

Fig. 7 is that in the bias condition of selected storage chip in this invention example and storage arrays, unselected chip is partially Pressure situation.

Fig. 8 A is a unselected storage chip in this invention example, this storage chip and selected storage chip Having identical trip, icon is for selecting storage chip during read operation.

Fig. 8 B is in Fig. 8 A, the n-p-n dipole elements state of unselected storage chip, and icon is the reading of selected storage chip During operation.

Fig. 8 C is a unselected storage chip in Fig. 8 A, and this storage chip has identical with selected storage chip Row, icon for selected storage chip during read operation.

Fig. 8 D is in Fig. 8 A, the n-p-n dipole elements state of unselected storage chip (Fig. 8 C), and icon stores core for selected During the read operation of sheet.

Fig. 8 E is a unselected storage chip in Fig. 8 A, and this storage chip has different from selected storage chip Row and column, icon for selected storage chip during read operation.

Fig. 8 F is in Fig. 8 A, the n-p-n dipole elements state of unselected storage chip (Fig. 8 E), and icon stores core for selected During the read operation of sheet.

Fig. 9 is the schematic diagram in this invention example to storage chip write " 0 ".

Figure 10 is the citing of selected storage chip in this invention example, and unselected chip is write in storage arrays Enter the situation of " 0 " operation.

Figure 11 A is in this invention example, the citing of unselected storage chip bias condition, in write " 0 " the operation phase Between.

Figure 11 B is the equivalent circuit diagram of Figure 11 A chips, illustrates own n-p-n dipole elements.

Figure 12 is in this invention example, and in selected storage chip and array, the citing of unselected storage chip, is writing During entering " 0 " operation.

Figure 13 A is in this invention example, the citing of selected storage chip bias condition, during write " 0 " operation.

Figure 13 B is the equivalent circuit diagram of Figure 13 A chips, illustrates own n-p-n dipole elements.

Figure 13 C is the citing of bias condition on unselected chip in Figure 13 A, and this unselected chip has with selected chip Having identical trip, the time is during selected chip write " 0 " operation.

Figure 13 D is the equivalent circuit diagram of Figure 13 C chips, illustrates own n-p-n dipole elements.

Figure 13 E is the citing of bias condition on unselected chip in Figure 13 A, and this unselected chip has with selected chip Having identical trip, the time is during selected chip write " 0 " operation.

Figure 13 F is the equivalent circuit diagram of Figure 13 E chips, illustrates own n-p-n dipole elements.

Figure 13 G is the citing of bias condition on unselected chip in Figure 13 A, and this unselected chip has with selected chip Having the row and column of difference, the time is during selected chip write " 0 " operation.

Figure 13 H is the equivalent circuit diagram of Figure 13 G chips, illustrates own n-p-n dipole elements.

Figure 14 is in this invention example, and the citing of the bias condition of unselected chip in selected chip and array, right During selected chip carries out pipeline transmission write " 1 " operation of band-to-band.

Figure 15 A is the citing of selected chip bias condition in Figure 14.

Figure 15 B is the equivalent circuit diagram of Figure 15 A chips, illustrates own n-p-n dipole elements.

Figure 15 C is the citing of bias condition on unselected chip in Figure 15 A, and this unselected chip has with selected chip Having identical trip, the time is during selected chip write " 1 " operation.

Figure 15 D is the equivalent circuit diagram of Figure 15 C chips, illustrates own n-p-n dipole elements.

Figure 15 E is the citing of bias condition on unselected chip in Figure 15 A, and this unselected chip has with selected chip Having identical trip, the time is during selected chip write " 1 " operation.

Figure 15 F is the equivalent circuit diagram of Figure 15 E chips, illustrates own n-p-n dipole elements.

Figure 15 G is the citing of bias condition on unselected chip in Figure 15 A, and this unselected chip has with selected chip Having the row and column of difference, the time is during selected chip write " 0 " operation.

Figure 15 H is the equivalent circuit diagram of Figure 15 G chips, illustrates own n-p-n dipole elements.

Figure 16 A is in this invention example, reference generating circuit, is used for producing the initial Accumulation current of storage chip, storage Depositing chip, to be positioned at the same source being written into online.

Figure 16 B is this invention another one example, reference generating circuit, is used for producing the initial accumulated electricity of storage chip Stream, it is online that storage chip is positioned at the same source being written into.

Figure 16 C is this invention another one example, reference generating circuit, is used for producing the initial accumulated electricity of storage chip Stream, it is online that storage chip is positioned at the same source being written into.

Figure 17 is in this invention example, and the floating body potential of storage chip increases along with being biased, the increase of bias The hole on buoyancy aid will be caused to be injected into electronics.

Figure 18 A is reference generating circuit and read circuit in this invention example, is connected with storage arrays.

Figure 18 B is the voltage induced electric furnace in this invention example, this circuit arrange between source line and bit line electrode it Voltage measures.

Figure 19 is the bias condition of chosen chip in this invention example, during selected chip is carried out read operation.

Figure 20 is the bias condition of chosen chip in this invention example, and selected chip is writing " 0 " operation Period.

Figure 21 is the another one example of this invention, for the bias condition of chosen chip, is carrying out selected chip During write " 0 " operation.

Figure 22 is the another one example of this invention, for the bias condition of chosen chip, is carrying out selected chip When band-to-band tunnel transmission write " 1 " operation.

Figure 23 A is the schematic diagram of storage chip in this invention another one example.

Figure 23 B is the schematic diagram of storage chip in this invention example, shows substrate regions and the contact of embedment trap.

Figure 24 is the schematic diagram of storage chip array in Figure 23.

Figure 25 is the schematic diagram of n-p-n dipole elements in Figure 23.

Figure 26 is in this invention example, the citing of array bias condition, during to selected chip write " 0 " operation.

Figure 27 is the bias condition of chosen chip in this invention example, and selected chip is writing " 0 " operation Period.

Figure 28 A is the citing of selected chip bias condition in Figure 27.

Figure 28 B is the equivalent circuit diagram of Figure 28 A chips, illustrates own n-p-n dipole elements.

Figure 28 C is the citing of bias condition on unselected chip in Figure 27, and this unselected chip has with selected chip Having identical trip, the time is during selected chip write " 0 " operation.

Figure 28 D is the equivalent circuit diagram of Figure 28 C chips, illustrates own n-p-n dipole elements.

Figure 28 E is the citing of bias condition on unselected chip in Figure 27, and this unselected chip has with selected chip Having identical trip, the time is during selected chip write 0 operation.

Figure 28 F is the equivalent circuit diagram of Figure 28 E chips, illustrates own n-p-n dipole elements.

Figure 28 G is the citing of bias condition on unselected chip in Figure 27, and this unselected chip has with selected chip Having the row and column of difference, the time is during selected chip write " 0 " operation.

Figure 28 H is the equivalent circuit diagram of Figure 28 G chips, illustrates own n-p-n dipole elements.

Figure 29 is in this invention example, the citing of selected storage chip bias condition, during write " 1 " operation.

Figure 30 is the schematic diagram of storage chip in this invention another one example.

Figure 31 is the schematic diagram of storage chip in this invention another one example.

Figure 32 is the schematic diagram of storage chip in this invention another one example.

Figure 33 is the schematic diagram of storage chip in this invention another one example.

Figure 34 is the schematic top plan view of storage chip in Figure 30 and Figure 32.

Figure 35 A-35E is array and the details of first storage chip enumerated in this invention.

Figure 36 A-36U is the schematic diagram manufacturing storage chip method in this invention.

Figure 37 A-36C is the method schematic diagram keeping storage chip state in this invention.

Figure 38 A-38D is the method keeping in this invention storing data mode in storage chip array.

Figure 39 be this invention storage chip in the schematic diagram of buoyancy aid voltage.

Figure 40 is the storage chip current-voltage curve of this invention.

Figure 41 is the schematic diagram that storage chip array carries out in this invention read operation.

Figure 42 A-42H is 4 operation charts representing storage chip array in Figure 41.

Figure 43 A and 43B is the operation chart of selected chip in this invention in this invention, and the operation carried out is the The write logical zero operation of one class.

Figure 44 is the storage chip array schematic diagram of Figure 43 in this invention, during first kind write logical zero operation.

Figure 45 is the operation chart of unselected chip in this invention Figure 46, during Equations of The Second Kind write logical zero operation.

Figure 46 is the storage chip array schematic diagram of Figure 43 in this invention, during Equations of The Second Kind write logical zero operation.

Figure 47 is the storage chip array schematic diagram of Figure 43 in this invention, during the 3rd class writes logical zero operation.

Figure 48 A-48H is 4 operation charts representing storage chip in this invention, operates the phase in the 3rd logic of class Between.

Figure 49 is the storage chip array schematic diagram of Figure 43 in this invention, during first kind write logic 1 operation.

Figure 50 A-50H displaying is 4 operation charts representing chip in array shown in Figure 15, patrols in first kind write During collecting 1 operation.

Figure 51 is the storage chip array schematic diagram of Figure 43 in this invention, during Equations of The Second Kind write logic 1 operation.

Figure 52 A-52H displaying is 4 operation charts representing chip in array shown in Figure 51, patrols in Equations of The Second Kind write During collecting 1 operation.

Figure 53 A-53E displaying is the storage chip in the second example in this invention.

Figure 54 A-54H displaying is the schematic diagram in Figure 53 A-53D operated storage chip array.

Figure 55 A-55F displaying is the schematic diagram that storage chip carries out in this invention many layer operations.

Figure 56 is the replacement storage chip in this invention.

Figure 57 is the top view of storage chip shown in Figure 56.

Figure 58 A is another replacement storage chip in this invention.

Figure 58 B is the schematic diagram of storage chip array shown in Figure 58 A.

Figure 59 A-59F displaying is the storage chip in the 3rd example in this invention.

Figure 60 A-60F displaying is another Physical Examples of storage chip in Figure 59 A-59F.

Figure 61 A displaying is the storage chip array shown in Figure 59 A-59F and Figure 60 A-60F.

Figure 61 B show is the circuit arrangement of the single-chip shown in Figure 59 A-59F and Figure 60 A-60F.

Figure 62 displaying is the operation of the holding in array in Figure 61 A.

Figure 63 displaying is the read operation in array in Figure 61 A.

Figure 64 A-64P is 8 operation charts representing storage chip array in Figure 63.

Figure 65 displaying is 2 row write carried out in storage arrays in Figure 61 A operations that enter logical zero.

Figure 66 A and 66B displaying are the operations of storage chip not selected in Figure 65.

Figure 67 displaying is the operation writing logical zero on 1 row carried out in storage arrays in Figure 61 A.

Figure 68 displaying is the operation writing logical zero in a storage chip carried out in storage arrays in Figure 61 A.

Figure 69 A-69P is 8 operation charts representing storage chip array in Figure 63.

Figure 70 displaying is the operation writing logic 1 in a storage chip carried out in storage arrays in Figure 61 A.

Figure 71 A-71P is 8 operation charts representing storage chip array in Figure 70.

Figure 72 displaying be Figure 61 A is carried out in storage arrays in another one storage chip write logic 1 it Operation.

Figure 73 A-73B displaying be in Figure 72 to single storage chip write logic 1 operate time, in fact it could happen that write Disturbed condition.

Figure 74 displaying be Figure 61 A is carried out in storage arrays in another one storage chip write logic 1 it Operation.

Figure 75 A-75B is the another kind of schematic diagram manufacturing storage chip method in this invention.

Figure 76 A-76AA displaying is the method manufacturing storage chip in Figure 75 B.

Figure 77 A-77F displaying is the storage chip in the 4th example in this invention.

Figure 78 A-78B displaying is the holding operation that in Figure 77 A-77F, a storage chip array is carried out by another.

Figure 79 and 80A-80H displaying is the read operation in Figure 77 A-77F carried out a storage chip array.

Figure 81 displaying is the operation writing logical zero in a storage chip carried out in storage arrays in Figure 77 F.

Figure 82 A-82B is the operation chart of storage chip array not selected in Figure 81.

Figure 83 displaying is the operation writing logical zero in a storage chip carried out in storage arrays in Figure 77 F.

Figure 84 A-84H is 4 operation charts representing storage chip array in Figure 83.

Figure 85 A-85F displaying is the storage chip in the 5th example in this invention.

Figure 86 is the holding operation using storage chip in this invention under SCR pattern.

Figure 87 is the read operation using storage chip in this invention under SCR pattern.

Figure 88 is to use the write logic 1 of storage chip to operate in this invention under SCR pattern.

Figure 89 is the write logical zero operation using storage chip in this invention under SCR pattern.

Figure 90 A-90C displaying is the existing technique of standard MOSFET transistor.

Figure 91 displaying is the storage chip schematic diagram of an example in this invention.

Figure 92 A is the schematic diagram of an example in this invention, and wherein storage arrays has paired storage chip.

Figure 92 B is one of this invention example, and wherein chip array has a pair storage chip, and have reading circuit with Connected, it is possible to be used for determining data mode.

Figure 93 is the example of this invention, wherein illustrates to read the bias condition of selected storage chip, and stores number The bias condition of unselected chip in group.

Figure 94 A is one of this invention example, illustrates reading and chooses the bias condition of chip.

Figure 94 B-94D is the example of this invention, illustrates during the read operation of Figure 93 signal, the most selected chip it Bias condition.

Figure 95 is one of this invention example, for the schematic diagram of storage chip write " 0 ".

Figure 96 A-96B is in this invention example, the citing of unselected storage chip bias condition, write " 0 " behaviour During work.

Figure 97 is the bias condition of this invention example array chips, during write " 0 " operation, and the most all BL electricity The most identical storage chip all writes " 0 " state.

Figure 98 is another example of this invention, the act of unselected storage chip in selected storage chip and array Example, during write " 0 " operation.

Figure 99 A is the bias condition of chosen chip in example shown in Figure 98, during write " 0 " operation.

Figure 99 B-99D displaying is the example in Figure 98, the most selected chip bias feelings during write " 0 " operation Condition.

Figure 100 and 101A is in this invention example, the citing of selected storage chip bias condition, wears band using band During tracing enters " 1 " operation.

Figure 101 B-101D is the bias condition citing of unselected storage chip, uses the action type shown in Figure 100, enters Row write enters the operation of " 1 ".

Figure 102 is the bias condition of storage chip in this invention example, is using operating of ionization by collision write " 1 " Cheng Zhong.

Figure 103 A-103D and 104 displayings are in this invention example, the bias condition of selected storage chip 750, make When ionization by collision write " 1 ".

Figure 105 is the scheme of prior art, and adjacent storage chip shares contact.

Figure 106 A is the schematic cross-section of storage chip string in this invention example.

Figure 106 B is this invention example, and between SL electrode and BL electrode, a storage chip includes that two store core Sheet, this figure is schematic top plan view.

Figure 107 is that the equivalent circuit of Figure 106 B chips array is shown.

Figure 108 and 109A-109B is this invention example, illustrates the bias state during read operation.

Figure 110-111 is this invention example, illustrates the bias state in write " 0 " operating process.

Figure 112 A-112B is this invention example, illustrates the bias state in write " 0 " operating process, this operation Single byte is allowed to write.

Figure 113 A-113B is this invention example, illustrates and wears band in write " 1 " operating process then inclined at use band Pressure condition.

Figure 114 A-114B is this invention example, illustrates and is using the bias clashed in ionization write " 1 " operating process State.

Figure 115 A is in this invention example, the schematic diagram of fin three-dimensional storage chip.

Figure 115 B is in the another one example of this invention, the schematic diagram of fin three-dimensional storage chip.

Figure 116 A is in this invention example, and the energy band diagram of own n-p-n dipole elements, chip is taken from Figure 23, worked as buoyancy aid When region uses positive voltage charging, embedment trap will apply a positive bias.

Figure 116 B is in this invention example, and the energy band diagram of own n-p-n dipole elements, chip is taken from Figure 23, worked as buoyancy aid When region 24 uses neutral particle to be filled with, embedment trap will apply a bias.

Figure 117 is the bias condition of storage chip in this invention example, and icon is for carry out read operation on selected chip Process.

Figure 118 is in this invention example, the citing of storage chip bias condition, during write " 0 " operation.

Figure 119 is in the another one example of this invention, the bias condition of storage chip, during write " 0 " operation.

Figure 120 A is in this invention example, the schematic diagram of selected storage chip bias condition, in write " 1 " the operation phase Between.

Figure 120 B is in this invention example, and in selected storage chip and array, unselected storage chip (150) is partially Pressure situation, during using ionization by collision write " 1 " operation.

Figure 121 A is the schematic cross-section of storage chip string in this invention example.

Figure 121 B is this invention example, and between SL electrode and BL electrode, a storage chip includes that two store core Sheet, this figure is schematic top plan view.

Figure 121 C is in this invention example, and the equivalent circuit of storage chip array is shown, storage arrays includes Figure 121 B Shown string, and other chip strings.

Figure 122 is in this invention example, and the bias condition of chip string, during read operation.

Figure 123 A is this invention example, in identical string and different string, and selected storage chip and unselected storage chip Bias condition, be also during read operation.

Figure 123 B is this invention example, i.e. array shown in Figure 123 A, also includes a reading circuit, is connected to measure Or the electric current that sensing (on selected chip) is from BL electrode to SL electrode.

Figure 124 is in this invention example, the bias condition of chip string, during write " 0 " operation.

Figure 125 is this invention example, in identical string and different string, selected storage chip and unselected storage chip it Bias condition, is also during write " 0 " operation.

Figure 126 is in this invention example, the bias condition of chip string, and during write " 0 " operation, this operation allows single Byte writes.

Figure 127 is this invention example, in identical string and different string, selected storage chip and unselected storage chip it Bias condition, is also during write " 0 " operation, and this operation allows single byte write.

Figure 128 is in this invention example, the bias condition of chip string, using band, band mode is worn write " 1 " behaviour then During work.

Figure 129 is this invention example, in identical string and different string, selected storage chip and unselected storage chip it Bias condition, is also to use band to wear band then during write " 1 " operation.

Figure 130 A is in this invention example, the bias condition of chip string, is using ionization by collision write " 1 " the operation phase Between.

Figure 130 B is this invention example, in identical string and different string, and selected storage chip and unselected storage chip Bias condition, be also use ionization by collision write " 1 " operation during.

Figure 131 A is in this invention example, the schematic top plan view of two storage chip strings in a chip array.

Figure 131 B is the cross section view of a string in Figure 131 A.

Figure 132 A-132U is in this invention example, manufactures the different phase of a storage chip array.

Figure 133 is in this invention example, the schematic diagram that storage chip chain connects side by side.

Figure 134 A is the schematic top plan view of storage chip chain in Figure 133.

Figure 134 B is the sectional view of I-I ' in Figure 134 A, and storage chip takes from Figure 48 A.

Figure 134 C is the sectional view of II-II ' in Figure 133, and storage chip takes from Figure 48 A.

Figure 135 is in this invention example, and the equivalent circuit table four of storage arrays, including the chain in Figure 133.

Figure 136 is in this invention example, the schematic equivalent circuit of storage arrays chain, the most in a chain it Selected chip carries out read operation.

Figure 137 is the schematic diagram of selected chip in the array shown in Figure 135, and the bias feelings during read operation Condition.

Figure 138 is in this invention example, the schematic equivalent circuit of storage arrays chain, the most selectes it to one Array chain carries out writing " 0 " operation.

Figure 139 is in this invention example, the schematic diagram of the storage chip chain shown in Figure 138, the most enters this chain Row write enters " 0 " operation.

Figure 140 is in the another one example of this invention, and the schematic equivalent circuit of storage arrays is the most carried out Write " 0 " operation.

Figure 141 is in this invention example, the schematic diagram of the storage chip chain shown in Figure 140, the most enters this chain Row write enters " 0 " operation.

Figure 142 is in the another one example of this invention, and the schematic equivalent circuit of storage arrays is now currently in use Ionization by collision write " 1 " operation.

Figure 143 is selected storage chip and the schematic diagram of bias condition in Figure 142, the most just enters in the enterprising row write of chip The operation of " 1 ".

Figure 144 is the chain of another example in this invention.

Figure 145 A is the schematic top plan view of storage chip array in Figure 144.

Figure 145 B is the sectional view of I-I ' in Figure 145 A, and storage chip takes from Figure 145 A.

Figure 145 C is the sectional view of II-II ' in Figure 145 A, and storage chip takes from Figure 145 A.

Figure 146 is that the equivalent circuit of storage arrays chain represents, including the chain in Figure 144.

Figure 147 is in this invention example, the schematic equivalent circuit of storage arrays, the most to a selected number Group chain carries out read operation.

Figure 148 is the schematic diagram of selected chip in the array shown in Figure 147, and the bias feelings during read operation Condition.

Figure 149 is in one of this invention example, and the schematic equivalent circuit of storage arrays the most writes " 0 " operates.

Figure 150 is in this invention example, and the schematic diagram of the storage chip array shown in Figure 149, the most to this chain Carry out writing " 0 " operation.

Figure 151 is in the another one example of this invention, and the schematic equivalent circuit of storage arrays is the most carried out Write " 0 " operation, this operation allows single byte write.

Figure 152 is in another example of this invention, the schematic diagram of the selected storage chip chain shown in Figure 151, now This chain is being carried out write " 0 " operation shown in Figure 151.

Figure 153 is in the another one example of this invention, and the schematic equivalent circuit of storage arrays is now currently in use Ionization by collision write " 1 " operation.

Figure 154 is selected storage chip and the schematic diagram of bias condition in Figure 153, the most just enters in the enterprising row write of chip The operation of " 1 ".

Figure 155 is in the another one example of this invention, and the schematic equivalent circuit of storage arrays is now currently in use Ionization by collision write " 1 " operation.

Figure 156 is selected storage chip and the schematic diagram of bias condition in Figure 155, the most just enters in the enterprising row write of chip The operation of " 1 ".Figure 157 is another example in this invention, is a storage arrays, and the adjacent area of this array passes through one Individual conductive region and a public BL electrode are connected.

Figure 157 is another example in this invention, is a storage arrays, and the adjacent area of this array passes through one Conductive region and a public BL electrode are connected.

Figure 158 A is another example in this invention, is a storage arrays.

Figure 158 B is the storage chip that one of storage arrays shown in 158A is separated.

Figure 158 C and 158D is respectively in Figure 158 B, and storage chip is along the sectional view of I-I ' and II-II '.

Figure 159 is in this invention example, and shown in Figure 158 A, the equivalent circuit of storage arrays represents.

Figure 160 A is in this invention example, and shown in Figure 158 B-158D, the equivalent circuit of storage chip represents.

Figure 160 B is in this invention example, the energy band diagram of own n-p-n dipole elements, and Figure 160 A taken from by assembly, when floating When body region uses positive voltage charging, embedment trap will apply a positive bias.

Figure 160 C is in this invention example, the energy band diagram of own n-p-n dipole elements (30), and Figure 160 A taken from by assembly, When floating body region uses mesoscopic particles to be filled with, embedment trap will apply a bias.

Figure 161 is in this invention example, the schematic diagram of storage arrays, the most carries out a selected array chain Read operation.

Figure 162 is the schematic diagram of selected storage chip shown in Figure 161, and the bias condition when carrying out read operation.

Figure 163 is in one of this invention example, the schematic diagram of storage arrays, the most carries out writing " 0 " operation.

Figure 164 is in this invention example, and the schematic diagram of the storage chip array shown in Figure 163, the most to this chain Carry out writing " 0 " operation.

Figure 165 is in another example of this invention, the schematic diagram of storage arrays, the most carries out writing " 0 " behaviour Make.

Figure 166 is in this invention example, the schematic diagram of the storage chip chain shown in Figure 165, the most enters this chain Write " 0 " operation shown in row Figure 165.

Figure 167 is in one of this invention example, and the schematic diagram of storage arrays is now currently in use band and wears then to enter to band Row write enters " " 1 " operation.

Figure 168 is selected storage chip and the schematic diagram of bias condition in Figure 167, the most just enters in the enterprising row write of chip The operation of " 1 ".

Figure 169 is in one of this invention example, and the schematic diagram of storage arrays is now currently in use ionization by collision and carries out Write " 1 " operation.

Figure 170 is selected storage chip and the schematic diagram of bias condition in Figure 169, the most just enters in the enterprising row write of chip The operation of " 1 ".

Figure 171 is the operational flowchart of storage chip in this invention example.

Figure 172 is the operational flowchart of storage chip in another example of this invention.

Figure 173 A is the generalized section of storage chip in this invention example.

Figure 173 B is in this invention example, and the storage chip array enumerated, chip is arranged according to row and column.

Figure 173 C is another example in this invention, is the array architecture of a storage chip assembly.

Figure 174 is in this invention example, the situation of write state " 1 " operation, and this operation can be enterprising in storage chip OK.

Figure 175 is in this invention example, the situation of write state " 0 " operation, and this operation can be enterprising in storage chip OK.

Figure 176 is in this invention example, the read operation that can carry out in storage chip.

Figure 177 is in this invention example, the holding that can carry out in storage chip or refresh operation.

Figure 178 A-178B is in this invention example, the shadow mirror image operation that can carry out on chip.

Figure 179 A-179B is in this invention example, the storage operation that can carry out on chip.

Figure 180 is in this invention example, the replacement to storage chip capture layer, and storage chip is arranged in advance by this replacement Fixed state.

Figure 181 A is the generalized section of storage chip in this invention another one example.

Figure 181 B is another example in this invention, is the array architecture of a storage chip assembly.

Figure 182-183 is in this invention example, the generalized section of fin semiconductor memory chip assembly.

Figure 184 is the top view of fin semiconductor memory chip assembly in Figure 182.

Figure 185 A is the view of double-deck storage chip.

Figure 185 B is the view of Multi-layer Store chip.

Figure 186 A-186E is array and the details of first storage chip enumerated in this invention.

Figure 187 is the operational flowchart of storage assembly in this invention.

Figure 188 is the schematic diagram that storage chip array carries out in this invention keeping operation.

What Figure 189 A and 189B represented is during the hold operation, the energy band diagram of storage assembly.

Figure 190 A and 190B is the schematic diagram that storage chip array carries out in this invention read operation.

Figure 191 A and 191B is the intention that storage chip array carries out in this invention writing the operation of logical zero.

Figure 192 A and 192B is the intention that storage chip array carries out in this invention writing the operation of logic-1.

Figure 193 A-193C is the schematic diagram that storage chip array carries out in this invention shadow mirror image operation.

Figure 194 A-194C is the schematic diagram that storage chip array carries out in this invention keeping operation.

Figure 195 is the schematic diagram that storage chip array carries out in this invention reset operation.

Figure 196 A-196R is a kind of schematic diagram manufacturing storage chip method in this invention.

Figure 197 A-197R is another schematic diagram manufacturing storage chip method in this invention.

Figure 198 is the sectional view of another kind of storage assembly in this invention.

Figure 199 A-199B is the schematic diagram that storage chip array carries out in this invention shadow mirror image operation.

Figure 200 A-200C is the schematic diagram that storage chip array carries out in this invention keeping operation.

Figure 20 1 is the schematic diagram that storage chip array carries out in this invention reset operation.

Figure 20 2A and 202B is the sectional view of another kind of storage assembly in this invention.

Figure 20 3 is that the equivalent circuit of the storage assembly shown in Figure 20 2A and 202B represents.

Figure 20 4 is the storage assembly array enumerated in this invention.

Figure 20 5 is the schematic diagram that storage chip array carries out in this invention keeping operation.

Figure 20 6 is the schematic diagram that storage chip array carries out in this invention read operation.

Figure 20 7A-207C is the intention that storage chip array carries out in this invention writing the operation of logical zero.

Figure 20 8A and 208B is the intention that storage chip array carries out in this invention writing the operation of logic 1.

Figure 20 9,210A-210B are the schematic diagram that storage chip array carries out in this invention shadow mirror image operation.

Figure 21 1,212A-212B are the schematic diagram that storage chip array carries out in this invention storing operation.

Figure 21 3A and 213B is the schematic diagram that storage chip array carries out in this invention reset operation.

Figure 21 4 and 215 is the sectional view of another kind of storage assembly in this invention.

Figure 21 6 is that the equivalent circuit of the storage assembly shown in Figure 21 5 represents.

Figure 21 7 is the storage assembly array enumerated in this invention.

Figure 21 8 is the schematic diagram that storage chip array carries out in this invention keeping operation.

Figure 21 9 is the schematic diagram that storage chip array carries out in this invention read operation.

Figure 22 0A, 220B and 221 are the intention that storage chip array carries out in this invention writing the operation of logical zero.

Figure 22 2A and 222B is the intention that storage chip array carries out in this invention writing the operation of logic-1.

Figure 22 3A-223B is the schematic diagram that storage chip array carries out in this invention shadow mirror image operation.

Figure 22 4 is the schematic diagram that storage chip array carries out in this invention reset operation.

Figure 22 5A and 225B is the schematic diagram that storage chip array carries out in this invention reset operation.

Figure 22 6 is the operational flowchart of storage assembly in another example of this invention.

Figure 22 7 is the schematic diagram that storage chip array carries out in this invention read operation.

Figure 22 8 is the schematic diagram that storage chip array carries out in this invention writing logic-1 operation.

Figure 22 9A-229C is in this invention, the sectional view of another one storage assembly, and this assembly is at SOI (SOI) Upper manufacture.

Figure 23 0A-230E is in this invention, and the sectional view of another storage assembly, containing fin structure.

Detailed Description Of The Invention

Before the system in this patent, assembly and method are illustrated, need to submit to that reader notes is that this is special Profit should not be restricted by the restriction of certain described example of this part, and example is possibly different from.Also should remind reader is, at this Term used in part, for certain example is described, is not intended to limit the scope of patent, and this patent is only subject to It is limited to the patent right statement hereinafter enclosed.

When providing a codomain, represent include between upper and lower bound each intermediate value (such as no special sound Bright, intermediate value is the 1/10 of lower limit unit).Smaller range (the most not including infinity) between setting, or on rule Setting or intermediate value in intermediate value in definite value territory, and regulation codomain belong to this invention.In above-mentioned smaller range Bound can all include (closed interval) or not include in (open interval), or comprise one of them, two or zero, on State the numerical value included and belong to this invention, except being otherwise noted this ultimate value of eliminating.When comprise in regulation codomain one or During two limit, the codomain removing wherein one or two limit falls within this invention.

Unless otherwise indicated, in industry belonging to all technology used herein and scientific terminology and the present invention, people The term being generally understood that has the identical meaning.Actually used or test this invention time, various method and material may be used Material, is similar to explanation hereafter, the most i.e. starts to illustrate method for optimizing and material.All quote in this article and open The patent illustrated all contains the method and/or material being cited in patent.

Notice in needing to state with annex special secondary school economic rights herein and be: the singulative of word also contains plural form Implication, unless context understand eliminate plural reference.Such as, " chip " is used to also contains " a pair chip ", Use " this electrode " to also contains one or more electrode, by that analogy, for being familiar with the people of prior art, be understood that.

The patent of discussion is open in this article was intended for before the date of application disclosing this patent.Any information in this literary composition is equal It is not to be construed as: allow by means of prior art, before this invention, applies for a patent disclosure.Meanwhile, patent public affairs herein Opening the date may have difference, actual publication date to need to determine separately with the publication date of reality.

Definition

" holding operation ", " preparing operation " or " keeping/preparation operation ", all represent a process: by keeping storage Electric charge, keeps the state of storage chip.The electric charge keeping stored can be by applying reverse biased to chip, and method is shown in this Literary composition explanation.

The process of " multilamellar write operation " expression: the state of two or more difference can be write in storage chip, often More than one byte is preserved on individual chip.

" write-verify ", " write and verify " or " alternately write and verify " algorithm or program refer to is: this process alternately to one Individual storage chip carries out writing and read operation, and this operation is used for verifying whether storage chip has reached to think during write operation The storage chip storing state wanted.

" reading verification operation " represents: this process carries out read operation to storage chip, and whether checking storage chip achieves is thought The storing state wanted.

" read and programming " operation to represent: this process carries out write and read operation simultaneously, in order to the storage core that write is required Sheet state.

" reverse biased electrode " represents: this electrode is positioned at the back side of semiconductor transistor assembly, is usually located at transistor gate Other side.Reverse biased electrode is often referred to: " back-gate electrode ".Herein, back-gate electrode refers to electrode of substrate or embedment trap electrode, Depend on the example illustrated.

Noun " reverse biased " represents the voltage of applying on reverse biased electrode.

" storage chip " represents: semiconductor memory chip, comprises the buoyancy aid of a conduction, it is possible to as data storage group Part.

" contactless storage chip " represents, storage chip does not comprises (any) contact, directly do not connects with (any) control line Touch.The usually series connection of contactless storage chip, constitutes a string, or parallel connection is a chain.

" storing string " or " string " represents, the storage chip of one group of interconnection, connected mode is series connection, and conductive region is by phase Adjacent storage chip is shared at chip surface or connects.In being connected in series, flow through each storage chip the most identical.

" chain " represents, the storage chip of one group of interconnection, and connected mode is in parallel, and conductive region is by adjacent storage chip Share at chip surface or connect.In being connected in parallel, the voltage drop in each storage chip is identical.

" chip array " or " storage chip array " represents, at one of row and column to storage chip.Paired storage core Sheet can also connect bunchiness or company further in chip array.

" shadow mirror image ", " shadow mirror image operation " and " shadow image program " represents: by data from impermanency stores Copy to the process of permanent storage.

" recover ", " recovery operation " or " recovery routine " represents, the content in permanent storage is copied to impermanency In storage.

" reset ", " reset operation " or " replacement process " represents, permanent storage is set to predetermined state.

" permanent data (permanent data) " represents, uses storage chip assembly to carry out the process operated in system In the data that will not change, and these data can deposit from permanent storage indefinite duration." permanent data " include but not It is limited to: program shelves, application file, music shelves, video shelves, operating system etc..

Noun " single-polysilicon " flash memory refers to, a permanent storage chip, only a polysilicon door, such as, use polycrystalline Silicon does floating boom, is used for storing permanent data.Therefore, single-polysilicon flash memory partly can be led with the metal-oxide of tradition at present Body (CMOS) program compatibility.Polycrystalline silicon material can be with the door coprecipitation of logic transistor and molding.

Noun " repeatedly grid " flash memory represents, has the permanent storage chip of multiple polysilicon layer/door, the such as second polysilicon Door (e.g., control gate), is i.e. that storehouse forms it on a multi-crystal silicon floating bar, can be used to store permanent data (see " permanent Property semiconductor memory technology " Fig. 4 .6 of W.D Brown and J.E.Brewer the 197th), herein with reference to quoting.Above-mentioned repeatedly grid Storage chip usually requires that two (or multiple) polysilicon layers process technique, when first polysilicon layer (such as floating boom) deposits and become After type, followed by the processing and forming of second polysilicon layer (such as control gate).

Describe in detail

According to the Fig. 1 in this invention example, storage chip (50).Chip (50) includes a substrate (12), has One conduction type, such as n-type conduction type.Substrate 12 is generally made up of silicon, but can comprise germanium, silicon-germanium, silicon-arsenic, carbon are received Mitron or other known semi-conducting materials.Substrate 12 has a surface 14.First area 16 has the first conduction type, as N-type, is positioned on substrate 12, towards surface 14.Second area 18 has the first conduction type, also is located on substrate 12, towards table Face 14, and separate with first area 16.First and second regions 16 and 18 all by a doping process in the group of substrate 12 Becoming and process on material, use is to be currently known and the doping process of typical case.It addition, also use a solid state diffusion process, Process the first and second regions, 16 and 18.

Floating body region 24 has the second conduction type, different from the first conduction type, if such as p-type-the first conductive-type Type is n-type, with the 14, first and second region, surface (16,18), insulating barrier 26 and substrate 12 adhesion.Floating body region 24 can be led to Overdoping technique processes on the composition material of substrate 12, it is also possible to processed by epitaxial growth.Insulating barrier 26 is (such as shallow slot Isolation (STI)), it is possible to use Si oxide.When chip 50 is connected into array 80, insulating barrier 26 by chip 50 with adjacent it Chip 50 separates, thus constitutes storage assembly as shown in Figure 2.Door 60 is between region 16 and 18, on surface 14.Door 60 Insulated with surface 14 by insulating barrier 62.Insulating barrier 62 can use silicon oxide and/or other insulant, insulate including height-K Material, includes but not limited to peroxidating tantalum, titanium oxide, zirconium oxide, hafnium oxide and or aluminium oxide.Door 60 can use polysilicon Material or metal gate electrode, such as tungsten, tantalum, titanium and their nitride

Chip 50 also includes wordline (WL) electrode 70, is connected with door 60, in source line (SL) electrode 72, with region 16 and 18 it One be connected (icon and 16 be connected, but can also be connected with 18), in bit line (BL) electrode 74, with region 16 and 18 additionally One is connected (icon is 18, but can also be connected with 16, now requires 72 to be connected with 18), and electrode of substrate 78, with base Plate 12 is connected.The contact of substrate regions 12 can be by having the region being connected with substrate regions 12 of first kind conduction type (not shown) realizes.

In another one example, storage chip 50 has p-type conduction type, (the i.e. first conduction type), and n-type is Second conduction type, as described above.

To the operation of storage chip 50 at " Scaled 1T-Bulk Devices Built with CMOS 90nm Technology for Low-cost eDRAM Applications " R.Ranica etc., the 38-41 page illustrates, technology literary composition Pluck, VLSI technical seminar, 2005, be hereby incorporated reference in full.The state of storage chip is come by the electric charge in buoyancy aid 24 Represent.Compared with not storing hole with the floating body region 24 on chip 50, as fruit chip 50 stores hole in floating body region 24, Then storage chip 50 has lower threshold voltage (gate voltage of transistor unlatching).

The positive charge of storage in floating body region 24, can reduce in time, and reason is at buoyancy aid 24, region 16,18 and The p-n diode of formation on substrate 12 can leak, also due to the recombining of electric charge.Being unique in that of this invention can The holding that carries out to all storage chip 50 in array 80 are parallel operates.Operation is kept to pass through to execute on electrode of substrate 78 Add a reverse biased just to realize, now by ground electrode 72 and/or electrode 74 ground connection.Be applied on electrode of substrate just it Reverse biased can remain connected to the state of storage chip 50.Keep operation independently can grasp with the voltage being loaded on electrode 70 Make.As it is shown on figure 3, inside storage chip 50, by, on substrate regions 12, buoyancy aid 24, SL and BL region 16 and 18, defining N-p-n dipole elements 30a and 30b.If buoyancy aid 24 has been filled with positive charge (such as, be set to one state), by SL region 16, float Body 24 and the bipolar transistor 3a of substrate regions 12 formation, and formed double by BL region 18, buoyancy aid 24, substrate regions 12 Gated transistors 30b will open.

A part for bipolar transistor current will be flowed in floating body region 24 and (usually become base current), and keep One state purgation data.The efficiency keeping operation can be improved by the design of dipole elements, will substrate 12, floater area Territory 24, region 16,18 composition one low gain dipole elements, wherein bipolar gain be defined as-flow out it from electrode of substrate 78 Collector current is than the base current of upper inflow floating body region 24.

To storing the storage chip of data under state " 0 ", dipole elements 30a, 30b will not open, final base stage Hole current can be flowed in floating body region 24.Make, continue to keep this state in state " 0 " purgation storage chip.

It will be seen that keep operation can batch, parallel operation, if electrode of substrate 78 is by the institute in chip array 80 Chip 50 is had to share (e.g., 78a, 78b.....78n).Electrode of substrate 78 can carry out segmentation, enabling to chip array (as Shown in Fig. 4 A) in selected part carry out independent being biased, such as electrode of substrate 78a, 78b is just from electrode 78m, 78n Classification is out.It addition, because electrode of substrate 78 will not be used for the selection of board address, would not be when keeping operation to storage The access of chip causes interruption.

In another one example, the direct impulse voltage of periodicity can be applied on electrode of substrate 78, with constant it Forward bias is different, thus reduces the power consumption of storage chip 50.Applying to reverse biased electrode (such as electrode of substrate 78) During positive pulse voltage, the state of storage chip 50 can be kept by the electric charge that refreshing is stored in buoyancy aid 24.Fig. 4 B enters One step illustrates multiplexer 40, and multiplexer is used for determining the bias being applied on electrode of substrate 78, the control letter on electrode Number can be clock signal 42, it is possible to use the operator scheme of difference is determined (hereinafter describing in detail).Positive input signal is permissible It is power source supplying voltage Vcc (Fig. 4 B), or the positive bias (see Fig. 4 C) of the difference produced by voltage generator circuit 44.

Keep/prepare operation to be likely to produce a bigger bin window, buoyancy aid 24 can be stored in by increasing In the quantity of electric charge realize.Without keeping/prepare operation, it is possible to the maximum potential being stored in buoyancy aid 24 is limited to flat rubber belting Voltage V_FB, because the junction leakage flowing to region 16 and 18 will increase with floating body potential for index, more than V_FB.But, by Applying a positive voltage on electrode of substrate 78, the action of dipole elements will produce a hole current flowing into buoyancy aid 24, compensate Junction leakage between buoyancy aid 24 and region 16&18.Therefore, the maximum charge V being stored in buoyancy aid 24_MC, can pass through Apply positive bias on electrode of substrate 78 to increase, see Fig. 5.Increase the maximum charge being stored in buoyancy aid 24 to make to store window more Greatly.

Keep/prepare operation may be used in storage chip 50 more than byte manipulation.In order to increase storage density, and do not increase Add the shared area of storage chip 50, it will usually use many layer operations.By whole storage window is divided into the layer of difference come Realize.In buoyancy aid stores, the chip status of difference is represented by the difference electric charge in buoyancy aid 24, and " The is shown in citing Multistable Charge-Controlled Memory Effect in SOI Transistors at Low Temperatures ", Tack etc., 1373-1382 page, the operation of IEEE electronic building brick, volume 37, May nineteen ninety；And the U.S. Patent 7542345 " there is the multibyte storage chip of conduction floating body transistor, and programming and read method ", draw at this With, as reference.But, owing to 0 state of charge in buoyancy aid 24 is steady statue, buoyancy aid 24 can the most gradually lose Remove electric charge, until steady statue.In many layer operations, the electric charge of difference represents the state of difference, and the kind of electric charge to be lacked In the kind in monolayer operation.Therefore, Multi-layer Store chip is easier to receive the impact losing electric charge, because needed for change state The quantity of electric charge " to lose " is less.

Fig. 6 represents, the net relative electric current of different buoyancy aid 24 current potentials, and the current potential of buoyancy aid 24 is electrode of substrate 78 and BL, SL, with And the function of WL electrode 72,74 and 70 ground connection.When 0 voltage is applied on electrode of substrate 78, does not have bipolar current and be flowed into In buoyancy aid 24, wherein the electric charge of storage can reduce in time.When applying a positive electricity and being pressed onto on electrode of substrate 78, hole Electric current will be flowed in buoyancy aid 24, compensates the junction leakage being flowed into region 16 and 18.Junction leakage is by buoyancy aid 24 and region Potential difference between 16&18 determines, and the bipolar current being flowed into buoyancy aid 24 is common by the current potential of electrode of substrate 78 and buoyancy aid 24 Determine.As shown in Figure 6, at certain electrode of substrate 78 current potential V_HOLDUnder, the floating body potential of difference；It is flowed into the electric current of buoyancy aid 24 And the junction leakage balance between buoyancy aid 24 and region 16&18.What buoyancy aid 24 current potential of difference represented is the electric charge of difference, thus Represent the different conditions of storage chip 50.The storing state of difference can come by using holding/preparation operation described herein as Maintain.

The bias condition of holding operation is: 0 voltage is applied on BL electrode 74, and 0 voltage is applied on SL electrode 72,0 electricity Pressure or negative voltage are applied on WL electrode 70, and positive voltage is applied on electrode of substrate 78.In a specific non-limiting examples, Being applied on electrode 72 by the voltage of about 0.0 volt, the voltage of about 0.0 volt is applied on electrode 74, about 0.0 volt Voltage be applied on electrode 70, and the voltage of about+1.2 volts is applied on electrode 78.Above magnitude of voltage can be different.

It is stored in the electric charge in buoyancy aid 24 to be sensed by the chip current of detection storage chip 50.Such as fruit chip 50 are in one state, store hole in floating body region 24, then storage chip has relatively low threshold voltage (transistor is opened The gate voltage opened), and finally have higher chip current, it is in " 0 " state relative to chip 50, does not stores up in floating body region 24 For depositing hole.Sensor circuit/reading circuit 90 is generally connected (see the reading circuit in Figure 18 A with the BL electrode 74 of storage arrays 80 90), this circuit may be used to determine the data mode of storage chip.The example of read operation is shown in " A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage(GIDL)Current for Low-power and High-speed Embedded Memory ", Yoshida etc., 913-918 page, International Electro assembly is big Meeting, 2003；And United States Patent (USP) 7301803 " being used for the bipolar reading technology with conduction floating body transistor ", quote herein, with For reference.The example of sensor circuit see " " An 18.5ns 128Mb SOI DRAM with a Floating body Cell ", Ohsawa etc., 458-459 page, page 609, IEEE International Solid circuit conference (2005), quote herein, only for reference.

Read operation can realize by applying following bias condition: applies a positive voltage on electrode of substrate 78, Apply 0 voltage on SL electrode 72, selected BL electrode 74 applies a positive voltage, and at selected BL electrode 74 One ratio of upper applying selectes positive voltage bigger on WL electrode 70.Unselected BL electrode keeps 0 voltage, unselected WL electrode Keep 0 voltage or negative voltage.In a specific non-limiting example, the voltage of about 0.0 volt is applied on electrode 72, The voltage of about+0.4 volt is applied on electrode 74, and the voltage of about 0.0 volt is applied on electrode 70, and by about+1.2 The voltage of volt is applied on electrode 78.Unselected electrode 74 keeps 0.0 volt, and unselected electrode 70 keeps 0.0 volt.Bias Situation such as Fig. 7 shows, respectively selected storage chip 50a in storage arrays 80 and unselected storage chip 50b, 50c and 50d.Above magnitude of voltage can be different.

Storage chip 50 unselected in read operation as shown in Fig. 8 A, 8C and 8E, bipolar group of the n-p-n of chip 50 inside The explanation in Fig. 8 A, 8C, 8E and Fig. 8 B, 8D, 8F respectively of the state of part 30a, 30b.In selected chip, storage chip 50 it Bias condition (there is identical trip, such as storage chip 50b) and there is the storage chip (such as storage chip 50c) of same column, point Not as shown in Fig. 8 A-8B and Fig. 8 C-8D；And it is not total to the bias condition of the storage chip 50 of row or column as shown in Fig. 8 E-8F.

For having the storage chip 50 of colleague mutually, such as the storage chip for selecting, the electricity of SL electrode 72 and BL electrode 74 Pressure is above 0.0 volt (such as Fig. 8 A-8B).It will be seen that these chips are in holding pattern, storage chip be in one state it, The electric charge in buoyancy aid 24 can be kept, because intrinsic n-p-n dipole elements 30a, 30b can produce hole current, with supplementary buoyancy aid 24 In electric charge；The storage chip 50 being simultaneously in " 0 " state will keep neutral state.

For having the storage chip of same column, as selected storage chip, BL electrode 74 is applied with one Positive voltage (Fig. 8 C-8D).But, the 30a of n-p-n dipole elements is made up of substrate 12, buoyancy aid 24 and region 16, will still protect Hold the state of buoyancy aid 24, and the SL electrode 72 now ground connection being connected with region 16.

For having the storage chip 50 of colleague mutually, it is selected storage chip, the electricity of SL electrode 72 and BL electrode 74 Pressure is above 0.0 volt (such as Fig. 8 E-8F).It will be seen that these chips are in holding pattern, storage chip be in 1 state it, energy Keep the electric charge in buoyancy aid 24, because intrinsic n-p-n dipole elements 30a, 30b can produce hole current, with in supplementary buoyancy aid 24 Electric charge；The storage chip 50 being simultaneously in 0 state will keep neutral state.

From the description above, it can be seen that keep operation will not interrupt the read operation of storage chip 50.Meanwhile, unselected it Storage chip 50 will be retained in holding operation during read operation.

Below the write operation of storage chip 50 is illustrated.The write " 0 " of chip 50 operates as shown in Figure 9.In order to incite somebody to action " 0 " write chip 50, needs to apply a back bias voltage to SL electrode 72, applies one 0 or back bias voltage to WL electrode 70, to substrate Electrode 78 applies one 0 or back bias voltage.The SL electrode 72 of the most selected chip is unaffected, keeps ground connection.In the case of hereinto, P-n junction between 24 and 16 is forward bias, will shift the hole in buoyancy aid 24.In a specific non-limiting example, will The voltage of about-2.0 volts is applied on electrode 72, and the voltage of about 0.0 volt is applied on electrode 70, and by about+1.2 The voltage of volt is applied on electrode 78.Above-mentioned magnitude of voltage can also be different, if the relativeness between above-mentioned electric charge.

As shown in Figure 10, for selected in storage arrays 80 and unselected storage chip 50 during write " 0 " operation partially Pressure situation.For selected storage chip, being applied to the back bias voltage on SL electrode 72 will produce between buoyancy aid 24 and region 16 Big potential difference.For the buoyancy aid 24 of the storage chip charged by positive charge, intrinsic n-p-n dipole elements 30a, 30b The hole current of generation is insufficient to compensate for the forward bias current of p-n diode, and this diode is made up of buoyancy aid 24 and knot 16.

Figure 11 A-11B is that intrinsic n-p-dipole elements 30a of unselected storage chip 50,30b are during write " 0 " operation Bias condition and equivalent circuit diagram.Owing to write " 0 " operation relates to apply a negative voltage to SL electrode 72, all unselected The bias condition determining chip is the most identical.It will be seen that unselected storage chip execution is a holding operation, BL simultaneously All it is about 0.0 volt with SL electrode.Reverse biased just is applied to electrode of substrate 78, carries out keeping operation, choosing will not be interrupted Determine write " 0 " operation of storage chip.It addition, unselected storage chip is still for keeping operation.

Write " 0 " operation can produce a shortcoming in all storage chip 50 sharing a SL electrode, it is simply that together with Time write all storage chip, so single byte write can not be carried out, as being written to the storage of certain storage chip 50 single Deposit byte.In order to write multiple data in the storage chip 50 of difference, " 0 " behaviour can be entered in all storage chip advanced person's row write Make, then enter " 1 " operation in the selected enterprising row write of byte.

Additionally there is a kind of write " 0 " operation allowing single byte write, it is simply that on WL electrode 70, apply a positive voltage, BL electrode 74 applies a negative voltage, SL electrode 72 applies 0/ negative voltage, electrode of substrate 78 applies one Individual 0 or positive voltage.In the case of hereinto, owing to being applied with a positive voltage on WL electrode 70, the current potential of buoyancy aid 24 will pass through Capacitance Coupled raises.Make: the current potential of buoyancy aid 24 raises, and negative voltage is applied on BL electrode 74, and the p-n junction between 24 and 18 is just To biasing, the hole on buoyancy aid 24 is fallen in transfer.Thus decrease in storage arrays 80 and interfere it to other storage chip 50 Write " 0 ", the current potential applied can optimize as follows: if it is assumed that the current potential with the buoyancy aid 24 of state " 1 " is V_FB1, then can be improved the current potential of buoyancy aid 24 by the voltage that setting is applied on WL electrode 70, V can be improved_FB1/ 2, and- V_FB1/ 2 voltages being just applied to BL electrode 74.Then on SL electrode 72, apply a positive voltage, reduce further and storing Array need not write other storage chip of " 0 " interference.Unselected chip will be maintained at hold mode, as at WL Apply 0/ negative voltage on electrode 70, and on BL electrode 74, apply 0 voltage.

In a non-limiting examples, following bias condition can be applied in selected storage chip 50a: at electrode 72 The voltage that upper applying is about 0.0 volt, applies about 0.2 volt on electrode 74, applies about+0.5 volt, at electrode on electrode 70 Apply about+1.2 volts on 78, on the electrode 72 of unselected storage chip, then apply about 0.0 volt, on electrode 74 Apply about 0.0 volt, electrode 70 applies about 0.0 volt, electrode 78 applies about+1.2 volts.Figure 12 gives storage Selected storage chip and the bias condition of unselected storage chip in array 80.Above magnitude of voltage can be different.

Under write " 0 " operation, the bias condition of selected storage chip 50a can be described in detail by Figure 13 A-13B.As Discussed above it, buoyancy aid 24 and knot 18 (being connected with BL electrode 74) between electric potential difference increase now, result in forward bias The bias current put is produced by n-p-n dipole elements 30a, 30b more than the hole current of base stage, this hole current, dipole elements It is made up of substrate 12, buoyancy aid 24 and region 16&18.Result is exactly that hole is shifted from buoyancy aid 24.

Unselected storage chip 50 is when writing " 0 " operation, as shown in Figure 13 C-13H.There is the storage of colleague mutually The bias condition of chip (such as storage chip 50b), as shown in Figure 13 C-13D, has same column as selected storage chip 50a Storage chip (such as storage chip 50c), its bias condition is as shown in Figure 13 E-13F；Have simultaneously mutually colleague and same column it Unselected storage chip 50 (such as storage chip 50d), as shown in Figure 13 G-13H.

For having the storage chip 50 of colleague mutually, such as the storage chip for selecting, the electricity of SL electrode 72 and BL electrode 74 Pressure is above 0.0 volt (such as Figure 13 C-13D).Due to the Capacitance Coupled with WL electrode 70, in said chip, the current potential of buoyancy aid 24 is also Can raise.For being in the storage chip of one state, buoyancy aid 24 current potential of rising can not keep, because p-n diode (by Buoyancy aid 24, knot 16&18 are constituted) forward bias bias current be greater than base stage hole current and (produced by n-p-n dipole elements 30 Raw), n-p-n dipole elements 30 is made up of substrate 12, buoyancy aid 24, knot 16 and 18.Therefore, the current potential of buoyancy aid 24 will be returned to initial it " 1 " equilibrium potential.For being in the storage chip of " 0 " state, if the potential rise height of buoyancy aid 24 is sufficiently large (as at least V_FB/ 3, illustrate to see below), then n-p-n dipole elements 30a and 30b can be unlocked so that buoyancy aid 24 reaches a new balance electricity Position, this current potential is in " 0 " between state and one state.Accordingly, it would be desirable to WL current potential is optimized so that n-p-n dipole elements 30a, 30b can not be unlocked, or make base stage hole current of a sufficiently low so that this electric current can not cause buoyancy aid 24 current potential at any time Between raise, simultaneously complete write operation (write operation time) during this period.This invention determines: buoyancy aid 24 current potential raises V_FB/ 3 be enough to prevent the rising of buoyancy aid 24 current potential too much.

It, pass through and carefully design the voltage being applied on WL electrode 70 accordingly, with the selected identical WL of storage chip use The state of the unselected storage chip of electrode (that is, having colleague mutually) is maintained.

For the storage chip with selected storage chip same column, then can apply a negative voltage on BL electrode 74 (see Figure 13 E and 13F) so that the current potential between buoyancy aid 24 and region 18 (being connected with BL electrode 74) realizes rising.Result must Arrive the bigger forward bias current between buoyancy aid 24 and knot 18.For being in the storage chip of state " 0 ", buoyancy aid 24 He Potential difference between knot 18 is the most of a sufficiently low so that p-n diode (being made up of buoyancy aid 24 and knot 18) will not be forward biased.Cause This, above-mentioned storage chip is still within state " 0 ".For being in the storage chip of state " 1 ", node leakage current is due to forward bias Put electric current and increase.But, the hole current of n-p-n dipole elements 30b (being made up of substrate 12, buoyancy aid 24 and region 18) is still Can increase, the potential difference between substrate 12 and region 18 cause (respectively collector and emitter).Therefore, it is in state In the storage chip of " 1 ", buoyancy aid 24 still can keep positive charge (that is, being in state " 1 ").

For having the storage chip 50 of colleague mutually, it is selected storage chip, the electricity of SL electrode 72 and BL electrode 74 Pressure is above 0.0 volt (such as Figure 13 G-13H).It will be seen that these chips keep holding pattern, storage chip is in " 1 " State it, the electric charge in buoyancy aid 24 can be kept because intrinsic n-p-n dipole elements 30a, 30b can produce hole current, with supplement Electric charge in buoyancy aid 24；The storage chip 50 being simultaneously in " 0 " state will keep neutral state.

Corresponding it, this invention proposes a kind of write " 0 " operation, it is allowed to carry out byte selection.It is applied to storage chip Positive bias on the electrode of substrate 78 of 50 must be used for keeping the state of unselected chip 50, especially with selected chip 50 There is the chip of identical row and column, owing to bias condition can change the current potential of storage chip 50, and do not affect intrinsic bipolar group Part 30a, 30b (being made up of substrate 12, buoyancy aid 24 and region 16/18) reach poised state again.Positive bias is applied to substrate Electrode 78, carries out keeping operation, will not interrupt write " 0 " operation of selected storage chip.

Also have write " 1 " operation that one can be carried out in storage chip 50, use ionization by collision or band to band forms Wearing mechanism then, illustrated example is shown in " A Design of a Capacitorless 1T-DRAM Cell Using Gate- Induced Drain Leakage(GIDL)Current for Low-power and High-speed Embedded Memory " Yoshida etc., the 913-918 page, International Electro assembly conference (2003), it is hereby incorporated, for reference.

The selected storage chip 50 bias condition when using band that band forms is worn write " 1 " operation then, is shown in Figure 14 and Tu 15A-15B.It is applied to the back bias voltage of WL electrode 70 and is applied to the positive bias of BL electrode 74, can be floating in selected storage chip 50 Produce hole on body 24 to inject.Be applied to the positive bias on electrode of substrate 78 will keep with the above the buoyancy aid 24 of discussion obtains just Electronics.Unselected chip 50 is then still in holding pattern, applies 0/ negative voltage on unselected WL electrode 70, 0 voltage, persistently this holding operation (holding pattern) is applied on unselected BL electrode 74.

In a non-limiting examples, following bias condition can be applied in selected storage chip 50a: at electrode 72 Upper applying about 0.0 volt, applies about+1.2 volts on electrode 74, applies about-1.2 volts on electrode 70, in electric shock 78 Apply about+1.2 volts, and bias below applying in unselected storage chip 50: the voltage of about 0.0 volt is applied On electrode 72, the voltage of about 0.0 volt is applied on electrode 74, and the voltage of about 0.0 volt is applied on electrode 70, and The voltage of about+1.2 volts is applied on electrode 78.Figure 14 gives in storage arrays 80 selected storage chip and the most selected Determine the bias condition of storage chip.Above magnitude of voltage can be different.

Unselected storage chip 50 is when writing " 1 " operation, as shown in figure _ 15C-15H.With selected storage chip 50 have mutually colleague (such as 50b) storage chip bias condition as shown in figures 15 c-d, have same column storage chip (as 50c) as shown in Figure 15 E-15F.Neither having with selected storage chip 50a goes together mutually does not the most have the storage chip 50 of same column (such as 50d), its bias condition is as shown in Figure 15 G-15H.

For having the storage chip 50 gone together mutually with chosen storage chip, the voltage of SL electrode 72 and BL electrode 74 is equal Higher than 0.0 volt, WL electrode 70 is 0 volt or negative voltage.(such as Figure 15 C-15D).Compared with the bias condition keeping operation, can see Arriving, the storage chip (that is, having identical WL electrode 70) with same column is in holding pattern.Therefore, above-mentioned storage core The state of sheet keeps constant.

For having the storage chip of same column, as selected storage chip, BL electrode 74 is applied with one Positive voltage.Dipole elements 30b (being made up of substrate 12, buoyancy aid 24 and region 18) being connected with BL electrode 74 is closed, because Small electric pressure reduction between electrode of substrate 78 and BL electrode 74 (respectively collector and emitter).But, with SL electrode 72 Dipole elements 30a (being made up of substrate 12, buoyancy aid 24 and region 16) being connected still can be for being in the storage chip of state " 1 " Producing base stage hole current, the buoyancy aid 24 of storage chip is filled with positive charge.In dipole elements 30a (by substrate 12, buoyancy aid 24 and district Territory 16 is constituted) close time, be in state " 0 " storage chip and will remain in state " 0 ".

For having the storage chip 50 of colleague mutually, it is selected storage chip, the electricity of SL electrode 72 and BL electrode 74 Pressure is above 0.0 volt (such as Figure 15 G-15H).It will be seen that these chips are in holding pattern (keeping operation), at storage chip In one state it, the electric charge in buoyancy aid 024 can be kept because intrinsic n-p-n dipole elements 30a, 30b can produce hole current, With the electric charge in supplementary buoyancy aid 24；The storage chip 50 being simultaneously in 00 state will keep neutral state.

Positive bias is applied to electrode of substrate 78, carries out keeping operation, write " 1 " behaviour of selected storage chip will not be interrupted Make.Meanwhile, unselected storage chip will be retained in holding operation during write " 1 " operation.

Multilamellar write operation can use another one write and verification algorithm to realize, and prime minister applies in storage chip 50 One write pulse, carries out write operation subsequently, and verifies whether to achieve required storing state.Without realize required it Storing state, then have another one write pulse and be applied in storage chip 50, followed by reading/verification operation.This follows Ring is constantly reciprocal, until realizing required storing state.

Such as, use band that band forms is worn hot hole then and inject, BL electrode 74 applies a positive voltage, at SL electrode Apply 0 voltage on 72, WL electrode 70 electrode applies a negative voltage, on electrode of substrate 78, just then apply one Voltage.After the positive voltage of various amplitude is applied on BL electrode 74, the state of difference can be write on buoyancy aid 24.Produced Difference floating body potential 24 corresponding to the positive voltage of difference, or the difference positive voltage pulse being applied on BL electrode 74.By Applying positive voltage on electrode of substrate 78, the base stage hole current being flowed into buoyancy aid 24 maintains the current potential of buoyancy aid 24.Non-at one Limit in example, realize write operation by applying following bias state.Electrode 72 applies about 0.0 volt of voltage, at electricity Apply about-1.2 volts on pole 70, electrode 78 applies about+1.2 volts, on BL electrode 74, apply voltage simultaneously, improve 74 Current potential.In a non-limiting examples, on BL electrode 74, the initial voltage applying 25 microvolts, carries out reading/verify behaviour subsequently Make.If reading/verification operation shows, chip current has reached required state (that is, the chip electricity that 00,01,10 or 11 are corresponding Stream), then can start multilamellar write operation.If the state needed for reaching, then improve the voltage being applied on BL electrode 74, can To increase 25 microvolts, or 50 microvolts.To carry out another one reading/verification operation subsequently, this process will be repeated, until realizing Required state.Above magnitude of voltage can be different.Carry out after write operation is read operation, in order to verify storing state.

Write-verification algorithm itself is relatively slow, because the write and read that to carry out taking second place operates more.This invention proposes a multilamellar Write operation, operates without alternately write and read during execution.This operation is real by applying a ramp voltage on BL electrode 74 Existing, on SL electrode 72, apply 0 voltage simultaneously, WL electrode 70 electrode applies a positive voltage, in selected storage A positive voltage is applied on chip substrate electrode 78.Unselected chip will be maintained at hold mode, i.e. at WL electrode 70 One 0/ negative voltage of upper applying, and on BL electrode 74, apply 0 voltage.Thus the bias condition of generation will be on buoyancy aid 24 Generation hole is injected, and is realized by ionization by collision mechanism.Storage chip 50 can be grasped in the reading that carries out of detection chip electric current simultaneously Making, electric current flows through the reading circuit 90 (see Figure 16 A-16C) coupled with source line 72.The chip current recorded on line direction, source is institute There is the integrating electric (see Figure 16 A-16C) of the storage chip 50 of common source line 72.Therefore, the storage chip of an only common source line 72 50 can be written into.This guarantees the change in accumulative chip current, be that the write operation of selected storage chip 50 causes it.

As shown in figure 17, the current potential of buoyancy aid 24 can increase over time because bias condition by ionization by collision mechanism to Buoyancy aid 24 is filled with hole.Once the change of chip current has reached required level (relevant with the state of storage chip 50), Then it is applied to the voltage on BL electrode 74 can be removed.By applying positive voltage (reverse biased) on electrode of substrate 78, flow into Base stage hole current to buoyancy aid 24 maintains the current potential of buoyancy aid 24.In this way, it is possible to carry out multilamellar write operation, hold Operate without alternately write and read during row.

Figure 16 A-16C gives reference generating circuit 92, is used for producing initial accumulated chip current in storage chip 50, Wherein storage chip 50 shares the same source line 72 being written into.Such as, at the beginning of the storage chip 50 of all common source lines 72 is produced The accumulative electric charge of beginning state, can be stored in electric capacity 94 (Figure 16 B).When electric charge needs write or reads from electric capacity 94, Transistor 96 is opened.It addition, fiducial chip 50R (Figure 16 C) is similar to a storage chip 50, it is also possible to be used for storing initial shape State.Utilization is similar to case, and write operation can be carried out on fiducial chip 50R, uses the accumulative chip current of source line 72.When Needing when the enterprising row write of fiducial chip 50R operates, transistor 96 is opened.Meanwhile, the substrate of fiducial chip is also applied with One positive bias, keeps its state.Fiducial chip 50R can be sized to: makes fiducial chip can store institute There is the maximum stored charge of storage chip 50, i.e. when the storage chip 50 of all common source lines 72 is all charged by positive charge.

It is similar to it, utilizes the multilamellar write operation of ionization by collision to realize: on BL electrode 74, apply a slope write Enter electric current rather than apply a ramp voltage at BL electrode 74.

In another example, band forms can be worn mechanism then by band and realizes, i.e. at BL electrode by multilamellar write operation Apply a ramp voltage on 74, on SL electrode 72, apply 0 voltage simultaneously, WL electrode 70 applies a negative electricity Pressure, applies 0/ positive voltage on the electrode of substrate 78 of selected storage chip 50.Unselected chip will be maintained at protecting Hold state, i.e. on WL electrode 70, apply 0/ negative voltage, and on BL electrode 74, apply 0 voltage.It addition, it is multiple BL electrode 74 can also be selected simultaneously, the write parallel to multiple chips.In selected storage chip, the current potential of buoyancy aid 24 will be due to Band forms is worn mechanism then and is raised by band.Selected storage chip 50 can carry out read operation, electricity at detection chip electric current simultaneously Stream flows through the reading circuit 90 coupled with source line 72.Level needed for once the change of chip current has reached is (with storage chip 50 State relevant), then being applied to the voltage on BL electrode 74 can be removed.If applying positive voltage, stream on electrode of substrate 78 The base stage hole current entered to buoyancy aid 24 maintains the current potential of buoyancy aid 24.In this way, it is possible to carry out multilamellar write operation, Operate without alternately write and read during execution.

Being similar to it, multilamellar write operation can also use band that band is worn mechanism class then and realize, and i.e. applies one on BL electrode 74 Individual slope reset current rather than on BL electrode 74 apply a ramp voltage.

In another one example, at programming operations simultaneously, can be by detection storage chip in bit line direction Upper curent change carries out read operation, and this electric current is through the reading circuit 90 (as shown in Figure 18 A) coupled with bit line 74.Represent not Can be used to verify the state of write operation with the fiducial chip 50R of storing state.Fiducial chip 50R can be by writing-verifying Operation is set, such as when all storage assemblies start for the first time.

In ramp voltage operates, the chip current of the write storage chip 50 produced, will be used to and fiducial chip The electric current of 50R contrasts, and is realized by reading circuit 90.During the operation of above-mentioned reading programming simultaneously, fiducial chip 50R Biased also with the bias condition identical with selected storage chip 50, now carry out be selected storage chip 50 write behaviour Make.Therefore, write operation needs to stop after reaching required chip status, to prevent from changing the state of fiducial chip 50R.For Slope current operates, and can sense voltage rather than the chip current of bit line 74.Bit-line voltage can use such as voltage induced Circuit (Figure 18 B) detects, such as " VLSI Design of Non-Volatile Memories ", Campardo G etc. (2005 Year), quote herein, for reference.

(without read-write operation alternately) in the example of a multilamellar write operation, given bit line direction uses One operation/scheme reading programming simultaneously, each storage chip 50 stores 2 bytes, it is desirable to each storage chip 50 can store 4 states.Along with the increase of electric charge in buoyancy aid 24,4 states can be expressed as " 00 ", " 01 ", " 10 ", “11”.In order to storage chip 50 is programmed to state " 01 ", state " 01 " corresponding for fiducial chip 50R will be activated. Thus, bias condition described above, will the fiducial chip 50R of selected storage chip 50 and " 01 " be used simultaneously.In source Apply 0 voltage on line electrode 72, electrode of substrate 78 applies a positive voltage, WL electrode 70 applies a positive electricity Pressure (by ionization by collision mechanism), applies a ramp voltage from 0 beginning on BL electrode 74 simultaneously.From low-voltage (such as 0 electricity Pressure) ramp voltage of beginnings, it is possible to the state of guarantee fiducial chip 50R will not change.

Subsequently, the voltage being applied on BL electrode 74 will raise.As a result, hole is injected into the buoyancy aid of selected chip 50 In 24, and the chip current of selected chip 50 increases therewith.The chip current once selecting chip 50 reaches " 01 " benchmark core The electric current of sheet, write operation i.e. stops, and the positive voltage being applied on BL electrode 74 and WL electrode 70 is i.e. removed.

As described above, the direct impulse voltage of periodicity can be applied on electrode of substrate 78, with constant forward bias Pressure difference, thus reduce the power consumption of storage chip 50.During this period, the operation of storage chip 50 can be by retouching briefly below State, now electrode of substrate 78 ground connection.When electrode of substrate 78 ground connection, the storage chip 50 being connected with electrode of substrate 78 is the most no longer located In hold mode.Therefore, the time of electrode of substrate ground connection must be shorter than the charge storage time of buoyancy aid, prevents buoyancy aid state at base It is charged electric charge during plate electrode base.Charge life (that is, charge storage time) in buoyancy aid 24, is not using described holding During pattern, because the millisecond order of magnitude, such as, see " A Scaled Floating Body Cell (FBC) Memory with High-k+Metal Gate on Thin-Silicon and Thin-BOX for 16-nm Technology Node and Beyond ", Ban etc., 92-92 page, VLSI technology conference (2008), quote herein, for reference.To reverse biased electrode During (such as electrode of substrate 78) applies positive pulse voltage, the state of storage chip 50 can be stored in buoyancy aid 24 it by refreshing Electric charge keeps.

Read operation can realize by applying following bias condition: applies 0 voltage on electrode of substrate 78, at SL Apply 0 voltage on electrode 72, selected BL electrode 74 applies a positive voltage, and on selected BL electrode 74 Apply a ratio and select positive voltage bigger on WL electrode 70.Unselected BL electrode 74 keeps 0 voltage, unselected WL electrode 70 keep 0 voltage or negative voltage.If electrode of substrate 78 is grouped (shown in such as Fig. 4 A-4C), then can unselected it A positive voltage is applied on electrode of substrate 78.In a specific non-limiting example, the voltage of about 0.0 volt is applied to On electrode 72, the voltage of about+0.4 volt is applied on electrode 74, and the voltage of about 0.0 volt is applied on electrode 70, and The voltage of about+1.2 volts is applied on electrode 78.Unselected electrode 74 keeps 0.0 volt, and unselected electrode 70 keeps 0.0 volt.Unselected electrode 78 (according to the packet situation of electrode of substrate 78 in Fig. 4 A and 4B) may remain in+1.2 volts (see Figure 19).Because the read operation carried out over time belongs to nanosecond, shorter very than charge life (charge storage time) is wanted Many, and now buoyancy aid 24 does not use holding operation to assist.Corresponding it, the execution of read operation does not interferes with and electrode 78 The state of the storage chip being connected, because the ground connection of electrode 78 the ofest short duration (nanosecond).

By applying following bias condition, can realize writing " 0 " operation on chip 50: apply one to SL electrode 72 Back bias voltage, applies one 0 or back bias voltage to WL electrode 70, applies one 0 or back bias voltage to electrode of substrate 78.The most selected chip SL electrode 72 unaffected, keep ground connection.If electrode of substrate 78 is grouped (shown in such as Fig. 4 A-4C), then can be not A positive voltage is applied on chosen electrode of substrate 78.In the case of hereinto, the p-n junction between 24 and 16 is forward bias, The hole in buoyancy aid 24 will be shifted.In a specific non-limiting example, the voltage of about-2.0 volts is applied to electrode On 72, the voltage of about 0.0 volt is applied on electrode 70, and is applied on electrode 78 by the voltage of about 0.0 volt.Not by Selected electrode 78 (according to the packet situation of electrode of substrate 78 in Fig. 4 A and 4B) may remain in+1.2 volts (see Figure 19).At base During plate electrode 78 ground connection, bipolar hole current is not had to be flowed in buoyancy aid 24.Therefore, the time that write " 0 " operation is required is more Short.Because the write carried out over time " 0 " operation belongs to nanosecond, shorter very than charge life (charge storage time) is wanted Many, and now buoyancy aid 24 does not use holding operation to assist.It, write " 0 " operation and do not interfere with unselected accordingly The state of storage chip 50, storage chip is connected with electrode 78, and the of short duration ground connection of electrode completes to write " 0 " operation.It is applied to Store the bias condition on very row 80 as shown in figure 20.Above-mentioned magnitude of voltage can also be different, if relative between above-mentioned electric charge Relation.

As shown in figure 21, for being alternately written into the bias condition of " 0 " operation, it is allowed to single byte is write.By following Condition is applied in selected storage chip 50: apply a positive voltage on WL electrode 70, applies one and bear on BL electrode 74 Voltage, applies 0/ positive voltage on SL electrode 72, applies 0 voltage on electrode of substrate 78.In the case of hereinto, by In being applied with a positive voltage on WL electrode 70, the current potential of buoyancy aid 24 will be raised by Capacitance Coupled.Make: the electricity of buoyancy aid 24 Position raises, and negative voltage is applied on BL electrode 74, the p-n junction forward bias between 24 and 18, and the hole on buoyancy aid 24 is fallen in transfer. In order to reduce in selected storage chip, the write " 0 " to the storage chip that other have identical row or column is disturbed, can be to applying Current potential optimize as follows: if it is assumed that the current potential with the buoyancy aid 24 of state " 1 " is V_FB1, then can be applied by setting Voltage on WL electrode 70 improves the current potential of buoyancy aid 24, can improve V_FB1/ 2, and-V_FB1/ 2 are just applied to BL electrode 74 Voltage.A positive voltage can be applied on SL electrode 72, reduce further other storage chip 50 in storage arrays The interference of write " 0 ", the array being disturbed does not shares SL electrode 72 with selected storage core.Unselected chip is still in Hold mode, 0 voltage being i.e. applied on WL electrode 70 or negative voltage, 0 voltage being applied on BL electrode 74, and be applied to Positive voltage on electrode of substrate 78, (according to the packet situation of electrode of substrate 78 in Fig. 4 A-4C).Because carry out over time writes Enter " 0 " operation and belong to nanosecond, than charge life (charge storage time) want short a lot, and now buoyancy aid 24 does not use Operation is kept to assist.It, write 0 operation and do not interfere with the state of unselected storage chip 50, store core accordingly Sheet is connected with electrode 78, and the of short duration ground connection of electrode completes to write " 0 " operation.

Still with reference to Figure 21, following bias condition can be applied in selected storage chip 50a: execute on electrode 72a Add one 0.0 volt, electrode 74a applies the current potential of 0.2 volt, electrode 70a applies the electricity of about+0.5 volt Position, applies the current potential of about 0.0 volt on electrode 78a；It is not connected with selected chip 50a with other at electrode 72n simultaneously SL electrode on apply the voltage of one about 0.0 volt, on electrode 74n and other BL not being connected with selected chip 50a are electric Extremely one 0.0 volt of voltage of upper applying, applies one 0.0 on electrode 70n with other WL electrodes not being connected with selected chip 50a Volt voltage, applies+1.2 volt voltages with selected chip 50a on electrode 78n with other electrode of substrate not being connected.Above Magnitude of voltage can be different.

In fig. 22, give chip 50a under write " 1 " operation then worn by band by band, be applied to storage arrays 80 it Bias condition, wherein, applies a back bias voltage on WL electrode 70a, applies a positive bias on BL electrode 74a, at SL electricity Apply 0 voltage on the 72a of pole, electrode of substrate 78a applies 0 voltage.It is applied to the back bias voltage of WL electrode 70a and executes It is added to the positive bias of BL electrode 74a, hole can be produced on the buoyancy aid 24 of selected storage chip 50a and inject.Unselected storage Deposit chip 50 and will be still in holding pattern, on unselected WL electrode 70, apply 0/ negative voltage (number of times, an electrode simultaneously 70n is not connected with selected chip 50a with every other WL electrode 70), and on unselected BL electrode 74, apply one Individual 0 voltage (now, electrode 74b, 74n and every other BL electrode 74, be not connected with selected chip 50a), and not by (now electrode of substrate 78 is grouped according to shown in Fig. 4 A and 4B, and is scheming to apply a positive voltage on selected electrode of substrate 78 In 22, electrode 78n is not connected with selected chip 50a with every other electrode of substrate 78).

Still with reference to Figure 22, following bias condition can be applied in selected storage chip 50a: execute on electrode 72a Add the current potential of about 0.0 volt, electrode 74a applies the current potential of about+1.2 volts, electrode 70a applies one The current potential of about-1.2 volts, applies the current potential of about 0.0 volt on electrode 78a；Simultaneously in unselected storage chip On, electrode 72 applies the current potential (defining according to previous section) of about 0.0 volt, unselected electrode 74 is executed Add the current potential (defining according to previous section) of about 0.0 volt, unselected electrode 70 applies one about 0.0 volt Current potential (according to previous section define), on unselected electrode of substrate 78 apply+1.2 volt current potentials (according to above Chapters and sections define).Above magnitude of voltage can be different.

Shown in Figure 23 A, in this invention, another example of storage chip 150.Chip 150 includes a substrate 12, There is the first conduction type, such as n-type conduction type.Substrate 12 is generally made up of silicon, but can comprise germanium, silicon-germanium, silicon- Arsenic, CNT or other known semi-conducting materials.Base plate 12 has a surface 14.First area 16 has the second conduction Type, such as n-type, is positioned on base plate 12, towards surface 14.Second area 18 has the second conduction type, also is located at base plate 12 On, towards surface 14.As it can be seen, second area 18 separates with first area 16.First and second regions 16 and 18 are all passed through One doping process is processed on the composition material of substrate 12, and use is to be currently known and the doping process of typical case.It addition, also Employ a solid state diffusion process, process the first and second regions 16 and 18.

As it can be seen, embedding layer 22 has the second conduction type, process the most on the substrate 12, be embedded to substrate 12 In.Embedding layer 22 can also be processed on the material of substrate 12 by ion doping technique.It addition, embedding layer 22 can also Obtained by epitaxial growth.The floating body region 24 of substrate 12 has the first conduction type, such as p-type conduction type, by substrate table Face, the first and second region 16&18, insulating barrier 26 and embedding layer 22 surround.Insulating barrier 26 (such as shallow-trench isolation (STI)), permissible Use Si oxide.When chip 150 is connected into array 180, chip 150 is separated by insulating barrier 26 with adjacent chip 150, Thus constitute storage assembly as shown in figure 24.Door 60 is between region 16 and 18, on surface 14.Door 60 passes through insulating barrier 62 insulate with surface 14.Insulating barrier 62 can use silicon oxide and/or other insulant, including height-K insulant, including But it is not limited to peroxidating tantalum, titanium oxide, zirconium oxide, hafnium oxide and or aluminium oxide.Door 60 can use polycrystalline silicon material or metal Gate electrode, such as tungsten, tantalum, titanium and their nitride

Chip 150 also includes wordline (WL) electrode 70, is connected with door 60, in source line (SL) electrode 72, with region 16 and 18 One of be connected (icon and 16 is connected, but can also be connected with 18), in bit line (BL) electrode 74, with region 16 and 18 separately Outer one is connected, and embedment trap (BW) electrode 76 is connected with embedding layer 22；Further, on the position below embedding layer 22, substrate electricity Pole 78 is connected with base plate 12.Embedment well area 22 contact can by region 20 realize (region 20 has the second conduction type, And it is connected with embedment well area 22)；Simultaneously with being connected of substrate regions 22, can be realized by region 28, region 28 has There is the first conduction type, be connected with substrate regions 12, as shown in fig. 23b.

In another one example, storage chip 150 has p-type conduction type, (the i.e. first conduction type), and n-type It is the second conduction type, as described above.

As shown in figure 25, inside storage chip 150, by embedment well area 22, buoyancy aid 24, SL and BL region 16 and 18 On, define n-p-n dipole elements 130a and 30b.The operating instruction of storage chip is as follows.It will be seen that storage chip herein As hereinbefore, similar with being biased on above-mentioned storage chip 50n-type electrode of substrate 78, this is in core to the operating principle of 150 A bias is applied on the n-type embedment trap electrode 76 of sheet 150.In this example, P-type substrate 12 ground connection of storage chip 150, will The reversal of the p-n joint between substrate 12 and embedding layer 22, thus prevent from producing leakage current from substrate 12 and embedding layer 22.

Keep the operation can be to realize, now by ground electrode 72 by applying a reverse biased just on BW electrode 76 And/or electrode 74 ground connection.If buoyancy aid 24 has been filled with positive charge (such as, be set to one state), by SL region 16, buoyancy aid 24 and The bipolar transistor of embedment well area 22 formation, and the bipolar transistor formed by BL region 18, buoyancy aid 24, substrate regions 22 To open.

A part for bipolar transistor current will be flowed in floating body region 24 and (usually become base current), and keep One state purgation data.The efficiency keeping operation can be improved by the design of dipole elements 130a, 130b, will imbed Well layer 22, floating body region 24, region 16,18 composition one low gain dipole elements, wherein bipolar gain be defined as-from BW electricity The collector current of pole 76 outflow is than the base current of upper inflow floating body region 24.

To storing the storage chip of data under state " 0 ", dipole elements 130a, 130b will not open, final base Pole hole current can be flowed in floating body region 24.Make, continue to keep this state in state " 0 " purgation storage chip.

Keep operation can the carrying out of parallel batch, be generally stored array at BW electrode 76 (as reverse biased electrode) All chips 150 on 180 are shared, or are at least shared by the chip 150 in a part of array 180.BW electrode 76 can also It is grouped, it is allowed to the selected part in storage arrays 180 carries out the biased operation of independence.It addition, because of BW electrode 76 not The selection of board address can be used for, when keeping operation, the access of storage chip would not be caused interruption.

Realizing keeping operation, the bias to chip 150 applying includes: 0 voltage is applied on BL electrode 74, and 0 voltage applies On SL electrode 72,0 voltage or negative voltage are applied on WL electrode 70, and positive voltage is applied on BW electrode 76, and 0 voltage is applied to Electrode of substrate 78.In a specific non-limiting example, the voltage of about 0.0 volt is applied on electrode 72, about 0.0 The voltage of volt is applied on electrode 74, and the voltage of about 0.0 volt is applied on electrode 70, and by the electricity of about+1.2 volts Pressure is applied on electrode 76, is applied on electrode 78 by about 0.0 volt of voltage.Above magnitude of voltage can be different.

Read operation on chip 150 can realize by applying following bias condition: applies one on BW electrode 76 Individual positive voltage, applies 0 voltage on SL electrode 72, applies a positive voltage on selected BL electrode 74, and in choosing Apply the positive voltage that the selected WL electrode 70 of a ratio is bigger on fixed BL electrode 74, on electrode of substrate 78, apply one simultaneously 0 voltage.When chip 150 belongs to array 180, unselected BL electrode 74 (such as 74b...74n) will remain in 0 voltage, and And unselected WL electrode 70 (as 70n is not connected with selected chip 150a with other WL electrodes 70), will remain in 0 or negative Voltage.In a specific non-limiting example, the voltage of about 0.0 volt is applied on electrode 72, about+0.4 volt Voltage be applied on electrode 74a, the voltage of about 0.0 volt is applied on the electrode 70a that selectes, and will about+1.2 volts Voltage be applied on electrode 76, on electrode 78 apply one 0.0 volt, as shown in figure 26.Unselected electrode 74 keeps 0.0 Volt, unselected electrode 70 keeps 0.0 volt, as shown in figure 26.Above-mentioned magnitude of voltage can also be different, if between above-mentioned voltage it Relativeness.Therefore, under above-mentioned bias condition, unselected storage chip (150b, 150c, 150d) will still It is in holding pattern, maintains the state of corresponding buoyancy aid 24.It addition, keep operation will not interrupt to selected storage chip 150a it Read operation.

In order to by 0 write chip _ 150, need to apply a back bias voltage to SL electrode 72, apply one 0 to WL electrode 70 Or back bias voltage, apply one 0 or positive bias to BW electrode 76, apply 0 voltage to electrode of substrate 78.Unselected chip The SL electrode 72 of 150, is not connected it with selected chip 150a, will keep ground connection.In the case of hereinto, between 24 and 16 with And the p-n junction between 24 and 18 is forward bias, the hole in buoyancy aid 24 will be shifted.A specific non-limiting example In, the voltage of about-2.0 volts is applied on electrode 72, the voltage of about-1.2 volts is applied on electrode 70, about+ The voltage of 1.2 volts is applied on electrode 76, and is applied on electrode 78 by the voltage of about 0.0 volt.Above-mentioned magnitude of voltage is also Can be different, if the relativeness between above-mentioned electric charge.

Due to write " 0 " operation relate only to SL electrode 72 apply a negative voltage (thus to full line be applied with this bear Voltage), the bias condition of all unselected chips is the most identical.It will be seen that unselected storage chip execution is one Keeping operation, BL and SL electrode is all about 0.0 volt simultaneously.

Therefore, write " 0 " operation that operation will not be interrupted in storage chip is kept.Core is being stored it addition, unselected Sheet, during write " 0 " operation, will be still in keeping mode of operation.

Additionally there is write " 0 " operation (different with described above) that is a kind of and that allow single byte write, it is simply that at WL electrode Apply a positive voltage on 70, BL electrode 74 applies a negative voltage, SL electrode 72 applies 0/ negative voltage, Apply one 0 or positive voltage on BW electrode 76, and on electrode of substrate 78, apply 0 voltage.In the case of hereinto, due to Being applied with a positive voltage on WL electrode 70, the current potential of buoyancy aid 24 will be raised by Capacitance Coupled.Make: the current potential of buoyancy aid 24 Raising, negative voltage is applied on BL electrode 74, the p-n junction forward bias between 24 and 16, and the hole on buoyancy aid 24 is fallen in transfer.Execute Bias on the WL electrode 70 being added to select and selected BL electrode 74, will have influence on and select storage chip 150 and have identical The unselected storage chip 150 of WL or BL electrode.Thus decrease in storage arrays 180 and cause to other storage chip 150 The write " 0 " of interference, the current potential applied can optimize as follows: " if it is assumed that have the electricity of the buoyancy aid 024 of state 01 Position is V_FB1, then can be improved the current potential of buoyancy aid 24 by the voltage that setting is applied on WL electrode 70, V can be improved_FB1/ 2, And-V_FB1/ 2 voltages being just applied to BL electrode 74.This reduces the potential change of buoyancy aid 24, including being in state " 1 " Unselected chip 150, said chip with selected from V_FB1To V_FB1The chip 150 of/2 has identical BL electrode.Right In being in " 0 " state, and the storage chip that selected chip 150 has identical WL electrode, if the current potential of buoyancy aid 24 raises foot Enough high (i.e., at least V_FB/ 3, illustrate to see below), then two n-p-n dipole elements 130a and 130b will not be opened, or base stage Hole current is of a sufficiently low, thus can not raise the current potential of buoyancy aid 24 in time so that write operation is capable of (during write operation Between).This invention determines: buoyancy aid 24 current potential raises V_FB/ 3 be enough to prevent the rising of buoyancy aid 24 current potential too much.Then exist Apply a positive voltage on SL electrode 72, reduce further in storage arrays, need not write other storage chip of 0 interference 150.Unselected chip will be maintained at hold mode, as applied 0/ negative voltage on WL electrode 70, and at BL electricity 0 voltage is applied on pole 74.In unselected chip 150, do not share with selected chip 150 WL or BL electrode it, will depend on So being in hold mode, i.e. now, 0/ negative voltage is applied on unselected WL electrode, 0 voltage be applied to unselected it On BL electrode 74.”

In a specific non-limiting example, for chosen chip 150, the voltage of about 0.0 volt is applied On electrode 72, the voltage of about 0.2 volt is applied on electrode 74, and the voltage of about+0.5 volt is applied on electrode 70, And the voltage of about+1.2 volts is applied on electrode 76, about 0.0 volt of voltage is applied on electrode 78.For the most selected Fixed chip, do not share with selected chip 50 identical WL electrode or BL electrode it, about 0.0 volt of voltage is applied to electrode 72 On, about 0.0 volt of voltage is applied on electrode 74, and about 0.0 volt of voltage is applied on electrode 70, and about+1.2 volt voltages apply On electrode 76, about 0.0 volt of voltage is applied on electrode 78.Figure 27 gives selected storage chip 150 in storage arrays 180 Bias condition with unselected storage chip 150.Above magnitude of voltage can be different.

As shown in Figure 28 A-28B, during write " 0 " operation, the bias condition of selected storage chip.Shown in Figure 28 C-28H, Bias condition for unselected storage chip 150.Bias condition shown in Figure 28 C-28D is: with selected storage chip 150a has the unselected storage chip 150 (such as 150B, Figure 27) of colleague mutually.Bias condition shown in Figure 28 E-28H is: With the unselected storage chip 150 (such as 150c, Figure 27) that selected storage chip 150a has same column.With selected storage Chip 150a neither have go together mutually the most do not have same column it, unselected storage chip 150a (as in Figure 27 it 150d), its bias condition is as shown in Figure 28 G-28H.

During the write " 0 " of storage chip 150 operates (single byte write " 0 " operation, as mentioned above), it is necessary to have applying Reverse biased on BW electrode 76, thus keep the state of unselected chip 150, especially have with selected chip 150a There is the storage chip of identical row or column；Owing to bias condition can change the current potential of storage chip 150, and without intrinsic bipolar group Part 130 (being made up of embedment well area 22, buoyancy aid 24, region 16 and 18) reaches poised state again.It addition, holding operation will not Write " 0 " operation in storage chip 150 can be interrupted.

Also have write 1 operation that one can be carried out in storage chip 150, use ionization by collision or band that band forms is worn Then mechanism, illustrated example is shown in " A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage(GIDL)Current for Low-power and High-speed Embedded Memory” Yoshida etc., the 913-918 page, International Electro assembly conference (2003), it is hereby incorporated, for reference.

In Figure 29, give selected storage element 150a, the bias feelings when using band that band is worn write " 1 " operation then Condition.It is applied to the back bias voltage of WL electrode 70a and is applied to the positive bias of BL electrode 74a, hole can be produced on buoyancy aid 24 and inject. The positive bias being applied on BW electrode 76a will keep with the above the positron obtained in the buoyancy aid 24 of discussion.Unselected unit 150 will be still in holding pattern, and on unselected WL electrode 70, (in figure 27,70n is with other not for applying 0 or negative voltage The WL electrode 70 being connected with unit 150a), execute on other BL electrodes 74 not being connected with unit 150a at BL electrode 74b, 74n Add 0 voltage.Positive bias is applied to BW electrode 76, carries out keeping operation, write " 1 " behaviour of selected storage element will not be interrupted Make.Meanwhile, when selected storage element writes " 1 " operation, unselected storage element 150 will always be in protecting Hold operation.

Multilamellar operation can also be carried out on storage element 150.As shown in Figure 6, can protect on storage element 50 Hold operation, keep its multilayered state.(buoyancy aid electric current is the letter of BW electrode 76 current potential for buoyancy aid current relationship between different buoyancy aids 24 Number (Fig. 6 B)), (electrode of substrate buoyancy aid electric current is electrode of substrate to be similar to the relation between the difference buoyancy aid electric current of electrode of substrate 78 The function (Fig. 6 A) of 78 current potentials).As shown in Figure 6B, at certain BW electrode 76 current potential V_HOLDUnder, the floating body potential of difference；Flow into Junction leakage balance between the electric current and buoyancy aid 24 and region 16&18 of buoyancy aid 24.What buoyancy aid 24 current potential of difference represented is The electric charge of difference, thus represent the different conditions of storage element 150.The storing state of difference can by use described herein as it Keep/prepare operation to maintain.

Below layer write operation more than carrying out on storage element 150 is illustrated, non-alternately read and write operation.In order to realize This operation, need to apply 0 volt of voltage on SL electrode 72, applies a positive voltage, apply on BW electrode 76 on WL electrode 70 One positive voltage (reverse biased), applies 0 volt of voltage on electrode of substrate 78, applies an increasing simultaneously on BL electrode 74 Big ramp voltage.Thus the bias condition of generation will produce hole injection on buoyancy aid 24, be realized by impact ionization. Storage element 150 can carry out read operation at detector unit electric current simultaneously, and electric current flows through the reading circuit 90 coupled with source line 72. (when source line current is equal to bit line current+BW electric current, and electric current is from imbedding trap to source for the cell current of measurement on line direction, source Line direction and bit line-source line orientation measurement), belong to the integrating electric of all storage elements 150；The most all storage elements are altogether Enjoy identical source line 72 (such as, in Figure 16 A-16C, for the example of detection resources line directional current.In storage arrays 80 and storage In poke group 180, it is also adopted by identical detection scheme).Therefore, only the storage element 150 of a common source line 72 can be write Enter.This guarantees the change in accumulated unit electric current, be that the write operation of selected storage element 150 causes it.

Thus the bias condition of generation will produce hole injection on buoyancy aid 24, be realized by impact ionization.Figure 17 Shown in, result is exactly that the current potential of buoyancy aid 24 can raise in time.Level needed for once the change of cell current has reached is (with storage The state of memory cell 150 is relevant, and levels of current is the most as shown in figure 17), then being applied to the voltage on BL electrode 74 can be removed. By applying positive voltage on BW electrode 76, the base stage hole current being flowed into buoyancy aid 24 maintains the current potential of buoyancy aid 24.Pass through This mode, it is possible to carry out multilamellar write operation, operates without alternately write and read during execution.

In another example, band can be worn effect then by band and realizes, i.e. on BL electrode 74 by multilamellar write operation Apply a ramp voltage, on SL electrode 72, apply 0 voltage simultaneously, WL electrode 70 applies a negative voltage, Apply a positive voltage on BW electrode 76, electrode of substrate 78 applies 0 voltage.Band is worn then imitate owing to employing band Should, the current potential of buoyancy aid 24 increases.Storage element 50 can carry out read operation at detector unit electric current simultaneously, and electric current flows through The reading circuit 90 coupled with source line 72.Once the change of cell current has reached the required level (state with storage element 50 Relevant), then being applied to the voltage on BL electrode 74 can be removed.If applying positive voltage on electrode of substrate 78, it is flowed into floating The base stage hole current of body 24 maintains the current potential of buoyancy aid 24.In this way, it is possible to carry out multilamellar write operation, during execution Operate without alternately write and read.

Being similar to it, multilamellar write operation can also use band that band is worn effect class then and realize, and i.e. applies one on BL electrode 74 Individual slope reset current rather than on BL electrode 74 apply a ramp voltage.

Similar it, when realizing reading-programming operations by the change on bit line 72 direction of the detector unit electric current, (wherein bit line current is equal to SL electric current+BW electric current), needs to be realized by the reading circuit 90 coupled with bit line 74, such as Figure 18 A Shown in.Slope current is operated, the voltage of bit line 74 can be sensed rather than remove sensing unit electric current.As shown in figure 18b, Bit-line voltage can be sensed, it is, for example possible to use voltage sense circuit.

Another one example in storage element 150 operation: employ silicon controlled rectifier (SCR) (SCR) principle, special in the U.S. Disclosed in profit application No.12/533661, date of filling is on July 31st, 2009, is hereby incorporated, for reference.

Figure 30 and 31 gives another example of storage element 50 illustrated in this invention.In this example, single Unit 50 has fin structure 52, manufactures on the substrate 12, and substrate 12 has the first conduction type (such as n-type conduction type) so that Can extend at substrate surface and obtain a three dimensional structure, fin 52 is generallyperpendicular extend to substrate 12 upper surface (and it On).Fin structure 52 includes the first and second region 16&18, has the first conduction type.Buoyancy aid 24 is by table on fin 52 Face, the first and second region 16&18 and insulating barrier 26 surround (insulating barrier 26 can be seen on the top view of Figure 34).When When unit 50 is connected into array 80, unit 50 is separated by insulating barrier 26 with adjacent unit 50, thus constitute as shown in Figure 2 it Storage assembly (array 80).Buoyancy aid 24 conducts electricity, and has the second conduction type, (such as p-type conduction type), can pass through ion Doping process or epitaxial growth processing obtain.Fin 52 is generally made up of silicon, but can comprise germanium, silicon-germanium, silicon-arsenic, carbon nanometer Pipe or other known semi-conducting materials.

As shown in figure 30, storage element assembly 50 also includes a door 60, is positioned at the both sides of buoyancy aid substrate regions 24.Separately Outward, door 60 can include three sides of buoyancy aid substrate regions 24, as shown in figure 31.Door 60 by insulating barrier 62 and buoyancy aid 24 every Open (insulation).Door 60 is between the first and second regions 16 and 18, adjacent with buoyancy aid 24.

Assembly 50 includes following electrode: wordline (WL) electrode 70, source line (SL) electrode 72, bit line (BL) electrode 74, With electrode of substrate 78.Electrode 70 is connected with door 60.Electrode 72 is connected with first area 16；Electrode 74 is connected with second area 18. It addition, electrode 72 can also be connected with second area 18, and electrode 74 can be connected with first area 16.Electrode 78 and substrate 12 It is connected.

Figure 32 and 33 gives another example of storage element 150 illustrated in this invention.In this example, single Unit 150 has fin structure 52, manufactures on the substrate 12, enabling extends at substrate surface and obtains a three dimensional structure, fin The 52 generallyperpendicular upper surfaces (on and) extending to substrate 12.Fin structure 52 is conducted electricity, and builds in embedment well layer 22.District Ion farrowing technique can be passed through in territory 22, processes, it is also possible to obtained by epitaxial growth on the material of substrate 12.Embedment Buoyancy aid substrate regions 24 is insulated by well layer 22 with main body substrate 12, and 24 have the first conduction type (such as p-type conduction type).Fin Type structure 52 includes the first and second regions 16,18 (having the second conduction type, such as n-type conduction type).Therefore, around floating Body 24 be: the upper surface of fin 52, the first and second regions 16 and 18 are, and embedment well layer 22, and insulating barrier 26 (see Figure 34). When unit 150 is connected into array 80, unit 150 is separated by insulating barrier 26 with adjacent unit 150, thus constitutes such as Fig. 2 Shown storage assembly.Fin 52 is generally made up of silicon, but can comprise germanium, silicon-germanium, silicon-arsenic, CNT or other The semi-conducting material known.

As shown in figure 32, storage element assembly 150 also includes a door 60, is positioned at the both sides of buoyancy aid substrate regions 24.Separately Outward, door 60 can include three sides of buoyancy aid substrate regions 24, as shown in figure 33.Door 60 by insulating barrier 62 and buoyancy aid 24 every Open (insulation).Door 60 is between the first and second regions 16 and 18, adjacent with buoyancy aid 24.

Assembly 150 includes following electrode: wordline (WL) electrode 70, source line (SL) electrode 72, bit line (BL) electrode 74, Embedment trap (BW) electrode 76 and electrode of substrate 78.Electrode 70 is connected with door 60.Electrode 72 is connected with first area 16；Electrode 74 with Second area 18 is connected.It addition, electrode 72 can also be connected with second area 18, and electrode 74 can be with first area 16 phase Even.Electrode 76 is connected with embedding layer 22；Electrode 78 is connected with substrate 12.

In Figure 34, give the top view of storage element 50/150 in Figure 30 and 32.

It can be seen that thus constitute a quasiconductor storage with conduction buoyancy aid explanation before this invention Deposit.This invention also includes the function keeping storing state, or periodic refresh parallel, without algorithm operates.Therefore, it can not Interruption carry out bin operation.The explanation made above, for the people being familiar with this technology, is can to manufacture also at present The optimal mode of use, the people being familiar with this technology will be appreciated from the scheme of various derivative deformation, combination, particular instance, side Method and the equivalents of citing.This invention is not limited to example described above, method, example, and all examples and method are equal Belong to the scope and principle of this invention right.

In a buoyancy aid stores, the storing state of difference is represented by the difference quantity of electric charge of buoyancy aid.At " ACapacitor- Less1T-DRAMCell " (S.Okhonin etc.) the 85-87 page, IEEE electronic building brick communication, volume 23 (in February, 2002) (" Okhonin-1: "), and " MemoryDesignUsingOne-TransistorGainCellonSOI " T.Ohsawa waits It, the 152-153 page, technical digest, IEEE ISSCC in 2002, (in February, 2002) (" Ohsawa-1 "), carry Go out to need to consider that one ties (2 electric pressures) at standard MOSFET individual character.Use more than or equal to 2 electric pressures, in standard In the buoyancy aid of MOSFET store data it, it is possible in a storage element spring as one 2 system words knot, such as " The Multistable Charge-Controlled Memory Effectin SOI Transistors at Low Temperatures " Tack etc., the 1373-1382 page, IEEE electronic building brick processes, volume 37, in May, 1900 (" Tack "), Quote herein, for reference；Also include United States Patent (USP) 7542345 " Multi-bit memory cell having Electrically floating body transistor, and method of programming and reading Same ", authorize artificial Okhonin etc., (" Okhonin-2 ").Tack describes, standard MOSFET (on SOI Build) buoyancy aid in store more than two states, by manipulation " backgate " realize-backgate is silicon trench bottom shared for MOSFET A conductive layer one of under oxide (BOX).Okhonin-2 discloses and obtains more than two kinds of sides of voltage status on buoyancy aid Method, uses intrinsic to double-click junction transistors (BJT) and realizes, and BJT builds in two source/drain areas of standard MOSFET, from And produce reading and write current.

Generally in bin designs, the sensing of a storage element and method state for design be particularly significant it. It is also such for storing for buoyancy aid DRAM.In current technology, employ the key element of difference and method to carry out read operation, as At " A Design of a Capacitor-less1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory " (Yoshida etc.) 913- In page 918 disclosed it, International Electro assembly meeting (2003) (" Yoshida "), be hereby incorporated, for reference；And in U.S. State's patent 7301803 " Bipolar reading technique for a memory cell having an Electrically floating body transistor " (" Okhonin-3 "), it is hereby incorporated, for reference；Also have " An18.5ns 128Mb SOI DRAM with a Floating Body Cell " (Ohsawa etc.) 458-459, page 609, ISSCC (2005) (" Ohsawa-2 "), is hereby incorporated, for reference.In Yoshida and Okhonin-3, all Illustrating a kind of method, produce read current from a standard MOSFET buoyancy aid storage element, this storage element passes through SOI- CMOS technology manufactures.Okhonin-3 illustrates to use intrinsic BJT transistor (being positioned among standard MOSFET architectures), produces Read current.Ohsawa-2 discloses a kind of detailed inductive scheme, uses standard MOSFET buoyancy aid buoyancy aid 24, can at SOI and Realize on standard silicon chip.

Write a logical zero to buoyancy aid DRAM cell, in the prior art, be directly to transmit it.Or can be by source The current potential of line or bit line drags down, by the knot forward bias of buoyancy aid, remove hole charge (if any).Write logic 1 the most generally makes With band, band is worn then (the also referred to as electric leakage of door induced drain or GIDL), or ionization by collision method realizes.

In buoyancy aid DRAM cell, write logical zero is that to transmit it (be exactly that transmission is directly biased into source electrode or drain electrode to straight line Knot (standard MOSFET), thus remove the major part carrier in buoyancy aid, write logical zero), writing logic 1 then has difference Technology.Band can be worn effect then by door induction band by write logic 1, is described in the example of Yoshida.At Yoshida Substantially method be: suitable negative voltage is applied on storage element zigzag (door) electrode, positive voltage that simultaneously will be suitable It is applied in the bit line electrode (drain electrode) of selected storage element, and by source line electrode (source electrode) ground connection.It is applied to WL electrode negative Voltage and the positive voltage being applied to BL electrode, will produce by force near the door between the drain region of mosfet transistor and floater area Strong electric field (being therefore it " door induction " part of GIDL).Thus make energy the band near door and drain knot overlapping area violent it It is bent upwards so that electronics is worn then to conduction band from valence band, leaves hole in valence band.Through the electronics of band becoming drain electrode Leakage current (is it " drain leakage " part of GIDL), during hole is injected into floating body region 24 simultaneously, and by hole electricity Lotus creates logic 1 state.This process is the most common, has accompanying drawing explanation the (the especially the 3rd in Yoshida Fig. 2, Fig. 6 of page, and Fig. 9 of page four).

The method also having one write logic 1, use is ionization by collision, such as " ANew1TDRAM Cell with Enhanced Floating Body Effect " Lin and Chang, the 23-27 page, ieee international symposium-storing technology, set Meter and test (2006) (" Lin "), be hereby incorporated, for reference.In Lin, the general method of use is: by storage element it Door and bit line (drain electrode) electrode bias simultaneously, in order to positive voltage can be used to write, simultaneously by source line (source electrode) ground connection.Improve door it Current potential, to positive voltage, can improve the current potential of floating body region, because the capacitance coupling effect of door insulating barrier.Associate it, be The positive voltage of drain electrode can make intrinsic n-p-n double-click transistor (drain electrode (n=colelctor electrode) to buoyancy aid (p=base stage) to source electrode (n =emitter stage)) open, no matter on storage element storage be logic 1 or logical zero.Wherein, at buoyancy aid (base stage) and drain electrode (collection Electrode) between the p-n junction voltage of reverse bias will produce a small area analysis, flow through knot.Portion of electrical current will with hot carrier it Form, by electric field acceleration, flows through transistor junction.These hot carriers and the atomic collision in semiconductor lattice, will be near knot Produce hole-electron pair.Electronics will be swept drain electrode (colelctor electrode) by electric field, become bit line (colelctor electrode) electric current, and hole will It is swept up floating body region, becomes hole charge, produce logic 1 state.

At present, major part work is all to carry out it on SOI, and SOI (SOI) is generally more expensive than silicon chip technique.Have Part work is devoted to reduce the cost manufacturing buoyancy aid DRAM, starts to carry out on silicon chip.At " Siliconon Replacement Insulator (SRI) Floating Body Cell (FBC) Memory " 165-in (S.Kim etc.) Page 166, technical digest, in VLSI technology conference (2010) (" S.Kim "), enumerate a kind of technique, it is possible to have the structure of selection Embedment area of isolation, quotes herein, for reference.In the example of S.Kim, construct silicon chip transistor.Then by manufacturing One substitutes SOI (SRI) structure.Below elemental floating body, there is layer of material, through selective etch, use insulator to enter Row is replaced, and produces the similar effect of SOI.Another process is: has the generation space of selection, and uses insulator to fill, Such as " A4-bit Double SONOS Memory (DSM) with 4Storage Nodes per Cell for Ultimate Multi-Bit Operation " Oh etc., the 58-59 page, technical digest, VLSI technology conference (2006) (" Oh "), draws at this With, for reference.

Major part work at present all refers to the (Silicon-on-insulator) MOSFET lateral of standard, and source electrode and drain electrode wherein are respectively positioned on quasiconductor table Face, is connected with the metal system of semiconductor surface.In a kind of buoyancy aid DRAM cell, employ vertical MOSFET, see “Vertical Double Gate Z-RAM technology with remarkable low voltage operation For DRAM application " J.Kim etc., the 163-164 page, VLSI technology conference (" J.Kim "), it is hereby incorporated, for Reference.In the scheme of J.Kim, buoyancy aid is by a two sides door, a source region, top and embedment drain region, a lower section Constitute.Drain electrode is connected with a tap region, enabling the conduction handle that will imbed drain region and a surface connects Come.

Another method employs standard lateral MOSFET on buoyancy aid DRAM cell, special by SProvisional Patent-U.S. Profit application discloses 2010/0034041 and delivers, and donor Widjaja (" Widjaja ") is hereby incorporated, for reference.Widjaja Illustrate a kind of standard lateral MOSFET buoyancy aid DRAM cell, silicon chip is realized by an embedment trap and a substrate, buries Enter trap and substrate constitutes vertical silicon controlled rectifier (SCR) (SCR), separately in substrate, embedment trap, buoyancy aid and source electrode (or drain electrode) region Build a P1-N2-P3-N4 structure.This arrangement works mode is similar to two bipolar transistor (BJT) assemblies and is connected, and one Individual n-p-n (N2-P3-N4) and a p-n-p (P3-N2-P1), can be carried out by the electric charge controlling floating body region (P3) upper Operation.

In the prior art, structure and the operation of standard MOSFET assembly is widely known.As shown in Figure 90 A, it is one The standard metal of individual citing-Oxide-Semiconductor Field effect transistor (MOSFET) assembly 100.MOSFET assembly 100 includes one Individual substrate regions, has the first conduction type 82, (as shown being p-type), the first and second regions 84 and 86, has second Conduction type (as shown is n-type), is positioned on surface 88, and a door 90, by insulating barrier 92 and semiconductor surface area Separate.Door 90 is between region 84 and 86.Insulating barrier 96 can be used to separate the transistor component in silica-based version 82 and other Assembly.

As shown in Figure 90 B, a MOSFET assembly 100 can also include a well area 96A, has the first conduction type (as shown being p-type), is positioned on substrate regions 82A and (has the second conduction type, as shown be n-type), Yi Ji One and second area 84A and 86A, there is the second conduction type, be positioned on the 88A of surface.It addition, door 90A, by insulating barrier 96 with Separately, page is between the first and second regions 84,86 for region, surface 88A.Insulating barrier 96A can be used to separate embedment well area Transistor component upper for 94A and other assemblies.MOSFET assembly 100 and MOSFET assembly 100A all uses silicon chip CMOS technology structure Build.

As shown in Figure 90 C, MOSFET assembly 100B does not uses SOI technique construction.MOSFET assembly 100B includes one Groove region, has the first conduction type 82B, (as shown being p-type), the first and second region 84B and 86B, has second and lead Electricity type (as shown being n-type), is positioned on the 88B of surface, and a door 90B, by insulating barrier 92B and semiconductor surface area Territory separates.Door 90B is between 84B and 86B of region.Groove region 82B is separated from side with other assemblies by insulating barrier 96B, Bottom is separated by insulating barrier 83B.Alternatively, it is also possible to add a conductive layer (not shown) on the insulating barrier 83B of bottom, it is used for As " backgate ", it is connected with groove region 82B by insulating barrier 83B.

Transistor 100,100A and 100B all become n-channel transistor, because can be by executing to door 90,90A and 90B Add a corresponding voltage to open transistor；And if it is applied with gate voltage, the purgation p-type material being positioned at door will be anti- Turn, work with n-type conduction type.Thus realize inside MOSFET100, turn between two n-type regions 84 and 86, as 84A and 86A of MOSFET100A, and 84B and 86B of MOSFET100B.In the prior art, the conduction type in all regions All can invert, (that is, the region of the first conduction type can become n-type, and the region of the second conduction type can become p- Type), to produce p-trench transistor.Generally, n-trench transistor is the most common in storage element (includes all types and skill The storage element of art) because major part carrier electrons is respectively provided with locomotivity and (in p-trench transistor, has mobile energy Power is major part carrier hole), thus the transistor realizing same size has a bigger reading electric current, but p-groove Transistor can also be as a kind of design.

Hereinafter, just illustrate a kind of semiconductor memory assembly, there is conduction buoyancy aid, use reverse bias region to subtract Little storage assembly size.In a storage element, the binary information of one or more word knot can be stored.Also illustrate simultaneously Construction method and operational approach to this semiconductor subassembly.

The disclosure employs standard regulation, p-type and n-type quasiconductor, and it " spreads " layer or region (in any case structure), Such as transistor source, drain electrode or regions and source/drain, buoyancy aid, embedding layer, trap and semiconductor substrate, and diffusion zone it Between insulating regions (such as silicon oxide, regardless of whether exposed in shallow slot, or other arrangements), be all considered to be in half Conductive surface " below "-and figure are also consistent with the program, by diffusion zone as the bottom of figure.This regulation is the most fixed Justice " interconnection " layer of difference, such as transistor gate (no matter use which kind of material construction, metal, p-type or n-type polysilicon, or Other materials), the metallic conductor in one or more layers, tactile between the diffusion zone of semiconductor surface and a metal level Point, the contact between gated semiconductor and a metal level, via between the two metal layers, (include door in said modules Between insulating barrier and the diffusion zone of semiconductor surface) between insulator, be all considered to be in semiconductor surface " it On "-and drawing also consistent with such scheme, when providing schematic diagram, always on figure.There is an example merited attention Outward: in certain embodiments, entirety or a part for door may be under semiconductor surface.Another one exception is: part is absolutely Edge body may be partially exposed on or below surface.Also other are had to make an exception.Prior art is had the people of certain understanding, will be not difficult Understand this regulation, be so easy to the picture with regard to standard and illustration method is discussed, also allow for discussing in the text the knot of quasiconductor Structure, and be that the physics quasiconductor being concentrated use in may be disposed in any angle and orientation, without affecting it physically or electrically Learn characteristic.

At this in example of discussion, the most freely a surface contact, is positioned at semiconductor regions, below semiconductor surface, It is connected with the interconnection area on semiconductor surface (in the bounds of storage element).This and current single-transistor (1T) Elemental floating body (FBC) DRAM is different, and elemental floating body has two-one, contacts and is positioned at source region, one be positioned at transistor it Drain region.1TFBCDRAM unit two contacts public with adjacent unit due to current part so that each cell-average is only Having a contact, the certain embodiments in this invention may be designed in two adjacent unit and shares a contact so that flat The most each unit only has half contact.

The advantage of this invention is to eliminate one of semiconductor region field surface source/drain regions, thus without at table Face is attached thereto.Contrast, such as prior art MOSFET shown in Figure 90 B and the emulation of this invention shown in Figure 35 C cross section.? Under any Technology, the structure shown in Figure 35 C is all certainly less than the structure shown in Figure 90 B.Certain embodiments in this invention In, door is also removed, thus reduces the size of storage element further.Contrast, the simulation cross section knot as shown in Figure 77 C and 85C Structure and the MOSFET (Figure 90 B) of prior art production.New storage element is referred to as " semitransistor storage element ", as phase Same, the abbreviation of similar structures.The structure same or like with shown in Figure 35 C is referred to as " the semitransistor storage element of band door ". The structure same or like with shown in Figure 77 C and 85C is referred to as " the semitransistor storage element of band door ".Semiconductor surface it Under be arranged vertically diffusion zone, by all semitransistor storage elements share-especially the bit line region of semiconductor surface (can Couple with the bit line on semiconductor surface), floating body region (be used for storing most electric charge carrier, majority carrier it Quantity determines the logic state being stored in data in storage element), line region, a source (it is fully located at semiconductor surface once, And within storage element surface, it is possible to be connected with purgation source line with semiconductor surface, be usually located at paired storage element with Under, and be attached thereto), wherein bit line region, buoyancy aid, and line region, source constitutes a vertical bipolar junction transistor, can For operating, by using the design of buoyancy aid DRAM storage element to be considered to build up-be " semitransistor ".

The people that the technology is had gained some understanding, it is easy to understand the present invention by illustrating with purgation example and method, Following method and example are merely to illustrate the principle of this invention.For understanding thoroughly the people of the technology, by read the disclosure and Inspection drawing, it is readily understood that example herein be have a lot of other scheme and method it.Therefore, disclosed example is only For illustrating, this invention is only limited by patent right statement.

Drawing in this illustrates, especially illustrates the drawing of semiconductor structure, only clear for convenience of understanding and explanation Mesh it, be not drawn to scale.In illustrated semiconductor structure, there is a conduction type of two kinds of differences: p-type, many Number electric charge carrier is positively charged hole, it will usually move along quasiconductor valence band under electric field action；N-type, most electric charges Carrier is electronegative electronics, generally moves along conduction band under electric field action.Generally add impurities to intrinsic semiconductor (empty The quantity of cave and electronics is equal, and conductive capability is low: but more much higher than insulator, but still than doped region difference very Many, therefore become " partly " conductor), generate a kind of conduction type.

Foreign atom can accept a more electronics (becoming " acceptor "), is introduced in semiconductor lattice；" hole " It it is exactly the positively charged carrier of becoming that can accept an electronics.After introducing above-mentioned atom, conduction type just becomes p- Type, hole loses electronics becomes that " acceptor " is most electric charge carrier.It is similar to it, when foreign atom can lose many electricity Son (referred to as " alms giver "), after being introduced in semiconductor lattice, the electronics donated just becomes charge carriers.Above-mentioned former when introducing After son, conduction type just becomes n-type, and the electronics lost becomes " alms giver " and is most electric charge carrier.

In the prior art, the quantity of the foreign atom used may because the order of magnitude of ultimate density is different each the most not phase With, the order of magnitude of concentration belongs to design alternative.But, the essence of majority carrier rather than quantity determine material be p-type also Be n-type sometimes, in this industry, severe, medium and lightly doped p-type material can be referred to as p+, p and p-, accordingly it, will Severe, medium and lightly doped n-type material are referred to as n+, n and n-.But, unfortunate is, not to "+" and the implication of "-" Carrying out accurate definition, in order to avoid the statement of excessively complexity, in this invention, p-type and n-type are i.e. expressed as " p " " n ", inapplicable diacritic.The people having gained some understanding the technology will readily appreciate that, in various embodiments, and the journey of doping Degree will be turned over when design as design alternative.

Below the example of difference is illustrated.A lot of examples have identical feature, function, operator scheme etc..When When the drawing figure of difference uses similar Ref. No., mean that they have similar, identical structure, thus be easy to By the relation between specification configuration and example, thus obtain more preferable understanding-especially different structure and be there is similar, phase Congenerous.

Figure 35 A-35E gives the example of a semitransistor storage element FBCDRAM storage element.Figure 35 A is part The top view of storage arrays, including storage element 250 (dotted line), Figure 35 B give independent storage element 250. Figure 35 C and 35D gives the sectional view of storage element 250, cuts open along I-I ' and II-II '；Figure 35 E gives below conducting embedment trap and unit The method of substrate.

With reference to Figure 35 C and 35D, unit 250 includes a substrate 12, has the first conduction type, such as p-type.Substrate 12 leads to Often it is made up of silicon, but germanium, silicon-germanium, silicon-arsenic, CNT or other known semi-conducting materials can be comprised.At this In the certain embodiments of invention, substrate 12 can be the chip (bulkmaterial) of semiconductor crystal wafer.In other instances, substrate 12 can also be the trap with the first conduction type, or for having the trap of the second conduction type, or can also be partly to lead Chip in the chip of body wafer, has the second conduction type, such as n-type, (drawing the most in the drawings), design determines.For letter Changing explanation, substrate 12 is generally divided into semiconductor chip, as shown in Figure 35 C and 35D.

Embedding layer 22 has the second conduction type, such as n-type, is positioned on substrate 12.Embedding layer 22 can also be mixed by ion General labourer's skill processes on the material of substrate 12.It addition, embedding layer 22 can also be by obtaining by epitaxial growth at substrate 12 Arrive.

Buoyancy aid 24, has the first conduction type, such as p-type, by bit line region 16, insulating barrier 62 and two side insulation layer 26 and 28, and the embedding layer 22 of bottom surrounds.Buoyancy aid 24 can be a part for initial substrate 12, is positioned on embedding layer 22, as Fruit is doped with embedding layer 22.It addition, buoyancy aid 24 can also be obtained by epitaxial growth.According to embedding layer 22 and the structure of buoyancy aid 24 Method, in certain embodiments, buoyancy aid 24 may have identical doping, or the doping of difference with substrate 12, at the example of difference Middle according to design it needs to be determined that.

Insulating barrier 26 and 28 (such as shallow-trench isolation (STI)), it is possible to use silicon oxide manufacture, can also use other to insulate Material.When unit 250 is connected into array 280, unit 250 is separated by insulating barrier 26 and 28 with adjacent unit 250, thus Constitute the storage assembly as shown in Figure 38 A-38C.Adjacent cells buoyancy aid 24 and embedment region 22 are isolated (see figure by sterillization layer 26 35C), adjacent floating body region 24 is isolated by insulating barrier 28 simultaneously, but does not isolate embedding layer 22 so that embedding layer 22 can be (being i.e. held on) is extended (along direction shown in II-II ' in Figure 35 D) on one direction.By embedding layer 22 be connected adjacent Storage element together form a source line, is positioned at storage element less than 250, thus eliminates the regions and source/drain of contact, Or adjacent connection handle (it be musted in institute in the storage element of prior art).From Figure 35 A and 35B it will be seen that half Conductive surface, within storage element 250 border, embedding layer 22 is contactless to be attached thereto.

Bit line region 16 has the second conduction type, such as n-type, is positioned in floating body region 24, towards surface 14.Bit line 16 Being processed on the composition material of substrate 12 by a doping process, use is to be currently known and the doping process of typical case.Separately Outward, it is possible to use solid state diffusion process generates territory, bitline regions 16.

Between bit line region 15 and insulating barrier 26, there is a door 60, be positioned on floating body region 24.Door 60 is by absolutely Edge layer 62 insulate with floating body region 24.Insulating barrier 62 can use silicon oxide and/or other insulant, including height-K insulation material Material, includes but not limited to peroxidating tantalum, titanium oxide, zirconium oxide, hafnium oxide and or aluminium oxide.Door 60 can use polysilicon material Material or metal gate electrode, such as tungsten, tantalum, titanium and their nitride

Unit 250 also includes: wordline (WL) electrode 70, is connected with door 60, bit line (BL) electrode 74, with bit line region 16 phase Even, source line (SL) electrode 72, it is connected with embedding layer 22, and electrode of substrate 78, it is connected with substrate 12.

As shown in Figure 35 E, the contact between SL electrode 72 and embedding layer 22, can (have second to lead by region 20 Electricity type) generate；Then it is connected with embedment well area 22；Contact between electrode of substrate 78 and substrate regions 12 simultaneously, Can be generated by region 21 (there is the first conduction type), and be connected with substrate regions 12.

SL electrode 72 is connected with embedding layer 22, as reverse biased electrode, i.e. at the electricity of semiconductor transistor assembly reverse side Pole, generally at transistor gate reverse side, is connected with buoyancy aid or device wafer, corresponding to region 82 (Figure 90 A) or the crystalline substance of transistor 100 Region 94A (Figure 90 B) in body pipe 100A.In buoyancy aid DRAM cell, otherwise effect mutually may be produced with being conductively connected of buoyancy aid Really, because under this kind connects, buoyancy aid may quit work.P-n in certain embodiments, between buoyancy aid 24 and embedment trap 22 Knot, is connected with source line electrode 72, after applying a negative voltage on source line electrode 72, and forward bias.In certain embodiments, SL electrode is biased by forward potential, thus is maintained at the electric charge in buoyancy aid 24.In certain embodiments, the use class of source line electrode 72 It is similar to the purposes of buoyancy aid source line in existing buoyancy aid DRAM cell.In different instances, the effect of SL electrode 72 may be with the back side Bias electrode is similar, or can also be similar to source line, or can be used for entirely different purposes.In certain embodiments, It is likely to be used for 2 or more different operatings.In the present note, " source line electrode " and " back side bias electrode " all can be equivalent mutual Change.

The relatively structure of storage assembly 250, and as shown in Figure 35 C with transistor component 100,100A and 100B (such as figure 90A-90C), it can be seen that in this invention, the structure of storage assembly is less than MOSFET100,100A and 100B, the most only There is a region to have the second conduction type, be positioned at the surface of silicon substrate.Therefore, storage element 250 has an advantage, it is simply that Only comprise a region on surface, there is the second conduction type, (such as bit line region 16, relative to region 84 and 86, or region 84A and 86A), therefore require nothing more than storage element 250 and there is a contact (that is, set up between bit line region 16 and electrode 74 even Connect).

To this be skillful at it can be seen that in Figure 35 A-35E, the first and second conduction types can be in storage Memory cell 250 exchanges, design needs to determine, and p-type is appointed as the first conduction type, by the second conduction type Being appointed as n-type is the most only to illustrate conveniently, and non-limiting.Therefore, in storage element 50, the first and second conduction types P-type and n-type can be respectively, in other example, it is also possible to be respectively n-type and p-type.It addition, be familiar with this skill The people of art, it will be seen that the relative doping level of every kind of conduction type zones of different can also need to determine according to design, omits Falling higher or lower doping level, such as p+ or p0-, or n+ or n-there is no big harm.

Below with reference to 36A-36U, the method illustrating to manufacture storage element 250.Following 21 figure volumes are one group, are divided into three Individual relevant view, often first figure of group is top view, and often second figure of group is the vertical Section View of first top view, According to I-I ' line cutting, the often sectional horizontal view that the 3rd figure is first view in group, according to II-II ' line cutting.Cause This, Figure 36 A, 36D, 36G, 36J, 36M, 36P and 36S are respectively storage element vertical view in different phase and manufacturing process Figure；Figure 36 B, 36E, 36H, 36K, 36N, 36Q and 36T are respectively corresponding vertical Section View (I-I ')；And Figure 36 C, 36F, 36I, 36L, 36O, 36R and 36U are respectively corresponding sectional horizontal view (II-II ').In Figure 36 A-36U, class Sihe is identical Structure use and identical Ref. No. in Figure 35 A-35E, in order to drawing above to as directed.Herein, " vertical " table Show in a top view, to the lower section of paper on paper, and " level " represent, in a top view, from the left side of paper to The right of paper.In the Physical Examples of storage element 50, cutting is relative to the vertical cutting in the surface of semiconductor subassembly.

Referring now to Figure 36 A-36C, it can be seen that first technique.In the 130nm technique of example, film oxidation silicon layer The thickness of 102 be about 100A it, the superficial growth at substrate 12 obtains.It it is the most then the accumulation polysilicon that goes out about 200A thickness Layer 104.Then accumulation goes out the silicon nitride layer 106 of about 1200A thickness.The technique that can also use other processing procedures, such as 250nm, 180nm, 90nm, 65n etc..It is similar to it, the thickness of every layer, and the combination of protective layer 102,104,106 can be according to design needs Determine.

As shown in Figure 36 D-36F, it is possible to use photoetching process, process an opening, form groove 108.Then, oxidation Then silicon 102, polysilicon 104, silicon nitride layer 106 can also be able to be etched, Jing Guoyi with first use photoetching process molding Individual silicon etch process, obtains groove 108.

As shown in Figure 36 G-36I, it is possible to use photoetching process processes an opening shape, obtains groove 112, then leads to Overetch silicon oxide 102, polysilicon 104 and silicon nitride layer 106, and a silicon trench etch technique, process groove 112. Groove 112 can etch and obtain, and groove depth is bigger than 108.In the 130nm technique of example, the degree of depth of groove 108 can be 1000A, The degree of depth of groove 112 is about 2000A.The technique that can also use other processing procedures, such as 250nm, 180nm, 90nm, 65n etc..Class Like it, it is also possible to need to select other gash depth according to design.

As shown in Figure 36 J-36L, oxidation process can also be carried out subsequently, groove 108 and 112 grows silicon oxidation Film, becomes the insulating barrier 26 and 28 on groove.In the 130nm technique of example, silicon oxide can grow into about 4000A.Then Can chemically-mechanicapolish polish, the silicon oxide film polishing that will obtain so that silicon oxide layer is smooth relative to silicon face.Then Silicon dry ecthing can be carried out, the silicon oxide layer height of the insulating barrier 26 and 28 of residue is polishing to the silicon face about 300A that illustrates. In other instances, the surface of insulating barrier 2628 can also be identical with silicon face height.Subsequently, can be by silicon nitride layer 106 He Removing with polysilicon layer 104, then carry out wet etch process, (and part is on groove 108 and groove 112 to remove silicon oxide layer 102 The silicon oxide film of formation).The technique that can also use other processing procedures, such as 250nm, 180nm, 90nm, 65n etc..It is similar to it, Other insulating layer materials, height and thickness, it is possible to use instead processing sequence, by design it needs to be determined that.

Such as Figure 36 M-36O, ion doping technique can be used, obtain embedding layer 22, this layer have the second conduction type (as N-type conduction type).The energy of ion doping can be optimized so that buried layer region 22 is more shallow than bottom insulation layer 26, And it is deeper than the insulating barrier 28 of bottom.Thus, the embedding layer 22 between adjacent cells is separated by insulating barrier 26, simultaneously insulating barrier 28 Buried layer region 22 between adjacent cells will not be separated.The embedding layer 22 being thus can be on II-II ' cutting direction Keep continuously.Buoyancy aid 24 (having the first conduction type, such as p-type) finally is separated by embedding layer 22 with substrate 12.

As shown in Figure 36 P-36R, the insulating barrier 62 of silicon oxide or hafnium door can obtain at Surface machining of silicon wafer subsequently (such as, in the 130nm technique of example, being of about 100A)；Then carry out polysilicon or metallic door 60 accumulation (example it In 130nm technique, about 500A).Subsequently, lithography step can be carried out, layer 62 and 60 process figure, then carries out many Crystal silicon and the etching of silicon oxide layer.The technique that can also use other processing procedures, such as 250nm, 180nm, 90nm, 65n etc..Similar It, the thickness of other doors and door insulant can according to design it needs to be determined that.

Such as Figure 36 S-36U, can use ion doping technique, obtain bit line region 16, this layer has the second conduction type (such as n-type conduction type).May then pass through last part technology, process contact and metal level (is not drawn in Figure 36 A-36U Go out).Door 60 and insulating barrier 26 and 28 can serve as the mask layer of doping process so that the region with the second conduction type will not Formed outside bit line region 16.In Ben Tu and follow-up drawing, gate layer 60 and door insulating barrier 62 are represented as and insulating barrier 26 The most identical.In certain embodiments, gate layer 60 and door insulating barrier 62 may overlap with insulating barrier 16, thus prevent in bit line region The doping of 16 enters between gate layer 60, door insulating barrier 62 and adjacent insulating barrier 26.

The state of storage element 250 is represented by the electric charge in buoyancy aid 24.If unit 250 is stored in buoyancy aid 24 Hole be filled with positive charge, then storage element will have relatively low threshold voltage (the door electricity that usually mosfet transistor is opened Pressure, or hereinto in the case of, for inversion layer voltage of formation under door insulating barrier 62), if unit 250 is not by buoyancy aid 24 Be filled with hole, then threshold voltage can be higher.

In buoyancy aid 24, the positive charge of storage will reduce over time, due to the leakage current (p-n junction of diode p-n junction By buoyancy aid 24 and bit line region 16, and buoyancy aid 24 and embedding layer 22 are constituted), and the reason of charge recombination.This invention it It is unique in that and the holding that carries out that all storage elements in array are parallel can be operated.

As shown in Figure 37 A, keep operation can by apply on embedding layer 22 to SL electrode 72 one just reversely partially Pressure realizes, simultaneously by bit line region 16 to BL electrode 74 ground connection, by substrate 12 to electrode of substrate 78 ground connection.It is applied to embedding layer The reverse biased just in region (being connected with SL electrode) can remain connected to the state of storage element 250.Keep operation can with add It is downloaded to the door 60 voltage to word line electrode 70 independently operate.In certain embodiments, word line electrode can also ground connection.Single storing The n-p-n dipole elements 30 of unit 250 inside is (by embedment well area 22 (collector region), buoyancy aid 24 (base region), and bitline regions Territory 16 (emitter region) is formed).

If buoyancy aid 24 is positively charged, then state corresponds to logic 1, and bipolar transistor 30 is by bit line region 16, buoyancy aid 24 are formed with embedment well area 22, will open due to impact ionization, the list of references that sees above " Lin ".Wherein, at buoyancy aid 24 With the p-n economize on electricity pressure of the reverse bias between embedment well area 22 will produce a small area analysis, flow through knot.Portion of electrical current will be with warm The form of carrier, by electric field acceleration, flows through crystal tube coupling.These hot carriers and the atomic collision in semiconductor lattice, will Hole-electron pair is produced near joint.Electronics will be pushed in buried layer region 22 by electric field, and hole will be pushed by electric field simultaneously In floating body region 24.

The hole current (colleague becomes base current) being flowed into floating body region 24 will keep the data of logic 1 state.Protect The efficiency holding operation can be improved by the design of dipole elements, will imbed well area 22, floating body region 24, bit line region The dipole elements of 16 one low gain of composition, wherein bipolar gain is defined as the collector current of-SL electrode 72 outflow than upstream Enter the base current of floating body region 24.

Figure 37 B is the energy band diagram of intrinsic n-p-n dipole elements 30, floating body region 24 positively charged, and at embedment well area 22 when applying a bias just.What dotted line represented is the Fermi energy level of the n-p-n transistor 30 of zones of different.Fermi energy Level is positioned at bottom the energy band of the valence band top (bottom band gap) of solid line 17 expressions and solid line 19 expression in the band gap at (band gap top). At the positive charge of floating body region, reduction electronics is flowed into the activation evergy of base region.It is once injected in floating body region 24, electricity Son will be pushed into embedment well area 22 (being connected with SL electrode 72), owing to forward bias acts on caused by embedment well area 22. The result of forward bias is exactly: by impact ionization, and electronics is accelerated, and produce extra hot carrier (hot hole and Thermoelectron to).The thermoelectron produced is flowed in SL electrode 72, and the hot hole simultaneously produced is flowed into floating body region therewith In 24.This process stores electric charge in floating body region 24, and will remain stored in the electric charge in floating body region 24, thus keeps N-p-n double-clicks transistor 30 and opens, as long as embedment well area 22 applies positive bias on SL electrode 72 always.

If buoyancy aid 24 is electric neutrality (voltage of buoyancy aid 24 is equal to the voltage in the bit line region 16 of ground connection), then corresponding to patrolling 0 state of collecting, does not has electric current to flow through from n-p-n transistor npn npn 30.Dipole elements 30 will remain turned-off, and can't collide electricity From.Therefore, the storage element being in logical zero state will keep logical zero state.

Figure 37 C is the energy band diagram of intrinsic n-p-n dipole elements 30, floating body region 24 positively charged, and at embedment well area During 22 one neutral bias of applying.In this case, it is achieved the energy level of the energy gap that 17A and 19A surrounds will be double because of the n-p-n of difference Pole assembly 30 region and different.Owing to current potential and the bit line region 16 of floating body region 24 are equal, Fermi energy level is constant, so in place Activation evergy is there is between line region 16 and floating body region 24.Solid line 23 represents, for reference, in bit line region 16 and floating body region Activation evergy between 24.Activation evergy prevents electronics to be flowed into buoyancy aid 24 from bit line region 16 (being connected with BL electrode 74) In.Therefore n-p-n dipole elements 30 will remain turned-off.

The operation of ionization by collision write logic 1 (list of references above " Lin " and as described in) with keep operating different, difference Place is that door 60 will not bias because of the voltage higher than normal holding operation when keeping operation.When writing logic 1 and operating, From door 60 to the Capacitance Coupled of floating body region 24, n-p-n dipole elements 30 will be forced to open, storage is what the most in the cells Plant data.Comparatively, promote without door, keep operation only to be produced by ionization by collision and staying, now storage element Save as logic 1；And when storage element storage be logical zero time, then will not produce carrier by ionization by collision.

In the example shown in Figure 37 A-37C, dipole elements 30 has a n-p-n transistor npn npn.Prior art is had The people understood, it is impossible to find out, by turning the first and second conduction types, i.e. turn be applied on storage element 50 relatively Value, can produce a dipole elements 30 containing p-n-p transistor.Therefore, select n-p-n transistor the most for convenience of explanation, Be easy to explain Figure 37 A-37C, and non-limiting mesh it.

Figure 38 A is: example array 280, containing storage element 250 (four example storage elements 250 arranged in rows and columns It is denoted as 250a, 250b, 250c and 250d).A lot, but in not all example array 280, the storage element of representative 250a will represent " selecting it " storage element 250, and now illustrated operation is for selected storage element 250.At this In class figure, represent the storage element 250 that storage element 250b represents unselected, have identical with selected storage element 250a OK, storage element 250c then represents unselected storage element 250, with selected storage element 250a have identical it Row, storage element 250d then represents, neither has identical trip with the storage element 250a chosen and does not the most have identical row.

Figure 38 A is, wordline 70a-70n, source line 72a-72n, bit line 74a-74p, and electrode of substrate 78.Each wordline 70a-70n is all connected with a storage element 250, and is connected with the door 60 of the storage element 250 of this row.It is similar to it, each Source line 72a-70n is all connected with a storage element 50, and is connected with the embedment well area 22 of the storage element 50 of this row.Often Individual bit line 74a-70n is all connected with a storage element 50, and is connected with the bit line region 16 of the storage element 50 of these row.As Holding operation shown in Figure 37 A-37C, does not has single storage element selected.And storage element in column is by by source line 72a-72n is selected, and can choose single file, multirow, or whole array 280.

Substrate 12 is respectively positioned on array less than 280.The people that have gained some understanding this technology are it can be appreciated that according to design need Want, can be at the one or more electrode of substrate 78 of one or more local appearance.The people that this technology is had gained some understanding, the most not Indigestibility, the example array 280 shown in Figure 38 A is expressed as a continuous array, but can also use other various groups Knitting and arrangement, such as wordline can be grouped or buffer, and bit line can be grouped or buffer, and source line can be carried out point Group or buffering, array 280 can be divided into two or more subnumber groups, control circuit such as word encoder, row encoder, packet group Part, induction amplifier, write amplifier can also be arranged in around example array 280, or be inserted into the submatrix of array 280 In.Therefore, function in this example, design etc., it is intended for explanation, limits absolutely not.

Figure 38 B is: aforementioned array 280, and multiplexer 40a-40n and voltage oscillogram 42a-42n.By SL electricity Pole 72 applies a positive voltage period pulse rather than constant positive bias on the reverse biased electrode of storage element 250, can To reduce the power consumption of storage element 250.Figure 38 B further illustrates: multiplexer 40a-40n, each and 72a-72n source One of line is connected, and multiplexer determines the bias voltage being applied on SL electrode 72a-72n, by the operator scheme of difference Determine.The potential pulse being applied on SL electrode be controlled it, such as, by as the logical signal pulse of waveform 42a-42n, choosing Select the input of multiplexer 40a-40n, thus select, such as, ground connection (0.0 volt) or supply voltage V_CC.A lot of other technology are also Can be used to apply potential pulse, such as at electricity shown in applying oscillogram 42a-42n of difference to SL electrode 72a-72n Pressure, or apply, or the selection input of multiplexer 42a-42n is linked together, and to all multiplexers simultaneously 42a-42n is simultaneously entered an identical impulse waveform (drawing the most in the drawings).It is familiar with the people of this technology to be easy to oneself and think Scheme to other.Therefore, this example is the most for instructions, is defined the right of this invention absolutely not.

In Figure 38 C, it is proposed that another method, being used for being applied to the potential pulse of SL electrode 72a-72n, electrode belongs to The storage element 250 of array 280.Positive input signal enters multiplexer 40a-40n, can pass through voltage generating circuit 44a- 44n produces, and voltage generating circuit is connected with each input in multiplexer 40a-40n.Alternatively, it is also possible to use single Voltage generating circuit, is connected with each multiplexer 40a-40n, reduces required circuit sum, is used for refreshing in array 280 it Storage element 250.Other examples are also possible, such as, apply waveform 42a-42n when difference, or apply simultaneously, Or the selection input of multiplexer 42a-42n is linked together, and applies an impulse waveform to all multitasks simultaneously Device 42a-42n (not shown).

In Figure 38 D, give a reference generating circuit, can be used for the reference generating circuit 44a-44n shown in Figure 38 C. Reference generator includes: reference cell 53, including the band door semitransistor storage element 250 of an improvement, and has first The region 25 of conduction type (p-type).P-type 25 region allows the current potential in direct inducing floating body region 24.Region 25 individually draws, Having identical conduction type with floating body region 24, reason is: this region can carry out the doping of difference, thus contributes to even Connect.Reference cell 53 is it can also be provided that logic 1 state, and now the current potential of floating body region 24 is just, for example,+0.5V.Sensing Current potential, by p-type region, subsequently with reference value V_RFF, (such as+0.5V) is compared, is completed by operational amplifier 27.As Really buoyancy aid 24 by current potential less than reference value, then be applied to reverse biased electrode 72 (embedment region 22 phase with reference cell 53 Even, it is possible to be connected with the embedment region 22 of the semitransistor storage element 250 of band door) upper voltage is by operational amplifier 27 liters Height, until the current potential of buoyancy aid 24 reaches required reference potential.If the current potential in buoyancy aid 24 region is higher than reference value, then apply Voltage on reverse biased electrode 72 can be reduced by operational amplifier 27, until the current potential of floating body region 24 reach required it Reference voltage.Reference voltage V_REFCan be produced by the mode of a lot of differences, such as, use band-gap reference, series resistance, digital-to-analogue Transducer etc..It is similar to it, it is possible to use dissimilar voltage generator.

As shown in figure 39, keep/prepare operation to be likely to produce a bigger bin window, can store up by increasing The quantity of electric charge existed in buoyancy aid 24 realizes.Without keeping/prepare operation, it is possible to be stored in the maximum potential in buoyancy aid 24 It is limited to flat-band voltage V_FB, because from buoyancy aid 24 be flowed into bit line region 16 junction leakage will with floating body potential for index increase Greatly, more than V_FB.But, by applying a positive voltage on SL electrode 72, the action of dipole elements will produce one and flow into floating The hole current of body 24, compensates the junction leakage between buoyancy aid 24 and bit line region 16.Therefore, be stored in buoyancy aid 24 Large charge V_MC, can increase by applying positive bias on SL electrode 72, see Figure 39.Increase and be stored in the maximum in buoyancy aid 24 It is bigger that electric charge makes to store window.

Keep/prepare operation to may be used for the multi-position action on storage element 250.In order to increase storage density, and do not increase Add the area that storage element is shared, it will usually use many layer operations.By whole storage window is divided into difference (more than 2) it Layer realizes.In one example, employ 4 layers of binary data representing 2 positions, but its other party can also be used Case, such as, use 8 layers of binary data representing 3 positions.In a buoyancy aid stores, the storing state of difference is by buoyancy aid 24 In difference voltage represent, such as in Tack and Oknoin-2 cited above.But, due to 0 electric charge in buoyancy aid 24 State is steady statue, and buoyancy aid 24 can the most gradually lose electric charge, until steady statue.In many layer operations, no Same electric charge represents the state of difference, and the kind of electric charge will be less than the kind in monolayer operation.Therefore, Multi-layer Store unit is more It is easily subject to the impact of charge loss.

Figure 40 represents, the net current of different buoyancy aid 24 current potentials, the current potential of buoyancy aid 24 is SL electrode 72 and BL and WL and base The function of plate electrode 74,70 and 78 ground connection.When 0 voltage is applied on SL electrode 72, does not have bipolar current and be flowed into buoyancy aid In 24, wherein the electric charge of storage can reduce in time.When applying a positive electricity and being pressed onto on SL electrode 72, hole current will Can be flowed in buoyancy aid 24, compensate the junction leakage being flowed into bit line region 16.Junction leakage is by buoyancy aid 24 and bit line region 16 Between potential difference determine, and the bipolar current being flowed into buoyancy aid 24 is together decided on by the current potential of SL electrode 72 and buoyancy aid 24.As Shown in Figure 40, at certain SL electrode 72 current potential V_HOLDUnder, the floating body potential of difference；It is flowed into electric current and the buoyancy aid 24 of buoyancy aid 24 And the junction leakage balance between bit line region 16.What buoyancy aid 24 current potential of difference represented is the electric charge of difference, thus represents storage The different conditions of memory cell 50.The storing state of difference can maintain by using holding/preparation operation described herein as.

In an example, give storage element 250 and keeping operation purgation bias condition: 0 voltage is applied to BL electricity On pole 74, positive voltage, such as+1.2 volts, it is applied on SL electrode 72,0 voltage or negative voltage are applied on WL electrode 70, and 0 voltage is executed It is added on electrode of substrate 78.In another one example, WL electrode 70 can apply negative voltage.In other instances, may be used To apply the voltage of difference on storage element 250, as design alternative, the most only voltage is illustrated, be not belonging to limit Mesh it.

In storage element 250 and array 280, the read operation of storage element can illustrate in conjunction with Figure 41, Figure 42 A-42H. Any inductive scheme feasible to storage element 250 can be used.Citing: Ohsawa-1 and Ohsawa-2 hereinbefore quoted In inductive scheme.

It is stored in the quantity of electric charge in buoyancy aid 24 to be sensed by the cell current of detection storage element 250.If Storage element 250 is in logic 1 state, i.e. stores hole in buoyancy aid 24, then storage element will have higher cell current (such as, be flowed into the electric current of SL electrode 72 from BL electrode 74), this electric current will be in logical zero state (i.e., than storage element 250 When buoyancy aid 24 does not stores hole) want big.Sensor circuit is generally connected with BL electrode 74, may be used to determine in storage element it Data mode.

Read operation can be carried out on storage element 250: on BL electrode 74, just applying one by following bias condition Voltage, applies a bigger positive voltage on selected WL electrode 70, applies 0 voltage on selected SL electrode 72, Electrode of substrate 78 applies 0 voltage.Thus dipole elements 30 is become a reverse n-p-n transistor, class It is similar to dipole elements 30 as keeping mode of operation (Figure 37 A-37C).On WL electrode 70 apply positive voltage, by buoyancy aid 24 it Voltage is raised by Capacitance Coupled, door 60 and floating body region 24 electric capacity (by door insulating barrier 62).Which increases bipolar group The electric current of part 30 so that the dipole elements 30 electric current when opening is significantly greater than electric current when closing, thus is easier to sensing storage There are the data in storage element 250.The maximum bias voltage being applied on WL electrode 70 may because of different instances and technique and Different.Virtual voltage in various embodiments can by design it needs to be determined that.

Figure 41 is the storage element 250 of array 280, is the most read an example.As it has been described above, read One of peek group 280 storage element 250 is more increasingly complex, because unit passes through wordline than reading a unit individually 70a-70n and source line 72a-72n is connected by row, and is connected by row by bit line 74a-74p.In an example, will apply greatly About 0.0 volt is applied on the SL electrode 72a that selectes, is applied to by about+0.4 volt in bit line electrode 74a selected, will about+ 1.2 volts are applied on selected zigzag electrode 70a, apply about 0.0 volt to electrode of substrate 78.The promising chosen bit line of institute Electrode 74b (not shown)-74p, all applies 0.0 volt；All unselected zigzag electrode 70b (not shown)-70n, all apply 0.0 volt；All unselected SL electrode 72b (not shown)s all apply+1.2 volts.Figure 41 gives, and chosen representative stores The bias condition of unit 250a, and in storage arrays 280 three unselected represent storage element 250b, 250c, The bias condition of 250d, each bias condition all differs.The people having gained some understanding this technology are it can be appreciated that this is sent out Bias combination employed in bright all can be needed to select by design.People that this technology is had gained some understanding it is to be appreciated that First and second conduction types can be exchanged, and then exchanges the relativeness of bias voltage in itself and example.

What Figure 42 A represented is the bias condition of storage element 250a (being selected it)；Figure 42 B is bipolar group of intrinsic n-p-n The part 30 equivalent circuit diagram when reading bias condition.

When read operation, three kinds of situations of unselected storage element 250 are as shown in Figure 42 C, 42E and 42G；Additionally scheme 42D, 42F, 42H are respectively the equivalent circuit diagram of above-mentioned situation.In selected unit, the bias condition (tool of storage element 250 Have identical trip, such as storage element 250b) and there is the storage element (such as storage element 50c) of same column, respectively such as Figure 42 C- Shown in 42D and Figure 42 E-42F；And it is not total to the bias condition such as figure of the storage element 250 (such as storage element 250d) of row or column Shown in 42G-42H.

As shown in Figure 42 C and 42D, storage element 250d Yu 250a (chosen storage element) has identical trip, SL Electrode 72 now ground connection so that said units is not the most in hold mode.Further, since read operation completes comparatively fast (nanosecond), with In buoyancy aid 24, the life-span (Millisecond) of hole charge is compared, and be will not cause many large disturbances to the electric charge of storage in buoyancy aid.

As shown in Figure 42 E and 42F, storage element 250c has identical row, BL electrode with selected storage element 250a Positive voltage is applied on 74.Due to SL electrode 72n and BL electrode 74a (that is, the emitter and collector of n-p-n dipole elements 30) it Between potential difference less, base current will not be produced and flow in buoyancy aid 24.Further, since read operation completes comparatively fast (nanosecond), Compared with the life-span (Millisecond) of electric charge in buoyancy aid 24, be will not cause many large disturbances to the electric charge of storage in buoyancy aid.

As shown in Figure 42 G and 42H, storage element 250d and storage element 250a neither has identical trip and does not the most have phase Same row, SL electrode 72n will keep positively charged, and BL electrode 74p will keep ground connection.It will be seen that these unit are in holding Pattern, storage element be in logic 1 state it, the electric charge in buoyancy aid 24 can be kept, because intrinsic n-p-n dipole elements 30 can be produced Raw hole current, with the electric charge in supplementary buoyancy aid 24；The storage element being simultaneously in logical zero state will keep neutral state.

In storage element 250 and array 280, the read operation of storage element can illustrate in conjunction with Figure 41-42H.To this The people that technology is had gained some understanding, it is contemplated that drawing is not necessarily made to scale and draws, the voltage of difference is the most for instructions, can be because of example And different, example discussed herein is the most for instructions, according to the principle of this invention, it is possibility to have other a lot of examples.Such as, two Planting conduction type can exchange, the relative voltage of unlike signal can be exchanged, and storage arrays 280 can be odd number group, or is divided into Subnumber group, corresponding control circuit can also use the mode of difference to realize, and relative voltage or the absolute voltage of difference is applied On storage element 250 or array 280, etc..Therefore, function in this example, bias grade etc., it is intended for explanation, limits absolutely not Fixed.

Engaging Figure 43 A and 43B below, first kind write 0 operation to carrying out on storage element 250 illustrates.? In Figure 43 A, negative voltage is applied on reverse deflecting electrode (that is, SL electrode 72), 0 voltage is applied on WL electrode 70, by 0 Voltage is applied on BL electrode 74 and electrode of substrate 78.With this understanding, p-n junction (buoyancy aid 24 of selected unit 250 and embedment trap Between 22) forward bias, shifts the hole in buoyancy aid 24.In a non-limiting example, the voltage of about 0.5 volt is executed Being added on electrode 72, the voltage of about 0.0 volt is applied on electrode 70, and the voltage of about 0.0 volt is applied to bit line On electrode 74 and electrode of substrate 78.Above-mentioned electric pressure is only for reference, can be different because of different instances, by design it needs to be determined that.Cause This, function in this example, bias grade etc., it is intended for explanation, limits absolutely not.

In Figure 43 B, giving the example of another one storage element 250, wherein substrate 12 is substituted by region 12A, and 12A has Having the first conduction type (for p-type in figure), be one of substrate 29 trap, substrate 29 has the second conduction type (i.e. icon N-type).Layout so just overcomes the negative effect in Figure 43 A, will imbed on trap electrode 72 imbed well area 22 it Voltage is reduced to about 0.5V so that p-n junction (between embedment trap 22 and buoyancy aid 4) forward bias, also makes to imbed trap 22 and base P-n junction forward bias between plate 12, produces the substrate current that need not.In the example shown in Figure 43 B, the current potential of trap 12A Can reduce, realize with the identical voltage of embedding layer electrode 72 by applying on trap electrode 76, thus prevent these regions it Between p-n diode forward biasing.In Figure 43 B, substrate 29 is biased to 0.0V approximately through electrode of substrate 31.Above-mentioned voltage etc. Level only for reference, can be different because of different instances, by design it needs to be determined that.Therefore, function in this example, bias grade etc., only For explanation, limit absolutely not.

Figure 44 is, the bias condition of selected and unselected storage element 250, writes logical zero in storage arrays 280 Operation (Figure 43 A) period.For selected storage element 250a and 250b, being applied to the back bias voltage on SL electrode 72a will be floating Big potential difference is produced between body 24 and embedment well area 22.Because embedment trap 22 is shared by multiple storage elements 250, logical zero To be written in all storage elements 250, share a SL electrode 72a including storage element 250a and 250b simultaneously.

Figure 45 A-45B is bias condition and the equivalent circuit of n-p-n dipole elements 30 in unselected storage element 250 Figure, for storage element 250c, 250d (array 280) during first kind logical zero write operation.Below will be to storage element 250d discusses, and represents the unselected storage element of every other applicable principle of identity with 250d.Owing to logical zero writes Operation only relates to want that the SL electrode 72a selected applies a negative voltage, storage element 250 and unselected SL electrode 72b ( Figure 44 is not drawn into)-72n be connected, be in hold mode, this state by SL electrode 72b-72n apply a positive bias Realize.From 45A-45B it can be seen that unselected storage element will be in holding operation, BL electrode applies about 0.0 Volt, WL electrode applies 0 volt, for chosen SL electrode forward bias.

Such as Figure 46, Equations of The Second Kind write logical zero operation can also realize by applying a negative voltage on BL electrode 74, with SL electrode 72 is different.In figures 4-6 can, selected storage element 250 includes 250a and 250c, and all sharing selectes bit line 74a Storage element 250.SL electrode 72 can apply 0 voltage, at WL electrode 70 with forward bias on electrode of substrate 78 simultaneously One 0 voltage of upper applying.Under these conditions, all storage elements sharing a BL electrode 74 will be written into logical zero state.

The write logical zero operation of above-mentioned first and second types, has one disadvantage in that, the storage of the most all shared SL electrodes 72 Unit 250 (first kind-row write enters logical zero), or the storage element 250 of shared BL electrode 74 (write of Equations of The Second Kind row-column is patrolled Collect 0), will be written simultaneously, it is impossible to carry out single storage element 250 writing logical zero operation.For the storage element in difference Write the binary data of appointment in 250, can first write logical zero on whole storage elements, then patrol must be written into On the position of volume 1, write carries out one or more write logic 1 and operates.

Write 0 operation allowing unit write on storage element 250 of the 3rd type, it is simply that apply on WL electrode 70 One positive voltage, applies a negative voltage on BL electrode 74, applies 0/ negative voltage, at electrode of substrate on SL electrode 72 One 0 or positive voltage is applied on 78.In the case of hereinto, owing to being applied with a positive voltage on WL electrode 70, buoyancy aid 24 it Current potential will be raised by Capacitance Coupled.Make: the current potential of buoyancy aid 24 raises, and negative voltage is applied on BL electrode 74,24 and bit line P-n junction forward bias between region 16, the hole on buoyancy aid 24 is fallen in transfer.

Thus decrease in storage arrays 280 and cause write logical zero interference, the electricity applied to other storage elements 250 Position can optimize as follows: if it is assumed that the current potential with the buoyancy aid 24 of logic 1 state is V_FB1, then can be by setting The voltage being applied on WL electrode 70, to improve the current potential of buoyancy aid 24, can improve V_FB1/ 2, and-V_FB1/ 2 are just applied to BL electricity The voltage of pole 74.Alternatively, it is also possible to carry out ground connection on the BL electrode 74 of unselected storage element 250, or apply one Individual less positive voltage, the storage element operated is not total to BL electrode 74 with selected storage element 250；Simultaneously can not by A negative voltage, the storage element operated and selected storage element is applied on the WL electrode 70 of selected storage element 250 250 are not total to WL electrode 70.

As shown in figure 47, selected in array 280 storage element 250a applies following bias condition, individually to storage Unit 250a carries out the write logical zero operation of independence.SL electrode 72 applies about 0.0 volt, BL electrode 74a applies big About 0.2 volt, word line electrode 70a applies about+0.5 volt, electrode of substrate 78 applies about 0.0 volt.For array 280 Remainder, apply+1.2 volts, at unselected BL electrode unselected SL electrode 72 (including SL electrode 72n) is upper About 0.0 volt (or less positive voltage) of upper applying 74 (including BL electrode 74p), (includes at unselected WL electrode 70 WL electrode 70n) upper applying about 0.0 volt.The people that have gained some understanding this technology are it can be appreciated that voltage etc. as shown in figure 47 Level, the most for instructions, in the example of difference, can select according to design requirement.

As Figure 47 gives, the bias condition of selected storage element 250a, such that it is able to carry out unit writing logical zero behaviour Make, as shown in Figure 48 A and 48B.As described above, the electromotive force between buoyancy aid 24 and bit line region 16 (being connected with BL electrode 74a) Difference can increase, and due to Capacitance Coupled and from ground connection, WL electrode 70a is brought up to+0.5V cause, causes forward bias current to compare base Pole hole current is (by n-p-n dipole elements 30 (embedment well area 22-and SL electrode 72a, buoyancy aid 24 and bit line region 16 are connected) Produce).Result is exactly that hole is shifted from buoyancy aid 24.

In array 280, unselected storage element, 250 under the bias condition shown in Figure 47, patrols in unit write During collecting 0 operation, as shown in Figure 48 C-48H.With the bias feelings that selected storage element 250a has the storage element gone together mutually Condition, (such as storage element 250b) is as shown in Figure 48 C and 48D；With the storage element that selected storage element 250a has same column Bias condition, (such as storage element 250c), as shown in Figure 48 E and 48F；Neither have identical with selected storage element 250a Row does not the most have the bias condition (such as storage element 250d) of the storage element of same column, as shown in Figure 48 G and 48H.

As shown in Figure 48 C and 48D, in storage element 250b, the current potential of buoyancy aid 24 (has with selected storage element 250a Colleague mutually), will be because of the Capacitance Coupled with WL electrode 70, and WL electrode 70 raises V_FBAnd raise.For having logical zero state Storage element, the rising of buoyancy aid 24 current potential will not the most at last p-n diode forward biasing (diode is made up of buoyancy aid 24), and And knot 16 will remove the hole in buoyancy aid 24.Therefore, the current potential of buoyancy aid 24 will be returned to initial logical zero equilibrium potential." for place In the storage element of logic 1 state, the current potential of buoyancy aid 24 will raise V immediately_FB, cause hole to be shifted from buoyancy aid 24.Removing After positive bias on WL electrode 70, the current potential of buoyancy aid 24 will decline V_FB.If the initial potential of buoyancy aid 24 (logic state 1) is V_FB1, then, after the operation of write logical zero, the current potential of buoyancy aid 24 will become V_FB1-V_FB.Accordingly it is desirable to WL current potential is optimized, will The decline of buoyancy aid voltage when storage element 50 is in logic 1 state is not too large, now applies (to go subsequently on WL electrode 70 Remove) positive voltage.Such as, owing to coupling with WL, the maximum potential of buoyancy aid raises not over V_FB1/2.In certain embodiments, not Chosen BL electrode 74p one less positive voltage of upper applying be have some superiority it.This means that dipole elements 30 is only capable of Otherwise (such as, the only p-n junction between buoyancy aid 24 and embedment trap 22 is opened, and thus be enough to shift to remove hole in operation mutually Hole in buoyancy aid 24) so that the hole being transferred in logic state 1 purgation floating body region 24 is minimum.

As shown in Figure 48 E and 48F, storage element 250c has identical row with selected storage element 250a, at BL electricity A negative voltage is applied so that the current potential between buoyancy aid 24 and bit line region 16 (being connected with BL electrode 74a) rises on the 74a of pole. So, the p-n diode between buoyancy aid 24 and bit line region 16 will forward bias.Logic state 0 purgation is stored Unit, the current potential raising buoyancy aid 24 can't change initial logical zero state, because during hole is not stored in buoyancy aid 24. For the storage element of logic 1 state, net effect is exactly that the current potential of buoyancy aid 24 will decline after write 0 operation.Thus, need Be optimized by BL current potential, the decline of buoyancy aid voltage when storage element 250 is in logic 1 state is not too large, now BL electrode 74a applies positive voltage.Such as, applying-V on BL electrode 74a_FB1/2。

As shown in Figure 48 G and 48H, storage element 250d and chosen storage element 250a do not have identical trip or Row, these unit are still in holding pattern, now apply a positive voltage on SL electrode 72n, apply on BL electrode 74p One 0 voltage, applies 0/ negative voltage on WL electrode 70n, applies 0 voltage on electrode of substrate 78.

More than it is the method entering logical zero operation in the enterprising row write of storage element 250 of difference in 3.Can also there be other Example and assembly combination, such as, the first and second conduction types are turned, with the time point commutation relation to bias.In example Array 280 in, (can also have the scheme of a lot of other difference) just can apply difference on the array row electrode of difference Bias, uses multiple array, and on multiple selected positions, (one or more array) carries out write " 0 " operation of multiple unit, By using decoding circuit to realize, intersect position such that it is able to convenient write logical zero on a data character, subsequently Then can write logic 1 on selected position, etc..The people that technique is had gained some understanding, be understood that made herein it Explanation.Therefore, function in this example, bias grade etc., it is intended for explanation, limits absolutely not.

Logical zero can also be entered by ionization by collision described above in the enterprising row write of storage element 250 to operate, such as, root According to quoting document " Lin ", or by band, band can also be worn effect (door induction leakage current or GIDL) then and realize, see and quote Document " Yoshida ".The example using write logic 1 operation of GIDL method is shown in Figure 49 and 50A-50H, uses ionization by collision write The example of logic 1 operation is shown in Figure 51 and 52A-52H and related description.

In Figure 49, give the bias condition of array 280, including the storage element 250a selected, use band to band Wear write logic 1 when operating then.It is applied to the back bias voltage of WL electrode 70a and is applied to the positive bias of BL electrode 74a, can be selected Produce hole on the buoyancy aid 24 of storage element 250a to inject.SL electrode 72a and electrode of substrate 78 all connect when writing logic 1 and operating Ground.

The ground of floating body region 24 at negative voltage and the lower section storage element 250a of WL electrode 70 applying.With BL electricity Positive voltage on pole 74 together creates a highfield, between bit line region 16 and floating body region 24, in selected storage Near the door 60 of memory cell 250a (being it " door induction " part of GIDL).Thus make door and drain joint overlapping area near it Can violent being bent upwards of band so that electronics is worn then to conduction band from valence band, leaves hole in valence band.Through can the electronics of band Become drain leakage (being the drain leakage part of GIDL), during hole is injected into floating body region 24 simultaneously, and And created logic 1 state by hole charge.This process is the most common, has accompanying drawing explanation in Yoshida (especially Fig. 2, Fig. 6 of page 3, and Fig. 9 of page four).

As shown in Figure 50 A-50B, following bias condition can be applied on storage element 250a.On SL electrode 72a Apply the current potential of about 0.0 volt, BL electrode 74a applies+1.2 volts, WL electrode 70a applies-1.2 volts, at base About 0.0 volt is applied on plate electrode 78.

In other parts of array 280, can apply unselected storage element 250 to bias as follows (including Storage element 250b, 250c, 250d): on SL electrode 72n, apply about+1.2 volts, BL electrode 74p applies about 0.0 Volt, applies about 0.0 volt on WL electrode 70n, applies about 0.0 volt on electrode of substrate 78.Figure 49 gives storage arrays Selected storage element and the bias condition of unselected storage element in 280.But, above-mentioned electric pressure can because of example not With, it is merely to illustrate, and non-limiting.

Unselected storage element 50 is when writing 1 operation, as shown in Figure 50 C-50H.The storage with colleague mutually is single The bias condition (such as storage element 250b) of unit, as shown in Figure 50 C and 50D.With selected storage element 250a, there is same column The bias condition (such as storage element 250c) of storage element, as shown in Figure 50 E and 50F.With selected storage element 250a neither Having goes together mutually does not has the storage element 250 (such as 250d) of same column, and its bias condition is as shown in Figure 50 G-50H.

As shown in Figure 50 C and 50D, storage element 250b, have with selected storage element 250a and go together mutually, have electrode 72a and 74p ground connection, applies about-1.2 volts on WL electrode 70a simultaneously.Due to SL electrode 70a ground connection, storage element 250b is also Being not in holding pattern, because the voltage between emitter and collector does not exists, n-p-n dipole elements 30 is closed Close.Further, since write logic 1 has operated comparatively fast (nanosecond), compared with the life-span (Millisecond) of electric charge in buoyancy aid 24, it is The electric charge of storage in buoyancy aid will not be caused many large disturbances.

As shown in Figure 50 E and 50F, storage element 250c has identical row, BL electrode with selected storage element 250a Positive voltage is applied on 74n.Due to SL electrode 72n and BL electrode 74a (that is, the emitter and collector of n-p-n dipole elements 30) Between potential difference be 0, base current will not be produced and flow in buoyancy aid 24.Further, since write operation completes comparatively fast (nanosecond), Compared with the life-span (Millisecond) of electric charge in buoyancy aid 24, be will not cause many large disturbances to the electric charge of storage in buoyancy aid.

As shown in Figure 50 G and 50H, storage element 250d and storage element 250a neither has identical trip and does not the most have phase Same row, SL electrode 72n will keep positively charged, and door 70n and BL electrode 74p will keep ground connection.It will be seen that said units will It is in holding pattern.The storage element being in logic state 1 will keep the electric charge in buoyancy aid 24, because intrinsic bipolar assembly 30 will Producing hole current, the electric charge in the reddest buoyancy aid 24, the unit being simultaneously in logical zero state will keep neutral state.

As shown in figure 51, write logic 1 operates the method that can use ionization by collision.Now, door 60 and bit line 16 (belong to The storage element 250 that will be written into) all biased under positive voltage effect.It is similar to keep operation (Figure 37 A-38D), it is possible to To use ionization by collision to provide hole current for buoyancy aid 24.But, in keeping operation, n-p-n dipole elements 30 keeps closing Close, storage element 250 now stores logical zero, and impact ionization current only flows into the storage element having logic 1, dimension Hold electric charge in the buoyancy aid 24 of logic 1 storage element so that it is keep complete logical one voltage level.Otherwise it is mutually: when using collision Ionization write logic 1 is when operating, and the voltage of door is just rather than 0.The voltage rising wealthy family 60 is operation just, also will raise buoyancy aid The current potential of 24, because the capacitance coupling effect of door insulating barrier 62, so that n-p-n bipolar transistor 30 is opened, the most now In storage element 250, storage is logic 1 or logical zero.The electric current that so may result in ionization by collision is flowed in buoyancy aid 24, Charging to logic 1 state to it, which kind of data storage is the most in the cells.

In the example shown in Figure 51, selected zigzag electrode 70a in+1.2V voltage below-center offset, the most unselected it Word line electrode 70b (not shown)-70n is in 0.0V voltage below-center offset, and selected bit line electrode 74a is in+1.2V voltage below-center offset, same Time unselected bit line electrode 74b-74p in 0.0V below-center offset；Selected source line 72a is in 0.0V below-center offset, and unselected Source line electrode 72b (not shown)-72n in+1.2V voltage below-center offset, electrode of substrate 78 is in 0.0V below-center offset simultaneously.Above-mentioned partially Put voltage levvl and be only explanation citing use, can be different because of the example of difference.

As Figure 52 A-52B, selected storage element 50a contain door 60,60 are connected with WL electrode 70, apply+1.2V voltage, position Line region 16 is connected with BL electrode 74a, applies+1.2V voltage, and embedding layer 22 is connected with source line electrode 72a, applies 0.0V voltage, Above-mentioned electrode all biases.With this understanding, the electric current of ionization by collision will flow into unit from BL electrode 74a, in floating body region 24 Inject hole, storage element 250a writes logic 1 state.

As shown in Figure 52 C-52D, unselected storage element 250b, with selected storage element 250a have identical it Capable, different row, with door 60,60 are connected with WL electrode 70a, at+1.2V voltage below-center offset, bit line region 16 and BL electrode 74p is connected, and in 0.0V voltage below-center offset, embedding layer 22 is connected with source line electrode 72a, in 0.0V voltage below-center offset.In this condition Under, collector emitter voltage, n-p-n dipole elements 30, for 0.0V so that assembly is closed, and protects in storage element 250b Content.

As shown in Figure 52 E-52F, unselected storage element 250c, with selected storage element 250a have identical it Capable, different row, with door 60,60 are connected with WL electrode 70n, at 0.0V voltage below-center offset, bit line region 16 and BL electrode 74a Being connected, in+1.2V voltage below-center offset, embedding layer 22 is connected with source line electrode 72n, in+1.2V voltage below-center offset.In this condition Under, n-p-n dipole elements 30 is closed, because no-voltage between collector and emitter.

As shown in Figure 52 G-52H, unselected storage element 250d, have from selected storage element 250a different it Capable, different row, with door 60,60 are connected with WL electrode 70n, at+0.0V voltage below-center offset, bit line region 16 and BL electrode 74p is connected, and in 0.0V voltage below-center offset, embedding layer 22 is connected with source line electrode 72n, in+1.2V voltage below-center offset.Can see Arriving, said units will be in holding pattern.The storage element being in logic state 1 will keep the electric charge in buoyancy aid 24, because this Levying dipole elements 30 and will produce hole current, the electric charge in the reddest buoyancy aid 24, the unit being simultaneously in logical zero state will keep Neutral state.

Figure 53 A is the top view of section store array, and including the semitransistor storage element 350 of band door, Figure 53 B gives Independent storage element 350. Figure 53 C and 53D gives the sectional view of storage element 350, cuts open along I-I ' and II-II '；Figure 53 E Give conducting embedment trap and the method for unit lower substrate.Figure 54 A-54H is storage arrays 380, by the storage of different row and columns Memory cell 350 is constituted.The main difference of storage element 250 and storage element 350 is: in storage element 250, insulating barrier 26 The embedding layer 22 of adjacent lines is isolated, and in storage element 350, insulating barrier 26 region taken is substituted by insulating barrier 28. Storage element 350 four sides by insulating barrier 28 around, embedding layer 22 as individually it " source line " always with all storage elements 350 (in storage arrays 380) is connected.Constitute a storage arrays similar with storage arrays 280, but combine Figure 54 A-54F and explanation are it will be seen that part operation is still had any different.It is the same with the storage element 250 in storage arrays 280, In the bounds of storage element 350, embedding layer 22 does not has contact.

With reference to Figure 53 C and 53D, unit 350 includes a substrate 12, has the first conduction type, such as p-type.Substrate 12 leads to Often it is made up of silicon, but germanium, silicon-germanium, silicon-arsenic, CNT or other known semi-conducting materials can be comprised.At this In the certain embodiments of invention, substrate 12 can be the chip (bulkmaterial) of semiconductor crystal wafer.In other instances, substrate 12 can also be the trap with the first conduction type, or for having the trap of the second conduction type, or can also be partly to lead Chip in the chip of body wafer, has the second conduction type, such as n-type, (drawing the most in the drawings), design determines.For letter Change explanation, substrate 12 is just drawn as semiconductor chip, as shown in Figure 53 C and 53D, it should be noted that can also be one at substrate material The trap processed on material, substrate has the second conduction type.

Buoyancy aid 24, has the first conduction type, such as p-type, by bit line region 16, insulating barrier 62 and two side insulation layers 28, And the embedding layer 22 of bottom surrounds.Buoyancy aid 24 can be a part for initial substrate 12, is positioned on embedding layer 22, if mixed Miscellaneous embedding layer 22.It addition, buoyancy aid 24 can also be obtained by epitaxial growth.According to embedding layer 22 and the structure side of buoyancy aid 24 Method, in certain embodiments, buoyancy aid 24 may have identical doping, or the doping of difference with substrate 12, in the example of difference According to design it needs to be determined that.

Insulating barrier 28 (such as shallow-trench isolation (STI)), it is possible to use silicon oxide manufacture, can also use other materials that insulate Material.When unit 350 is connected into array 380, unit 350 is separated by insulating barrier 28 with adjacent unit 350, thus constitutes such as Storage assembly shown in Figure 54 A-54F.Adjacent floating body region 24 is isolated rather than embedding layer 22 by insulating barrier 28, and be buries Enter layer 22 to keep in whole array 380 continuously (conducting).

Between bit line region 15 and insulating barrier 28, there is a door 60, be positioned on floating body region 24.Door 60 is by absolutely Edge layer 62 insulate with floating body region 24.Insulating barrier 62 can use silicon oxide and/or other insulant, including height-K insulation material Material, includes but not limited to peroxidating tantalum, titanium oxide, zirconium oxide, hafnium oxide and or aluminium oxide.Door 60 can use polysilicon material Material or metal gate electrode, such as tungsten, tantalum, titanium and their nitride

Storage element 350 also includes: wordline (WL) electrode 70, is connected with door 60, bit line (BL) electrode 74, with bit line region 16 are connected, and source line (SL) electrode 72 is connected with embedding layer 22, and electrode of substrate 78, is connected with substrate 12.

As shown in Figure 53 E, the contact between SL electrode 72 and embedding layer 22, can (have second to lead by region 20 Electricity type) generate；Then it is connected with embedment well area 22；Contact between electrode of substrate 78 and substrate regions 12 simultaneously, Can be generated by region 21 (there is the first conduction type), and be connected with substrate regions 12.

SL electrode 72 is connected with embedding layer 22, as reverse biased electrode, be i.e. positioned at semiconductor transistor module backside it Electrode, is usually located at the reverse side of transistor gate.

The relatively structure of storage assembly 350, and as shown in Figure 53 C with transistor component 100,100A and 100B (such as figure 90A-90C), it can be seen that in this invention, the structure of storage assembly is less than MOSFET100,100A and 100B, the most only There is a region to have the second conduction type, be positioned at the surface of silicon substrate.Therefore, storage element 350 has an advantage, it is simply that Only comprise a region on surface, there is the second conduction type, (such as bit line region 16, relative to region 84 and 86, or region 84A and 86A), therefore require nothing more than storage element 350 and there is a contact (that is, set up between bit line region 16 and electrode 74 even Connect).

To this be skillful at it can be seen that in Figure 53 A-53E, the first and second conduction types can be in storage Memory cell 350 exchanges, design needs to determine, and p-type is appointed as the first conduction type, by the second conduction type Being appointed as n-type is the most only to illustrate conveniently, and non-limiting.Therefore, in storage element 350, the first and second conduction types P-type and n-type can be respectively, in other example, it is also possible to be respectively n-type and p-type.It addition, be familiar with this skill The people of art, it will be seen that the relative doping level of every kind of conduction type zones of different can also need to determine according to design, omits Falling higher or lower doping level, such as p+ or p0-, or n+ or n-there is no big harm.

Figure 54 A is: example array 380, containing storage element 350 (four example storage elements 350 arranged in rows and columns It is denoted as 350a, 350b, 350c and 350d).A lot, but in not all example array 380, the storage element of representative Storage element 350 selected for representative, now illustrated operation are for selected storage element 350 by 350a.At such In figure, represent the storage element 350 that storage element 350b represents unselected, have identical with selected storage element 350a OK, storage element 350c then represents unselected storage element 350, with selected storage element 350a have identical it Row, storage element 350d then represents, neither has identical trip with the storage element 350a chosen and does not the most have identical row.

Figure 54 A is, wordline 70a-70n, source line 72X, bit line 74a-74p, and electrode of substrate 78.Each wordline 70a- 70n is all connected with a storage element 350, and is connected with the door 60 of the storage element 350 of this row.Each bit line 74a-70n All it is connected with a storage element 350, and is connected with the bit line region 16 of the storage element 350 of these row.Merit attention is: Source line electrode 72X no longer be control row electrode, with one of storage element 350 row be connected, but " whole " storage element 350 it Control electrode, hereinafter referred to as source line electrode 72X, thus avert misconceptions, i.e. source line electrode 72X is for each storage individually Unit 350 still has identical function.

Substrate 12 and embedding layer 22 are respectively positioned on below array 380.The people that have gained some understanding this technology are it can be appreciated that root Need according to design, can be at the one or more electrode of substrate 78 of one or more local appearance or embedment trap electrode 72.To this The people that technology is had gained some understanding, it will also be appreciated that the example array 380 shown in Figure 54 A is expressed as a continuous array, but Being to use other various tissues and arrangements, such as wordline can be grouped or buffer, bit line can be carried out point Group or buffering, source line can be grouped or buffer, and array 380 can be divided into two or more subnumber groups, and control circuit is such as Word encoder, row encoder, analysis component, induction amplifier, write amplifier can also be arranged in around example array 380, Or it is inserted in the submatrix of array 380.

As shown in Figure 54 B, example storage arrays 380 is in array and keeps in operation.For all storages in array 380 Unit 350, keeps operation to carry out simultaneously, realizes by applying the voltage an of+1.2V on source line electrode 72, word simultaneously To apply all will apply on 0.0V, bit line electrode 74a-74p and electrode of substrate 78 0.0V on line electrode 70a-70n.This bias strip Part will make: the intrinsic transistor 30 of the storage element 350 of each stored logic 1 in array 380 is opened, and recover on buoyancy aid 24 Hole charge, as described above.Meanwhile, this bias condition will make: the storage of each stored logic 0 in array 380 is single The intrinsic transistor 30 of unit 350 cuts out, and keeping buoyancy aid 24 is electric neutrality, as described above.Above-mentioned bias voltage level is only and says Bright citing use, can be different because of the example of difference.

As shown in Figure 54 C, for the read operation of single unit 350a chosen in storage element 350.In order to realize this behaviour Make, need to apply about+1.2V on word line electrode 70a, simultaneously on unselected zigzag electrode 70b (not shown)-70n Apply 0.0V, applying+0.4V in selected bit line electrode 74a, apply in unselected bit line electrode 74b-74p simultaneously 0.0V, applies 0.0V on source line electrode 72, applies 0.0V on electrode of substrate.Above-mentioned bias voltage level only illustrates citing With, can be different because of the example of difference.

Thus dipole elements 30 is become a reverse n-p-n transistor, be similar to by dipole elements 30 as Keep mode of operation (Figure 37 A-37C).

In selected storage element 350a, the Capacitance Coupled between word line electrode 70a and buoyancy aid 24 will increase logic 1 With the difference of read current under logical zero state.The maximum bias voltage being applied on WL electrode 70 may be because of different instances and technique And it is different.Virtual voltage in various embodiments can by design it needs to be determined that.

In unselected storage element 350b, with selected storage element 350a, there is identical trip, dipole elements 30 Close, because voltage is 0 between collector and emitter.In making the short period during read operation, this storage element energy Enough keep its logic state.

Unselected storage element 350c, has identical row with selected storage element 350a, by closedown or be in Carry out more weak holding operation, depend in particular instance the characteristic of assembly under this process.Make during read operation is shorter In time, this storage element can keep its logic state.

In unselected storage element 350d, there is from selected storage element 350a different row and columns, bipolar group Part 30 is closed, because voltage is 0 between collector and emitter.In making the short period during read operation, this storage list Unit can keep its logic state.

As shown in Figure 54 D, the write logical zero operation of all storage elements 350 in an array.In order to realize this operation, All zigzag electrode 70a-70n are all in 0.0V voltage below-center offset, and all bit line electrode 74a-74p are all at the voltage of-1.2V Below-center offset, source line electrode 72 is in 0.0V voltage below-center offset, and electrode of substrate is in 0.0V voltage below-center offset.Above-mentioned bias voltage level is only For citing use is described, can be different because of the example of difference.

Above-mentioned bias condition makes the p-n junction in buoyancy aid 24 and bit line region 16 (on intrinsic bipolar assembly 30) bias, including All storage elements 350.Thus all holes in buoyancy aid 24 are shifted, simultaneously at all storage elements 350 of array 380 Middle write logical zero.

As shown in Figure 54 E, in the storage element 350 of array 380, carry out writing logical zero operation to string.In order to realize This operation, all zigzag electrode 70a-70n are all in 0.0V voltage below-center offset, and all bit line electrode 74a are at the voltage of-1.2V Below-center offset, unselected bit line electrode 74b-74p is in 0.0V below-center offset, and source line electrode 72 is at+1.2V voltage below-center offset, substrate Electrode is in 0.0V voltage below-center offset.Above-mentioned bias voltage level is only explanation citing use, can be different because of the example of difference.

Above-mentioned bias condition makes the p-n junction in buoyancy aid 24 and bit line region 16 (on intrinsic bipolar assembly 30) bias, including All storage elements 350 being connected with bit line 74a, 350a and 350c.Thus all holes in buoyancy aid 24 are shifted, simultaneously Storage element 350 on select column writes in array 380 logical zero.

So, other storage element 350 in array 380, including 350b and 350d, it is at keeping mode of operation, and The logic state of self will be kept when writing logical zero operation.

As shown in Figure 54 F, for the write logical zero operation of single unit 350a chosen in storage element 350.For reality Now this operation, needs to apply about+0.5V on word line electrode 70a, (does not draws at unselected zigzag electrode 70b simultaneously Go out) the upper applying-1.2V of-70n, selected bit line electrode 74a applies 0.2V, simultaneously in unselected bit line electrode 74b- Apply 0.0V on 74p, source line electrode 72 applies 0.0V, electrode of substrate applies 0.0V.Above-mentioned bias voltage level is only For citing use is described, can be different because of the example of difference.

Above-mentioned bias condition makes the p-n junction in buoyancy aid 24 and bit line region 16 (on intrinsic bipolar assembly 30) bias, including Selected storage element 350a.Due in selected storage element 350a, the electric capacity coupling between word line electrode 70a and buoyancy aid 24 Close so that dipole elements 30 is opened, the hole in buoyancy aid 24 is shifted.

In unselected storage element 350c, with selected storage element 350a, there are identical row, its buoyancy aid electricity Pressure will temporarily reduce, because the negative capacitance that exists between buoyancy aid 24 and door 60 (being connected with word line electrode 70n) couples, prevent bipolar Assembly 30 is opened.Make it can keep the logic state of self within the short period of read operation, make simultaneously buoyancy aid 24 it Current potential recovers to level (by just coupling realization between buoyancy aid 24 and door 60 (being connected with word line electrode 70n)) before, After having operated, word line electrode returns to normal 0.0V state.

As shown in Figure 54 G, for the use GIDL effect write logic of single unit 350a chosen in storage element 350 1 operation.In order to realize this operation, need to apply about-1.2V on word line electrode 70a, simultaneously at unselected zigzag electricity Applying 0.0V on the 70b (not shown)-70n of pole, applying+1.2V in selected bit line electrode 74a, simultaneously in unselected position Apply 0.0V on line electrode 74b-74p, source line electrode 72 applies 0.0V, electrode of substrate applies 0.0V.Above-mentioned biasing Voltage levvl is only explanation citing use, can be different because of the example of difference.

Above-mentioned bias condition makes the storage element 350a selected due to GIDL effect, turns on electric current, and see above citation Offer Yoshida.It-1.2V of word line electrode acts on jointly with it+1.2V of bit line electrode 74a, creates a highfield so that GIDL electric current flows into storage element 350a from bit line 74a, and produces enough holes in the buoyancy aid 24 of storage element 350a Electric charge, is placed on logic 1 state.

Unselected storage element 350c, has identical row with selected storage element 350a, is in hold mode. Making within the short period of write logic 1 operation, this storage element can keep its logic state.

As shown in Figure 54 H, for the use impact ionization write of single unit 350a chosen in storage element 350 Logic 1 operates.In order to realize this operation, need to apply about+1.2V on word line electrode 70a, simultaneously at unselected word Applying 0.0V on line electrode 70b (not shown)-70n, applying+1.2V in selected bit line electrode 74a, simultaneously unselected Bit line electrode 74b-74p on apply 0.0V, on source line electrode 72 apply 0.0V, on electrode of substrate apply 0.0V.Above-mentioned Bias voltage level is only explanation citing use, can be different because of the example of difference.

Above-mentioned bias condition makes the storage element 350a selected due to impact ionization, turns on electric current, sees above and draw Use document Lin.Under the effect of word line electrode+1.2V and it+1.2V of bit line electrode 74a, the dipole elements of storage element 350a 30 open, and are in which kind of logic state the most before, thus produce enough hole charge in buoyancy aid 24, are placed on logic 1 state.

In unselected storage element 350b, with selected storage element 350a, there is identical trip, dipole elements 30 Close, because voltage is 0 between collector and emitter.Making within the short period of read operation, this storage element can be protected Hold its logic state.

In unselected storage element 350d, there is from selected storage element 350a different row and columns, bipolar group Part 30 is closed, because voltage is 0 between collector and emitter.Make within the short period of read operation, this storage element energy Enough keep its logic state.

In prior example, write, read and keep is single binary digit, and is at single storage element Operate on 250 or 350.Owing to this programme has only to the noise appearance of the simplest support circuit, the simplest operational approach, maximum Limit, can obtain bigger storage density by storing two or more position on storage element 250 or 350, and cost is only Increase and support circuit and the complexity of operational approach.It addition, because the voltage window of storage element 250 or 350 is by more than 2 Logical layer is shared, and noise margin is also to reduce it.

Preferably can store the information corresponding to binary digit integer numeral in storage element 250 or 350, this just means The kind of the electric pressure being stored in storage element 250 or 350 by the power equal to 2 (e.g., 2,4,6,8 etc.), but at this In item invention, it is possibility to have other schemes.Due to lower noise margin, the data in array 80 or 380 can be compiled Code, it is possible to use any error correcting code (ECC).Relatively reliable in order to be ECC (error correcting code), the electric pressure of inside can use non- Binary coding, as used Ge Lei coding, is assigned to electric pressure by binary value.If using Ge Lei coding, then at voltage etc. In Ji, being increased or decreased of a grade only needs to change one of binary coding position.Thus, for the Pueraria lobota of two Thunder encodes, and minimum electric pressure, corresponding to the neutral state of buoyancy aid 24, can become logical zero 0, and the voltage of a high grade is permissible Being encoded to logical zero 1, then the electric pressure of high one-level can be encoded to logic 11, electric pressure the highest in buoyancy aid 24 can be right 10 should be encoded to.For one three Ge Lei encode, logic levels can be followed successively by from low to high: logical zero 00, logical zero 01, Logical zero 11, logical zero 10, logic 110, logic 111, logic 101, logic 110.The read error being most likely to occur is exactly by one Individual electric pressure is wrong as adjacent another one electric pressure, and this coding can ensure that the reading of a grade makes mistakes and will produce The error correction of raw most position/mistakes, in individual unit, is down to minimum by the figure place of reading needed for error correction.Can also use Other codings, this example is intended for explanation, non-limiting.

Multilamellar write operation can use another one write and verification algorithm to realize, and prime minister is at storage element 250 or 350 One write pulse of upper applying, carries out write operation subsequently, and verifies whether to achieve required storing state.Without realization Required storing state, then have another one write pulse and be applied on storage element 250 or 350, followed by reading/testing Card operation.This circulation is constantly reciprocal, until realizing required storing state.

Such as, use band that band is worn hot hole then and inject write storage element 250 or 350, BL electrode 74 applies one Individual 0 voltage, applies 0 voltage on SL electrode 72, applies a negative voltage, then at substrate electricity on WL electrode 70 electrode 0 voltage is applied on pole 78.After the positive voltage of various amplitude is applied on BL electrode 74, can write not on buoyancy aid 24 Same state.The difference floating body potential 24 produced is corresponding to the positive voltage of difference, or is just applied to the difference on BL electrode 74 Potential pulse.Noting, before performing this algorithm, storage element 250 or 350 must write minimum voltage shape on buoyancy aid 24 State.

In a non-limiting examples, realize write operation by applying following bias state.SL electrode 72 applies About 0.0 volt of voltage, applies about-1.2 volts on electrode 70, applies about 0.0 volt on electrode 78, simultaneously at BL electrode 74 Upper applying 0.0 voltage, steps up the current potential of 74.In a non-limiting examples, initial applying 25 microvolts on BL electrode 74 Voltage, carry out subsequently reading/verification operation.If reading/verification operation shows, cell current has reached required state and (that is, has reached To the binary value 00,01,11 or 10 cell current corresponding to one of them), then can smoothly complete multilamellar write operation.If For the state needed for reaching, then improve the voltage being applied on BL electrode 74,25 microvolts, or 50 microvolts can be increased.Subsequently will Carrying out another one reading/verification operation, this process will be repeated, until realizing required state.But, above-mentioned electric pressure Can be different because of example, it is merely to illustrate, and non-limiting.In order to write 4 grades in storage element, it is necessary at least use 3 The positive voltage pulse (can have the amplitude of difference) of middle difference, is applied on BL electrode 74.First pulse is corresponding single in storage Writing the electric pressure corresponding with binary value 01 in unit, second pulse correspondence write binary value 11 on storage element is right The electric pressure answered, the 3rd the corresponding electric pressure writing binary value 10 correspondence on storage element of pulse.

Write-verification algorithm itself is relatively slow, because the write and read that to carry out taking second place operates more.This invention proposes more than one Layer write-read operations, it may not be necessary to read and write operation alternately realizes, as shown in Figure 55 A-55F.To this technology The people of solution are it can be appreciated that for all semitransistor storage elements, above-mentioned principle is the most applicable.

As shown in Figure 55 A, the current potential of buoyancy aid 24 can increase over time because bias condition by impact ionization to Buoyancy aid 24 is filled with hole.Once the change of cell current has reached required level (has with the state of selected storage element 250 Close), then being applied to the voltage on BL electrode 74 can be removed.In this way, it is possible to by applying one during error correction Individual ramp voltage, carries out multilamellar write operation, operates without alternately write and read during execution.At the end in burst length, apply Voltage then return to initial value, such as ground connection.As shown in Figure 55 A, ramp pulse it (width T1) be applied to storage element 250 it In bit line electrode 74, storage element is in minimum current potential (logical zero 0 state), thus the current potential of buoyancy aid 24 rises from logical zero 0 To logical zero 1.Being similar to it, be applied in bit line electrode 74 by ramp pulse (width T2), storage element 250 is in potential minimum State (logical zero 0) so that the current potential of buoyancy aid 24 rises to logic 11 from logical zero 0；Then ramp pulse (width T3) is applied In bit line electrode 74, storage element 250 is in potential minimum state (logical zero 0) so that the current potential of buoyancy aid 24 is from logical zero 0 It is raised to logic 10.

As shown in Figure 55 B, this operation is by applying a slope electricity on the BL electrode 74a of selected storage element 250a It is compacted existing, on SL electrode 72a, applies 0 voltage simultaneously, WL electrode 70 electrode applies a positive voltage, selecting it 0 voltage is applied on storage element electrode of substrate 78.Thus the bias condition of generation will produce hole injection on buoyancy aid 24, Realized by ionization by collision mechanism.Storage element 250a can carry out read operation at detector unit electric current simultaneously, and electric current flows through The reading circuit 91a coupled with source line 72a.

At the remainder of array 280, unselected WL electrode 70b (not shown)-70n applies 0 voltage, Unselected SL electrode 72b (not shown)-72n applies 0 voltage, on unselected BL electrode 74b-74p Apply 0 voltage.Cell current is measured on line direction, source, is the unit electricity of the storage element 250 of all common source line 72a Stream；But all unselected unit, such as 50b, for bias state, because having from bit line region 16 to line region, source 22 The effect of 0 voltage, thus when source line electrode 72a correct bias keeps 0 voltage, the most selected storage element will not be led Electricity.Therefore, the storage element 50a every time only having a common source line 72 can be written into.

As shown in Figure 55 B, unselected storage element 250b, 0 voltage (from BL electrode 74p to SL electrode 72a it Between) effect under, do not have electric current to produce, therefore stored data mode will not change.Unselected storage element 250c and selected storage element 350a shares same BL electrode 74a, its WL electrode 70 ground connection.Thus, buoyancy aid 24 will not be subject to To the effect (elevated potential) of voltage coupling, the buoyancy aid 24 of selected storage element 250a then can be under the effect of voltage coupling Rise high voltage.Unselected SL electrode 72n is also applied with a positive bias.In this case, storage element 250c it Electric current reduces, thus decreases the hole charge received in self floating body region 24, is now applied to the electricity on BL electrode 74a Pressure raises in slope.Unselected storage element 250d, have from selected storage element 250a different trip, different it Row, with door 60,60 are connected with WL electrode 70n, and in+0.0V voltage below-center offset, bit line region 16 is connected with BL electrode 74p, 0.0V voltage below-center offset, embedding layer 22 is connected with source line electrode 72n, in+1.2V voltage below-center offset.It will be seen that said units Holding pattern will be in.The storage element being in logic state 1 will keep the electric charge in buoyancy aid 24, because intrinsic bipolar assembly 30 To produce hole current, the electric charge in the reddest buoyancy aid 24, the unit being simultaneously in logical zero state will keep neutral state.

Figure 55 B gives reference generating circuit 93a-93n, is connected with source line electrode 72a-72n respectively；Also read electricity Road 91a-91n, is connected with source line electrode 72a-72n respectively, and is connected with reference generating circuit 93a-93n respectively.Benchmark occurs Circuit 93a is used for storing cell current initial in selected storage element 250a, and in real time in write operation, this value is sent out Deliver to reading circuit 91a；The change making electric current can be detected and use feedback (for drawing in Figure 55 B) appropriate time Terminate ramp voltage.This function can realize to use the mode of difference.

In Figure 55 C, the accumulative electric charge of selected storage element 250a can be stored in electric capacity 97a, 250a common source line 72a.When electric charge needs write or reads from electric capacity 94, transistor 95a opens.

It addition, as shown in Figure 55 D, reference cell 250Ra-250Rn is similar to storage element 250, it is used for substituting benchmark and sends out Electric capacity 97a-97n in raw circuit 93a-93n.Reference cell 250Ra-250Rn can be used in the storage element 250a selected Original state.

In another example, band can be worn effect then by band on storage element 250 and realize by multilamellar write operation, On BL electrode 74, i.e. apply a ramp voltage, on SL electrode 72, apply 0 voltage simultaneously, WL electrode 70 applies One negative voltage, applies 0 voltage on the electrode of substrate 78 of selected storage element 250.Unselected unit will maintain In hold mode, i.e. apply 0/ negative voltage on WL electrode 70, and apply 0 voltage on BL electrode 74, at SL electricity A positive voltage is applied on pole 72.It addition, multiple BL electrodes 74 can also be selected simultaneously, the write parallel to multiple unit.Choosing Determining in storage element 250, band will be worn mechanism then due to band and raise by the current potential of buoyancy aid 24.Selected storage element 250 can be Detector unit electric current carry out read operation simultaneously, electric current flows through the reading circuit 91 coupled with source line 72.The once change of cell current Change the level (relevant with the state of storage element 50) having reached required, then being applied to the voltage on BL electrode 74 can be removed. In this way, it is possible to carry out multilamellar write operation, operate without alternately write and read during execution.

In another one example, as shown in Figure 55 E, simultaneously, can be by detection storage element reading also write operation Curent change in bit line direction carries out read operation, and this electric current passes through the reading circuit 99a coupled with bit line 74a (such as Figure 55 E Shown in).In certain embodiments, reading circuit 99b-99p (not drawing in Figure 55 E) can additionally each with bit line 74b-74p Individual position is connected；And in other instances, reading circuit 99a can use decoding scheme (not shown) to be shared by multiple row.

The reference cell 250R representing different storing state can be used to verify the state of write operation.Reference cell 250R Can by writing-verification operation is set, such as when all storage assemblies start for the first time or grasp in follow-up refreshings During work.Thus, when selected storage element 250a is written into, the selected reference cell 250R that will be written into contains institute The voltage status (or similar voltage) of need, through reading, feeds back to reading circuit by value so that write operation can be in selected storage When the magnitude of voltage of unit 250a reaches required value, terminated.In certain embodiments, the row of multiple reference cells can comprise The reference value of difference, corresponding to the write value (not drawing in Figure 55 E) of multiple different layers unit.

In ramp voltage operates, the cell current of the write storage element 250a produced, will be used to and benchmark list The electric current of unit 250R contrasts, and is realized by reading circuit 99a.During the operation that above-mentioned reading is simultaneously written, reference cell 250R is biased also with the bias condition identical with selected storage element 250, now carry out be selected storage element 50 it Write operation.Therefore, write operation needs to stop after reaching required location mode, to prevent from changing the shape of reference cell 250R State.

As shown in Figure 55 F, slope current is operated, voltage rather than the cell current of bit line 74a can be sensed.? During slope current operation, positive bias be applied on the line electrode 72a of source, then electric current will pass through BL electrode 74a.BL electrode 74a Voltage will react the state of storage element 250a.During beginning, storage element 250a is in logical zero state, at storage element 250a is upper it can be seen that bigger voltage drop, and the voltage on BL electrode 74a is by relatively low.Along with electric current flows from storage element 250a Entering, and increase, the hole of injection will increase so that storage element 250a is placed in logic 1 state.In logic 1 state write operation At the end of, the voltage drop of storage element 250a can decline, it is possible to sees that the current potential of BL electrode 74a rises.

(without read-write operation alternately) in the example of a multilamellar write operation, given bit line direction uses One operation/scheme reading programming simultaneously, each storage element 250 stores 2 positions, it is desirable to each storage element 250 can store 4 states.

Along with the increase of electric charge in buoyancy aid 24,4 states can be expressed as 00,01,10,11.In order to by storage element 250a is programmed to state 01, and state 01 corresponding for reference cell 250R will be activated.Thus, bias strip described above Part, will use the reference cell 250R of selected storage element 250 and 01 simultaneously.Source line electrode 72 applies one 0 electricity Pressure, applies 0 voltage on electrode of substrate 78, applies a positive voltage (by ionization by collision mechanism) on WL electrode 70, On BL electrode 74, apply a ramp voltage from 0 beginning simultaneously.From the ramp voltage of low-voltage (such as 0 voltage) beginning, energy Enough ensure that the state of reference cell 250R will not change.

Subsequently, the voltage being applied on BL electrode 74a will raise.As a result, hole is injected into, selected unit 50 is to float In body 24, and the cell current of selected unit 250 increases therewith.The cell current once selecting unit 250 reaches 01 benchmark The electric current of unit, write operation i.e. stops, and the positive voltage being applied on L electrode 74 and WL electrode 70 is i.e. removed.

In unselected storage element 250b, with selected storage element 250a, there is identical trip, dipole elements 30 Close, because voltage is 0 between collector and emitter.Make within the short period of multilamellar write operation, this storage element Its logic state can be kept.

Unselected storage element 250c, has identical row with selected storage element 250a, is in hold mode. Owing to the potential difference between SL electrode 72n and BL electrode 74a (that is, the emitter and collector of n-p-n dipole elements 30) is less, Base current will not be produced flow in buoyancy aid 24.Making within the short period of multilamellar write operation, this storage element can be protected Hold its logic state.

Unselected storage element 250d, does not have identical column or row with selected storage element 250a, is in guarantor Hold state.Making within the short period of multilamellar write operation, this storage element can keep its logic state.

Merit attention is that, during the holding of storage element 250 operates, its state is to automatically select in various modes It.It is to say, the number of cavities being injected in buoyancy aid 24 is proportional to hole (i.e. electric charge) quantity existing in buoyancy aid 24 It.Therefore, each storage element will select the holding electric current of self.

Figure 56-57 is, the semitransistor storage element 250V, Figure 57 of band door give storage element 250V shown in Figure 56 it Top view.Seeing Figure 56 and 57, the selection of Ref. No. uses the principle of identical numbering to carry out according to identical, similar functions. In this example, unit 250V has fin structure 52, manufactures on the substrate 12, enabling extends at substrate surface and obtains one Individual three dimensional structure, the generallyperpendicular upper surface (on and) extending to substrate 12 of fin 52.Fin structure 52 turns on, at embedment trap Building on layer 22,22 are positioned at the surface of substrate 12.It addition, embedment trap 22 can also allow other fin in substrate 12 diffusion inside Type structure 52 builds thereon；Or embedment trap 22 can also make the conductive layer on substrate 12, with other fin structure 52 phases Even, storage element 350 similarly as described above.Fin 52 is generally made up of silicon, but can comprise germanium, silicon-germanium, silicon-arsenic, carbon Nanotube or other known semi-conducting materials.

Embedment well layer 22 can be processed on the material of substrate 12 by ion doping technique and be obtained, and is then etched, Imbed trap 22 after making etching to be located on substrate 12.It addition, embedment well layer 22 can also pass through epitaxial growth, at substrate 22 Upper processing obtains, it is not necessary to part can etch away.Embedment well layer 22, has the second conduction type (such as n-type conductive-type Type), buoyancy aid 24 is insulated with chip substrate 12,24 have the first conduction type (such as p-type conduction type), and 12 have first leads Electricity type.Fin structure 52 includes bit line region 16 (having the second conduction type, such as n-type conduction type).Storage element 250V Also include door 60, be positioned at the both sides of buoyancy aid substrate regions 24, insulating barrier 62 separate with buoyancy aid 24.Door 60 by insulating barrier 62 with Buoyancy aid 24 separates (insulation).Door 60 is between bit line region 16 and insulating barrier 28, adjacent with buoyancy aid 24.

Therefore, around buoyancy aid 24 it is: the upper surface of fin 52, side and towards territory, purgation bitline regions 16, and embedment well layer The top of 22, and insulating barrier 26,28,62.When unit 250V is connected into array, insulating barrier 26 and 28 is by unit 250V and phase The unit 250V of neighbour separates, thus constitutes storage assembly as shown in the figure.Adjacent embedment trap 22 is separated by insulating barrier 26, and exhausted Edge layer 28 is not result in that imbedding trap separates.So, embedding layer 22 defines the most in one direction and is continuously turned on.At this example In, the surface 14 of quasiconductor is positioned at the top of fin structure.In other instances, at semiconductor surface 14, storage element 250V Within border, embedding layer 22 is contactless to be attached thereto.

As shown in Figure 58 A, another fin structure 52A can be built.In this example, door 60 and insulating barrier 62 surround Three sides of buoyancy aid substrate regions 24.The electric charge to buoyancy aid 24 that door 60 three sides is exactly is capable of more preferable control System.

Storage element 250V can be used to replace storage element 250, place array to be similar to array 280, in unit sum Between the control signal electrode of group, there is similar connection.In the case, keep, reading and writing operation all with parallel element above Example is similar to, such as the storage element 250 in array 280.In other instances, the first and second conduction types can exchange, and presses Select according to design needs.In other instances, it is also possible to using deformation and the assembly combination of difference, this example is intended for Bright, indefinite mesh it.

Figure 58 B gives the storage element 250V in array 280V.According to the feature of fin structure 52A, the compactest cloth Put and be usually perpendicular to source line 72 along bit line 70 and arrange rather than as in array 280, be arranged in parallel.This just obtains The structure of array 580, wherein unit 250V uses fin structure 52A to build, and source line 72a-72p is parallel with bit line 74a-74p, Vertical with wordline 70a-70m.The operation of relevant storage arrays 280V, at U.S. Patent application " COMPACT SEMICONDUCTOR MEMORY DEVICE HAVING REDUCED NUMBER OF CONTACTS, METHODS OF OPERATING AND METHODS OF MAKING " in be described in detail, authorize artificial AttomeyDocketNo.Zeno014, numbering 12/89758, Date of filling on October 4th, 2010, quote herein.

Shown in Figure 59 A, for the semitransistor storage element 450 (being illustrated by the broken lines) of another one band door.Figure 59 B is figure A part of 59A, including single storage element 450, and sectional view I-I ' and II-II '.Figure 59 C is the section view of I-I ' in Figure 59 B Figure.Figure 59 D is the sectional view of II-II ' in Figure 59 B.In Figure 59 A-59F, substrate 12, semiconductor surface 14, bit line region 16, Embedment well layer 22, floating body region 24, insulating barrier 26 and 28, door 60, door insulator 62, word line electrode 70, embedment trap electrode 72, position Line electrode 74, electrode of substrate 78, all parts with similar functions all use identical reference to compile with storage element 250 Number.

With reference to Figure 59 A, 59B, 59C and 59D, unit 450 includes a substrate 12, has the first conduction type, such as p-type. Substrate 12 is generally made up of silicon, but can comprise germanium, silicon-germanium, silicon-arsenic, CNT or other known quasiconductor materials Material.Embedding layer 22 has the second conduction type, is positioned on substrate 12.Embedding layer 22 can also be by ion doping technique at substrate Process on the material of 12.It addition, embedding layer 22 can also be obtained by epitaxial growth.

Bit line region 16 has the second conduction type, such as n-type, is positioned in floating body region 24, towards surface 14.Bit line 16 Being processed on the composition material of buoyancy aid 24 by a doping process, use is to be currently known and the doping process of typical case.Separately Outward, it is possible to use solid state diffusion process generates territory, bitline regions 16.

Buoyancy aid 24 on the substrate 12 is surrounded by surface 14, bit line region 16, insulating barrier 26 and 28 and embedding layer 22.Absolutely Edge layer 26 and 28 (such as shallow-trench isolation (STI)), it is possible to use Si oxide.When unit 450 is connected into array 180, insulation Unit 450 is separated by layer 26 and 28 with adjacent unit 450, thus constitutes the storage assembly as shown in Figure 61 A.Insulating barrier 26 will Adjacent cells buoyancy aid 24 and embedment region 22 isolate (including storage element 450A, 450 and 450B), and insulating barrier 28 is by adjacent simultaneously Floating body region 24 isolate, but do not isolate adjacent buried layer region 22 so that embedding layer 22 can in one direction ( Along direction shown in II-II ' in Figure 35 D) extend (being i.e. held on).(as shown in Figure 59 B and 59D).In other instances, half Conductive surface 14, within storage element 450 border, embedding layer 22 is contactless to be attached thereto.

Door is 60 between the bit line region 16 of adjacent cells 450 and 450A, and surface 14, floating body region 24 and wherein one On individual adjacent insulating barrier 26, as shown in Figure 59 C.In the design, the door 70 of storage element 450 and 450A all with door 60 phase Even.Door 60 is insulated with surface 14 by insulating barrier 62.Insulating barrier 62 can use silicon oxide and/or other insulant, including But it is not limited to peroxidating tantalum, titanium oxide, zirconium oxide, hafnium oxide and or aluminium oxide.Door 60 can use polycrystalline silicon material or metal Gate electrode, if tungsten, tantalum, titanium and their nitride are in Figure 59 A, 59B and 59C, door 60 is positioned on insulating barrier 26, by adjacent Unit 450 and 450A isolation.

Unit 450 also includes: wordline (WL) electrode 70, is connected with door 60, bit line (BL) electrode 74, with bit line region 16 phase Even, source line (SL) electrode 72, it is connected with embedding layer 22, and electrode of substrate 78, it is connected with substrate 12.

As shown in Figure 59 E, the contact between SL electrode 72 and embedding layer 22, can (have second to lead by region 20 Electricity type) generate；Then it is connected with embedment well area 22 and embedment trap electrode 72；Be connected with substrate regions 12 touching simultaneously Point, can be generated by region 28 (having the first conduction type), and be connected with substrate regions 12 and electrode of substrate 78.SL electricity Pole 72 is used as the reverse biased electrode of storage element 450.

As shown in Figure 59 F, embedment trap 22 (and SL electrode 72 below) can be by adjacent storage element 450 and 450B Share rather than shared WL electrode 70.In this example, the degree of depth of insulating barrier 26A is similar with insulating barrier 28, enabling use Embedment trap 22 builds this connection.Therefore, when be arranged in array to storage element 450 time, source line electrode 72 is by adjacent lines Paired unit 450 share, word line electrode 70 is shared by the paired unit of adjacent lines, owing to there being line electrode 72 trip of shared source, Need the line displacement of shared word line.Storage element 4500 is made to share same source line electrode with adjacent unit (such as 450B), The unit (such as 450A) adjacent with another shares a word line electrode 70.Should be noted that is, because storage element 450 trip It is mirror-image arrangement, it is possible to realize above-mentioned connection, but storage element 50 not mirror-image arrangement.

In Figure 60 A-60E, for the example of another storage element 450, paired door 60 can adjacent with buoyancy aid 24 it Building in groove, buoyancy aid belongs to two adjacent storage elements 450.This example is with the main difference of example in Figure 59 A-59E, The insulating barrier 26 of row front and back, adjacent with buoyancy aid 24 and be positioned at below door 60, all with a groove, it is labeled as 26T, such as Figure 60 C Shown in.This groove can insert an insulator 62 and door material 60, constitutes T-shape structure.Thus make the door 60 can be at two Side is adjacent with buoyancy aid 24, is capable of the more preferable control of electric charge in floating body region 24, in order to corresponding by wordline electricity simultaneously Pole 70 is applied to the signal of telecommunication on door 60.Wherein, by the operation driving word line electrode to carry out, come by applying a positive voltage Promote the current potential (being realized by Capacitance Coupled) of buoyancy aid 24, will benefit from this design, because the electric capacity between door 60 and buoyancy aid 24 By extended.

As shown in Figure 60 A, for the top view of storage element 450 (dotted line) example.As shown in Figure 60 B, for one of 60A portion Point, and I-I ' and II-II ' sectional view.Figure 60 C is the sectional view of I-I ' in Figure 60 B.Figure 60 D is the section view of II-II ' in Figure 60 B Figure.In Figure 60 A-60F, substrate 12, semiconductor surface 14, bit line region 16, embedment well layer 22, floating body region 24, insulating barrier 26 and 28, door 60, door insulator 62, word line electrode 70, embedment trap electrode 72, bit line electrode 74, electrode of substrate 78, all have The parts of similar functions all use identical Ref. No. with storage element 250.

With reference to Figure 60 A, 60B, 60C and 60D, unit 450 includes a substrate 12, has the first conduction type, such as p-type. Substrate 12 is generally made up of silicon, but can comprise germanium, silicon-germanium, silicon-arsenic, CNT or other known quasiconductor materials Material.Embedding layer 22 has the second conduction type, is positioned on substrate 12.Embedding layer 22 can also be by ion doping technique at substrate Process on the material of 12.It addition, embedding layer 22 can also be obtained by epitaxial growth.

Region 16 has the second conduction type, such as n-type, is positioned in floating body region 24, towards surface 14.Region 16 is passed through One doping process is processed on the composition material of buoyancy aid 24, and use is to be currently known and the doping process of typical case.It addition, also Solid state diffusion process can be used to come formation zone 16.

Buoyancy aid 24 on the substrate 12 is by surface 14, bit line region 16, insulating barrier 26 and 28 and embedding layer 22 and groove 26T Surround.Insulating barrier 26 and 28 (such as shallow-trench isolation (STI)), it is possible to use Si oxide.When unit 450 is connected into array 480 Time, unit 450 is separated by insulating barrier 26 and 28 and groove 26T with adjacent unit 450, thus constitutes the storage as shown in Figure 61 A Assembly.Adjacent cells buoyancy aid 24 and embedment region 22 are isolated and (are included storage element 450A, 450 and by insulating barrier 26 and groove 26T 450B), adjacent floating body region 24 is isolated by insulating barrier 28 simultaneously, but does not isolate adjacent buried layer region 22 so that bury Enter layer 22 and can extend (being i.e. held on) (along direction shown in II-II ' in Figure 35 D) in one direction.(such as Figure 60 B and Shown in 60D).

Door 60 is positioned in groove 26T, between the bit line region 16 of adjacent cells 450 and 450A, is positioned on surface 14, The structure of a T-shape is built, as shown in Figure 60 C on floating body region 24.In the design, storage element 450 and 450A Door 70 be all connected with door 60.Door 60 is isolated in surface 14 and the side of groove 26T and bottom by insulating barrier 62 and floating body region 24. Insulating barrier 62 can use silicon oxide and/or other insulant, includes but not limited to peroxidating tantalum, titanium oxide, zirconium oxide, oxygen Change hafnium and or aluminium oxide.Door 60 can use polycrystalline silicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitride groove 26T can be obtained by silicon etch process processing, is similar to the STI moulding process of use after STI26 and 28 molding.With Groove 26T is as different in thick-oxide in a state of excitement, and gate oxide 62 can be obtained by growth after trench etch, carry out afterwards door 60 it Build.

Unit 450 also includes: wordline (WL) electrode 70, is connected with door 60, and bit line (BL) electrode 74 is connected with region 16, Source line (SL) electrode 72, is connected with embedding layer 22, and electrode of substrate 78, is connected with substrate 12.

As shown in Figure 60 F, embedment trap 22 (and SL electrode 72 below) can be by adjacent storage element 450 and 450B Share rather than shared WL electrode 70.In this example, the degree of depth of insulating barrier 26A is similar with insulating barrier 28, enabling use Embedment trap 22 builds this connection.Therefore, when be arranged in array to storage element 450 time, source line electrode 72 is by adjacent lines Paired unit 450 share, word line electrode 70 is shared by the paired unit of adjacent lines, owing to there being line electrode 72 trip of shared source, Need the line displacement of shared word line.Storage element 4500 is made to share same source line electrode with adjacent unit (such as 450B), The unit (such as 450A) adjacent with another shares a word line electrode 70.Should be noted that is, because storage element 450 trip It is mirror-image arrangement, it is possible to realize above-mentioned connection, but storage element 50 not mirror-image arrangement.

The people that this technology is had gained some understanding it can be appreciated that storage element 450 will may be used for other a lot of examples, as Shown in Figure 59 A-60F.Such as, the first and second conduction types can exchange, and needs according to design.Other geometry entities, such as base Plate 12 can substitute with the trap on substrate, and substrate has the second conduction type (not shown), according to design needs.Therefore, this is real Example is intended for explanation, is not belonging to the restriction to this invention.

Figure 61 A show the storage arrays 450 in array 480.In example array 480, storage element 450 selects position For: the storage element 450 in adjacent lines can share a bit line 70a-70n, and adjacent storage element row can be shared Same source line 72a-72n+1, wherein storage element is because of a line displacement.Therefore, a source line 72 will be had more, with line 70 phase Ratio, because top and bottom trip all do not have adjacent storage element 450 can share a source line 72.Because WL is electrode 70a- 70n and source line electrode 72a-72n+1 can be shared by adjacent storage element, it is possible to realizes less storage arrays 480, because of For sharing the effective area that can reduce storage element 450.It addition, the storage element 450 in storage arrays 460 can be according to many Article one, wordline 70 is arranged, wordline is than source line more than 72, because the provisional capital of top and bottom does not has to share zigzag 70.

As shown in Figure 61 B, for the circuit diagram of single storage element 450, with storage element 250 phase shown in Figure 37 A With, main difference is the physical arrangement of storage element 250 and 450, relative position, and the control line shared.Therefore, The operating principle of storage element 450 will be identical with aforementioned storage element 250.The operation of storage element, wherein WL are described below Share by adjacent storage element with SL electrode.This people being skillful at is not difficult to find out, the operation of storage element 450, altogether Enjoy wordline 70, but use the source line 72 of difference, by realizing with the operation not sharing source line 72, or can also be able to lead to Cross similar method to operate other row.

As shown in Figure 62, the holding operation of storage element 450 can come real by the method similar with storage element 250 Existing, positive bias will be applied to reverse biased electrode (that is, SL electrode 72 is connected) with embedment well area 22, simultaneously by bit line electricity Pole 74 ground connection (is connected with bit line region 16), and electrode of substrate 78 is connected with substrate simultaneously.As it was previously stated, keep operation and be applied to Voltage on electrode 70 is unrelated, and electrode 70 is the most preferably connected to ground.Bipolar group of the n-p-n in storage element 450 inside Part 30 is made up of embedment well area 22, buoyancy aid 24 and bit line region 16.

If buoyancy aid 24 positive charge (and being in logic 1 state), then bipolar transistor 30 is (by bit line region 16, buoyancy aid 24 are constituted with embedment well area 22) will open, as shown in Figure 37 A-37C.A part for bipolar transistor current will be flowed into floating Body region 24 (usually becomes base current), and keeps "-1 " state purgation data.The efficiency keeping operation can be by double The design of pole assembly improves, and will imbed well area 22, floating body region 24, bit line region 16 form the bipolar of a low gain Assembly, wherein bipolar gain is defined as the collector current base current than upper inflow floating body region 24 of-SL electrode 72 outflow.

For the storage element of logic state 0, dipole elements will not be opened, and is flowed into floating without base stage hole current In body 24, see Figure 37 A-37C.Make, continue to keep this state at state " 0 " purgation storage element.

Periodicity positive voltage pulse is applied on SL electrode 72 rather than applies a constant positive bias, will reduce The energy consumption of storage element 450, is similar to shown in Figure 38 A-38D.

As shown in Figure 62, operation purgation bias condition is being kept for 2 row in storage arrays 480.In non-limiting examples, Being applied on the line electrode 72b of source by+1.2 volt voltages, source line electrode 72a and 72c that 0.0 volt of voltage is applied to other (does not draws Go out) on-72n+1,0.0 volt of voltage is applied on BL electrode 74a-74p, 0.0 volt of voltage is applied to WL electrode 70a-70n On, 0.0 volt of voltage is applied on electrode of substrate 78a-78n+1.450a, 450c, 450d and 450f is thus made to be in Hold mode.Above-mentioned electric pressure is example use, can select according to technology node or design, the meaning of indefinite.

As shown in Figure 63 and 64A-64P, being stored in the electric charge in buoyancy aid 24 can be by detecting the unit of storage element 450 Electric current senses.If unit 450 is in logic 1 state, i.e. buoyancy aid 24 and stores hole, then storage element will have relatively The cell current of height, and is in the unit 450 of logical zero state, and in buoyancy aid 24, the storage element without hole is compared.Sensor circuit Generally it is connected with the BL electrode 74 in array 480, may be used to determine the data mode in storage element.Example reference The discussion of Yoshida, Ohsawa-1, Ohsawa-2.

Read operation can be carried out on storage element 450: apply on selected BL electrode 74 by following bias condition One positive voltage, and on selected BL electrode 74, one ratio of applying selectes positive voltage bigger on WL electrode 70, selected SL electrode 72 on apply 0 voltage, on electrode of substrate 78 apply 0 voltage.Unselected BL electrode will keep 0 Voltage, unselected WL electrode will keep 0 voltage, and unselected SL electrode will keep positive voltage.

In Figure 63, give the storage arrays 480 bias condition when read operation；Selected storage element 450a is being entered Bias condition during row read operation, such as Figure 64 A-64B；The unselected storage element 450b-450h bias when read operation Situation is as shown in Figure 64 C-64P.Wherein, unselected storage element 450b, shares identical WL electrode 70a and BL electrode 74a, but do not share same SL electrode 72, as shown in Figure 64 C-64D with selected storage element 450a.Wherein, unselected Storage element 450c, share identical SL electrode 72b and BL electrode 74a, but do not share with selected storage element 450a Same WL electrode 70, as shown in Figure 64 E-64F.Wherein, unselected storage element 450d, shares identical WL electrode 70a With SL electrode 72b, but do not share same BL electrode 74, as shown in Figure 64 G-64H with selected storage element 450a.At figure In 64I-64J, bias condition on unselected storage element 450e is as it can be seen, 450e is total to selected storage element 450a Enjoy same WL electrode 70a, but do not share SL electrode 72 and BL electrode 74.In Figure 64 K-64L, unselected storage element The upper bias condition of 450f is as it can be seen, 450f shares same SL electrode 72b with selected storage element 450a, but does not share WL Electrode 70 and BL electrode 74.Wherein, unselected storage element 450g, share identical BL electrode 74a, but not with selected Storage element 450a share same WL electrode 70 and SL electrode 72, as shown in Figure 64 M-64N.Not with selected storage element 450a shares the bias condition of the storage element 450h of any control electrode, as shown in Figure 64 D-64P.

In a non-limiting examples, in Figure 63,64A and 64B, the bias condition of selected storage element 450a such as schemes institute Show.In an example, applying about 0.0 volt is applied on the SL electrode 72b that selectes, is applied to select by about+0.4 volt Bit line electrode 74a on, about+1.2 volts are applied on selected zigzag electrode 70a, apply about 0.0 volt and arrive electrode of substrate (do not draw in Figure 64 B) on 78.

In the remainder of example array 480, unselected bit line electrode 74b-74p keeps 0.0 volt, unselected Zigzag electrode 70b-70n keeps 0.0 volt, and unselected SL electrode 72a and 72c (not drawing in Figure 63)-72n+1 keeps At+1.2 volts.Shown in Figure 64 C-64P, for other details of storage element 450b-450h unselected in storage arrays 480. Should be noted that is: above-mentioned electric pressure is example use, can select according to technology node or design, indefinite it Meaning.

As shown in Figure 63,64C and 64D, storage element 450b and chosen storage element 450a shares identical WL electricity Pole 70a and BL electrode 74a, but do not share SL electrode 72.The potential difference of BL and SL electrode (and the emitter stage of dipole elements 30 and collection Electrode) less than storage element, it is possible to reduce the base current being flowed into buoyancy aid 24.Further, since read Having operated very fast (nanosecond), compared with the life-span (Millisecond) of electric charge in buoyancy aid 24, be will not store it in buoyancy aid Electric charge causes many large disturbances.

As shown in Figure 63,64E and 64F, storage element 450c and chosen storage element 450a shares identical SL electricity Pole 72b and BL electrode 74a, but do not share WL electrode 70, but when BL electrode forward bias, WL electrode 72b and SL electrode 72 All ground connection.It will be seen that these storage elements 450c is in holding pattern, storage element be in logic 1 state it, can keep floating Electric charge in body 24, because intrinsic n-p-n dipole elements 30 can produce hole current, with the electric charge in supplementary buoyancy aid 24；Simultaneously The storage element being in logical zero state will keep neutral state.

As shown in Figure 63,64G and 64H, storage element 450d and chosen storage element 450a shares identical SL electricity Pole 72b and WL electrode 70a, but do not share BL electrode 74, but when WL electrode is under+1.2V voltage effect, SL electrode 72b and The equal ground connection of BL electrode 74b.Therefore owing to there is no voltage difference between the emitter and collector of n-p-n dipole elements 30, store Unit 450d will not be constantly in hold mode.Further, since read operation complete comparatively fast in (nanosecond), with buoyancy aid 24 electric charge it Life-span (Millisecond) is compared, and be will not cause many large disturbances to the electric charge of storage in buoyancy aid.

As shown in Figure 63,64I and 64J, storage element 450e and chosen storage element 450a shares identical WL electricity Pole 70a and SL electrode 72, but do not share BL electrode 74.It will be seen that these storage elements 450e is in holding pattern, store single Unit be in logic 1 state it, the electric charge in buoyancy aid 24 can be kept because intrinsic n-p-n dipole elements 30 can produce hole current, With the electric charge in supplementary buoyancy aid 24；The storage element being simultaneously in logical zero state will keep neutral state.

As shown in Figure 63,64K and 64L, storage element 450f and chosen storage element 450a shares identical SL electricity Pole 72b, but do not share BL electrode 74 and WL electrode 70.Accordingly, because n-p-n dipole elements 30 emitter and collector it Between do not have voltage difference, storage element 450f will not be constantly in hold mode.Further, since read operation completes comparatively fast (nanosecond Level), compared with the life-span (Millisecond) of electric charge in buoyancy aid 24, be will not cause many large disturbances to the electric charge of storage in buoyancy aid.

As shown in Figure 63,64M and 64N, storage element 450g and chosen storage element 450a shares identical BL electricity Pole 74a, does not share SL electrode 72 and WL electrode 70, is now applied with positive voltage on BL electrode 74.Due to SL electrode 72 and BL electricity Potential difference between pole 74 (that is, the emitter and collector of n-p-n dipole elements 30) is less, will not produce base current and flow into In buoyancy aid 24.Further, since read operation completes comparatively fast (nanosecond), compared with the life-span (Millisecond) of electric charge in buoyancy aid 24, it is The electric charge of storage in buoyancy aid will not be caused many large disturbances.

As shown in Figure 63,64O and 64P, storage element 450h and selected storage element 450a do not share any WL, BL and SL electrode, SL electrode 72 will keep positive electricity, BL electrode maintained at ground (Figure 64 O-64P) simultaneously.It will be seen that these storage elements Be in holding pattern, storage element be in logic 1 state it, the electric charge in buoyancy aid 24 can be kept, because bipolar group of intrinsic n-p-n Part 30 can produce hole current, with the electric charge in supplementary buoyancy aid 24；The storage element being simultaneously in logical zero state will keep neutrality State.

Should be noted that is: above-mentioned electric pressure is example use, under the conditions of difference, can according to technology node or Design to select, the meaning of indefinite.

2 row write at storage element 450 enter logical zero operation, as shown in Figure 65.At reverse biased electrode (that is, SL electrode 72) one negative bias of upper applying, applies 0 voltage on WL electrode 70, applies on BL electrode 72 and electrode of substrate 78 One 0 voltage.Unselected SL electrode 72 will keep forward bias.With this understanding, the p-n junction (buoyancy aid of selected unit 50 Between 24 and embedment trap 22) forward bias, shifts the hole in buoyancy aid 24.In a specific non-limiting example, will be big The voltage of about 0.5 volt is applied on electrode 72, and the voltage of about 0.0 volt is applied on electrode 70, and by about 0.0 volt Voltage be applied on electrode 74 and 78.Above-mentioned magnitude of voltage can also be different, if the relativeness between above-mentioned electric charge.

In Figure 65, chosen SL electrode 72b is at the voltage below-center offset of about 0.5V, the most unselected SL electrode 72a, 72c (not shown) 72n+1 is in the voltage below-center offset of about+1.2V；WL electrode 70a-70n in the voltage below-center offset of 0.0V, BL electrode 74a-74p is in 0.0V voltage below-center offset, and electrode of substrate 78a-78n+1 is in 0.0V voltage below-center offset.In certain embodiments, Substrate is actually the trap in another one substrate (not shown), and electrode of substrate can be kept away in the voltage below-center offset of about 0.5V Exempt from selected SL electrode 72, produce the electric current that need not.So, allow for all storage elements 450 all with SL electrode 72b is connected, including storage element 450a, 450c, 450d, 450f of selecting, in order to write logical zero state.

As shown in Figure 65,66A and 66B, enter in two row write for selected in storage arrays 480 and unselected storage element 480 Bias condition during logical zero operation.For selected storage element, 450a, 450c, 450d, 450f, it is applied to SL electrode 72 Upper back bias voltage will produce big potential difference between buoyancy aid 24 and embedment well area 22.Thus make the hole in buoyancy aid 24 Electric charge flows out.Owing to embedment trap 22 is shared by multiple storage elements 50, all storage elements 450 sharing SL electrode 72 will be write Enter logical zero state.

In unselected storage element 450, the bias condition of n-p-n dipole elements 30 is as shown in Figure 66 A-66B, including Storage element 450b, 450e, 450g, 450h, during write logical zero operation.Owing to write logical zero operation relates to selected SL electrode 72 apply a negative voltage, the bias condition of all unselected cells is the most identical.Unselected storage element will It is in holding operation, BL electrode applies about 0.0 volt, WL electrode applies 0 volt, for chosen SL electrode forward bias.

As seen in figure 67, the operation of single-row write logical zero can realize by applying back bias voltage on BL electrode 74, and without Use SL electrode 72 (as shown in Figure 65,66A and 66B).SL electrode 72 can apply with forward bias on electrode of substrate 78 simultaneously One 0 voltage, applies 0 voltage on WL electrode 70.With this understanding, the storage element of all shared BL electrodes 74 is permissible Being written into logical zero state, it is constant that the most every other storage element 450 is in hold mode.

In Figure 67, selected BL electrode 74a can be at the voltage below-center offset of about-1.2V, the most unselected BL Electrode 74b-74p is 0.0 volt of voltage below-center offset, and WL electrode 70a-70n is at 0.0V voltage below-center offset, source line electrode 72a-72n+1 In about+1.2V voltage below-center offset, electrode of substrate 78a-78n+1 is in about 0.0V voltage below-center offset.With this understanding, all with The storage element 450 that BL electrode 74a is connected, including storage element 450a, 450b, 450c and 450g of selecting, all will be written into Logical zero state, simultaneously its storage element 450 therewith, including unselected storage element 450d, 450e, 450f, 450h, all Holding pattern will be in.Above-mentioned electric pressure is example use, can select according to technology node or design, indefinite Meaning.

As shown in Figure 68 and 69A-69P, single unit allows write 0 operation of unit write, it is simply that on WL electrode 70 Apply a positive voltage, BL electrode 74 applies a negative voltage, SL electrode 72 applies 0/ negative voltage, at substrate One 0 or positive voltage is applied on electrode 78.In the case of hereinto, owing to being applied with a positive voltage, buoyancy aid on WL electrode 70 The current potential of 24 will be raised by Capacitance Coupled.Make: the current potential of buoyancy aid 24 raises, and negative voltage is applied on BL electrode 74,24 Hes P-n junction forward bias between bit line region 16, the hole on buoyancy aid 24 is fallen in transfer.Thus decrease in storage arrays 480 to Other storage elements 450 cause write logical zero interference, and the current potential applied can optimize as follows: if it is assumed that have The current potential of the buoyancy aid 24 of logic 1 state is V_FB1, then buoyancy aid 24 can be improved by the voltage that setting is applied on WL electrode 70 Current potential, V can be improved_FB1/ 2, and-V_FB1/ 2 voltages being just applied to BL electrode 74.

In a non-limiting examples, following bias condition can be applied on selected storage element 450a: at SL electricity Apply about 0.0 volt on the 72b of pole, BL electrode 74a apply about 0.2 volt, WL electrode 70a applies about+0.5 volt, Electrode of substrate 78a-78n+1 applies about 0.0 volt；Simultaneously at the SL electrode 72a-72c (not shown)-72n+ for being selected Apply about+1.2 volts on 1, BL electrode 74b-74p applies about 0.0 volt, on unselected WL electrode 70b-70n Apply about 0.0 volt.It is partially that Figure 68 gives selected storage element 450 and unselected storage element 450 in storage arrays 480 Pressure situation.Above-mentioned electric pressure is example use, can select according to technology node or design, the meaning of indefinite.

Under write logical zero operation, the bias condition of selected storage element _ 450a can by Figure 69 A-69B specifically Bright.As discussed above it, the electric potential difference between buoyancy aid 24 and bit line region 16 (being connected with BL electrode 74a) increases now, Result in the bias current hole current more than base stage of forward bias, this hole current is produced by n-p-n dipole elements 30a, 30b Raw, dipole elements is constituted by imbedding well area 22, buoyancy aid 24 and bit line region 16.Result is exactly that hole is shifted from buoyancy aid 24.

Unselected storage element 450 is when writing 1 operation, as shown in Figure 69 C-69P.Wherein, unselected storage Memory cell 450b, shares identical WL electrode 70a and BL electrode 74a, but does not shares same with selected storage element 450a SL electrode 72, as shown in Figure 69 C-69D.Wherein, unselected storage element 450c, shares identical SL electrode 72b and BL Electrode 74a, but do not share same WL electrode 70, as shown in Figure 69 E-69F with selected storage element 450a.Wherein, not by Selected storage element 450d, shares identical WL electrode 70a and SL electrode 72b, but not with selected storage element 450a Share same BL electrode 74, as shown in Figure 69 G-69H.In Figure 69 I-69J, unselected storage element 450e biases feelings Condition is as it can be seen, 450e and selected storage element 450a shares same WL electrode 70a, but does not share SL electrode 72 and BL electricity Pole 74.In Figure 69 K-69L, bias condition on unselected storage element 450f is as it can be seen, 450f and selected storage Unit 450a shares same SL electrode 72b, but does not share WL electrode 70 and BL electrode 74.All with chosen storage element Share the bias condition of the storage element of identical BL electrode 74a, as shown in Figure 69 M-69N, do not share identical WL electrode 70 He SL electrode 72 (e.g., storage element 450g)；The most all and selected storage element 450a does not share any WL, SL and BL electrode 70,72,74 (e.g., storage element 450h) are as shown in Figure 69 O-69P.

The current potential (sharing identical WL electrode 70 with selected storage element) of buoyancy aid 24 will be because of the electricity with WL electrode 70 Hold coupling, and raise V_FB.For having the storage element of logical zero state, the rising of buoyancy aid 24 current potential will not p-n bis-pole the most at last Pipe forward bias (diode is made up of buoyancy aid 24), and tie 16 and will remove the hole in buoyancy aid 24.Therefore, the current potential of buoyancy aid 24 Will be returned to initial logical zero equilibrium potential." for being in the storage element of logic 1 state, the current potential of buoyancy aid 24 will raise immediately V_FB, cause hole to be shifted from buoyancy aid 24.After the positive bias removed on WL electrode 70, the current potential of buoyancy aid 24 will decline V_FB。 If the initial potential of buoyancy aid 24 (logic state 1) is V_FB1, then, after the operation of write logical zero, the current potential of buoyancy aid 24 will become V_FB1-V_FB.Therefore, WL current potential needs to be optimized so that the floating body potential in storage element 50 will not be too under logic 1 state High.Such as, owing to coupling with WL, the maximum potential of buoyancy aid raises not over V_FB1/2。

As shown in Figure 69 C-69D, unselected storage element 450b, shares identical WL electricity with selected storage element Pole 70a and BL electrode 74a, but do not share SL electrode 72, apply a volt bias to BL electrode, simultaneously by SL electrode forward bias Put.Voltage difference (i.e. the emitter and collector of dipole elements 30) between BL and SL electrode, is greater than storage element and is protecting Hold state purgation voltage difference.Therefore, (p-n diode is by buoyancy aid 24 and bit line region 16 structure for the forward bias current of p-n diode Become) will be supplemented by the base current (bigger) of dipole elements 30.Therefore, storage element 450b will be in holding mould all the time Formula.Therefore, when storage element 450b is in logic 1 state, it will keep the electric charge in buoyancy aid 24, because intrinsic bipolar assembly 30 will produce hole current, supplement the electric charge in buoyancy aid 24, simultaneously when storage element 450b is in logical zero state, Dipole elements 30 will be closed so that the electric charge of buoyancy aid 24 keeps neutrality.

As shown in Figure 69 E-69F, unselected storage element 450c shares SL electrode with selected storage element 450a 72b and BL electrode 74A, but do not share WL electrode 70, SL electrode 72 ground connection simultaneously, BL electrode negative bias.So, buoyancy aid 24 it is positioned at With the p-n diode between bit line region 16 will forward bias.For logic state 0 purgation storage element, raise buoyancy aid 24 Current potential can't change initial logical zero state, because during hole is not stored in buoyancy aid 24.For logic 1 state it Storage element, net effect is exactly that the current potential of buoyancy aid 24 will decline after write 0 operation.Therefore, BL current potential needs to carry out excellent Change so that the floating body potential in storage element 50 will not be the highest under logic 1 state.Such as, applying-V on BL electrode 74_FB1/ 2.For being in the storage element of logical zero state, dipole elements 30 will remain turned-off so that unit keeps logical zero state.

As shown in Figure 69 G and 69H, storage element 450d shares identical WL electrode with chosen storage element 450a 70a and SL electrode 72b, but do not share BL electrode 74, the now equal ground connection of SL electrode 72 and BL electrode 74.Accordingly, because at n-p-n Do not have voltage difference, storage element 450d will not be constantly in hold mode between the emitter and collector of dipole elements 30.Separately Outward, owing to write operation completes comparatively fast (nanosecond), compared with the life-span (Millisecond) of electric charge in buoyancy aid 24, be will not be to buoyancy aid The electric charge of middle storage causes many large disturbances.

As shown in Figure 69 I-69J, share identical for chosen storage element 450e with chosen storage element 450a WL electrode 70a and SL electrode 72, but do not share BL electrode 74.It will be seen that these storage elements 450e is in holding pattern, Storage element be in logic 1 state it, the electric charge in buoyancy aid 24 can be kept, because intrinsic n-p-n dipole elements 30 can produce sky Cave electric current, with the electric charge in supplementary buoyancy aid 24；The storage element being simultaneously in logical zero state will keep neutral state.

As shown in Figure 69 K and 69L, storage element 450f shares identical SL electrode with chosen storage element 450f 72b, but do not share BL electrode 74 and WL electrode 70.Accordingly, because between the emitter and collector of n-p-n dipole elements 30 Do not have voltage difference, storage element 450f will not be constantly in hold mode.Further, since write operation completes comparatively fast (nanosecond), Compared with the life-span (Millisecond) of electric charge in buoyancy aid 24, be will not cause many large disturbances to the electric charge of storage in buoyancy aid.

As shown in Figure 69 M-69N, share identical for chosen storage element 450g with chosen storage element 450a BL electrode 74a, and do not share WL electrode 70 and SL electrode 72；Now on BL electrode applying be back bias voltage, and SL electrode protect Hold positive bias.Voltage difference (i.e. the emitter and collector of dipole elements 30) between BL and SL electrode, is greater than storage single Unit's voltage difference in the hold state.Therefore, (p-n diode is by buoyancy aid 24 and bitline regions for the forward bias current of p-n diode Territory 16 is constituted) will be supplemented by the base current (bigger) of dipole elements 30.Therefore, storage element 450g will be in guarantor all the time Hold pattern.The storage element being in logic state 1 will keep the electric charge in buoyancy aid 24, because intrinsic bipolar assembly 30 will produce sky Cave electric current, the electric charge in the reddest buoyancy aid 24, the unit being simultaneously in logical zero state will keep neutral state.

As shown in Figure 69 O and 69P, storage element 450h does not share any WL, BL and SL with selected storage element 450a Electrode 70,74,72, SL electrode 72 will keep positive electricity, BL electrode maintained at ground simultaneously.It will be seen that these storage elements are in Holding pattern, storage element be in logic 1 state it, the electric charge in buoyancy aid 24 can be kept, because intrinsic n-p-n dipole elements 30 Hole current can be produced, with the electric charge in supplementary buoyancy aid 24；It is simultaneously in the storage element of logical zero state by character in holding State.

This invention can also be listed the example of dissimilar write logical zero operation.Above-mentioned electric pressure is to be shown Example use, can select according to technology node or design, the meaning of indefinite.

Logical zero can also be entered by ionization by collision described above in the enterprising row write of storage element 450 to operate, such as, root According to quoting document Lin, or by band, band can also be worn effect (door induction leakage current or GIDL) then and realize, see citation Offer Yoshida.

Figure 70 illustrates, at band, band is worn then the storage selected in storage arrays 480 in (GIDL) write logic-1 operating process The bias condition example of memory cell 450a.As previously discussed, with reference to the way of Jitian, selected representative storage element On the WL electrode 70a of 450a applying negative-grid bias and on BL electrode 74a the positive gate bias of applying cause the storage element selected The buoyancy aid 24 of 450 occurs that hole is injected.In write logic-1 operating process, SL electrode 72 and underlayer electrode 78 can be grounded.

Being further elucidated with in Figure 71 A and 71B, in specific non-limiting example, to selecting it Storage element 450a applies following bias condition: on SL electrode 72b, apply the current potential of about 0.0 volt, to BL electrode 74a The current potential that upper applying is about+1.2 volts, applies the current potential of about-1.2 volts and to underlayer electrode 78 (figure on WL electrode 70a 71B does not shows) the upper current potential applying about 0.0 volt.This bias condition makes it possible to band and is bent upwards and (leans on to bitline regions 16 Nearly selected representative storage element 450a) part, at bit line (electronics) upper generation GIDL electric current.Simultaneously on buoyancy aid 24 Occur that hole is injected, charge for it, until logic-1 level.

Figure 70 also illustrates the bias condition being applied on unselected electrode, and Details as Follows: to unselected SL electrode Apply the voltage of about+1.2 volts on 72a and 72c (not showing) to 72n+1, apply to unselected BL electrode 74b to 74p The voltage of about+0.0 volt, applies the voltage of about+0.0 volt and to substrate electricity to unselected WL electrode 70b to 70n+1 Pole 78a to 78n+1 applies the voltage of about+0.0 volt.

In write logic 1 operating process unselected storage element see Figure 71 C to 71O: storage element 450b (with selected it Storage element 450a shares same WL electrode 70a and BL electrode 74a, but does not share same SL electrode 72) bias strip Part is as shown in Figure 71 C to 71D.Storage element 450c (shares same SL electrode 72b and BL electricity with selected storage element 450a Pole 74a, but do not share same WL electrode 70) bias condition as shown in Figure 71 E to 71F.Storage element 450d is (with selected Storage element 450a share same WL electrode 70a and SL electrode 72b, but do not share same BL electrode 74) bias Condition is as shown in Figure 71 G to 71H.Storage element 450e (share same WL electrode 70a with selected storage element 450a, but Do not share same SL electrode 72, the most do not share same BL electrode 74) bias condition as shown in Figure 71 I to 71J.Store Unit 450f (shares same SL electrode 72b with selected storage element 450a, but does not share same WL electrode 70, also Do not share same BL electrode 74) bias condition as shown in Figure 71 K to 71L.Storage element is (with selected storage element 450a Share same BL electrode 74a, but do not share same WL electrode 70, the most do not share same SL electrode 72), as single in stored The bias condition of unit 450g is as shown in Figure 71 M to 71N.And storage element (does not share WL, SL with selected storage element 450a With BL electrode 70,72 and 74), if the bias condition of storage element 450h is as shown in Figure 71 O to 71P.

As shown in Figure 71 C to 71D, (single with selected storage for unselected representative storage element 450b Unit 450a shares same WL electrode 70a and BL electrode 74a, but does not share same SL electrode 72) for, BL and SL electrode It is forward bias.Therefore, between the emitter and collector end of n-p-n bipolar device 30, there is not electric potential difference, thus Storage element 450b is no longer in hold mode.But, compared with the charge life of buoyancy aid 24 (several milliseconds), write operation The time completed is generally shorter (several nanoseconds).Therefore, hardly the electric charge being stored in buoyancy aid is interfered.

As shown in Figure 71 E to 71F, (single with selected storage for unselected representative storage element 450c Unit 450a shares same SL electrode 72b and BL electrode 74a, but does not share same WL electrode 70) for, SL electrode 72 is existing Being grounded, BL electrode is forward bias.Therefore, storage element 450c will be in hold mode, and in state logic-1 it Storage element will keep the electric charge in buoyancy aid 24, and reason is that intrinsic bipolar device 30 can produce holding electric current, supplement buoyancy aid Electric charge in 24；Additionally the storage element in state logic 0 can be maintained at neutral state.

As shown in Figure 71 G to 71H, (single with selected storage for unselected representative storage element 450d Unit 450a shares same WL electrode 70a and SL electrode 72b, but does not share same BL electrode 74) for, SL electrode 72 He BL electrode 74 is grounded now.Therefore, between the emitter and collector end of n-p-n bipolar device 30, there is not electromotive force Difference, thus storage element 450d is not also in hold mode.But, compared with the charge life of buoyancy aid 24 (several milliseconds), write Enter time that operation completes generally shorter (several nanoseconds).Therefore, hardly the electric charge being stored in buoyancy aid is caused Interference.

As shown in Figure 71 I to 71J, (single with selected storage for unselected representative storage element 450e Unit 450a shares same WL electrode 70a, but does not share same SL electrode 72, does not the most share BL electrode 74) for, SL electricity Pole keeps forward bias.Therefore, storage element 450e will be still in hold mode, and storage element in state logic-1 will be protected Holding the electric charge in buoyancy aid 24, reason is that intrinsic bipolar device 30 can produce holding electric current, supplements the electric charge in buoyancy aid 24；Separately Storage element in outer state logic 0 can be maintained at neutral state.

As shown in Figure 71 K to 71L, (single with selected storage for unselected representative storage element 450f Unit 450a shares same SL electrode 72b and WL electrode 70, but does not share same BL electrode 74) for, SL electrode 72 He BL electrode 74 is grounded now.Therefore, between the emitter and collector end of n-p-n bipolar device 30, there is not electromotive force Difference, thus storage element 450f is no longer in hold mode.But, compared with the charge life of buoyancy aid 24 (several milliseconds), The time that write operation completes is generally shorter (several nanoseconds).Therefore, hardly the electric charge being stored in buoyancy aid is made Become interference.

As shown in Figure 71 M to 71N, (single with selected storage for unselected representative storage element 450g Unit 450a shares same BL electrode 74a, but does not share same WL electrode 70, does not the most share SL electrode 72) for, BL electricity Pole and SL electrode are applied in forward bias.Therefore, do not exist between the emitter and collector end of n-p-n bipolar device 30 Electric potential difference, thus storage element 450g is no longer in hold mode.But, compared with charge life (the about number milli of buoyancy aid 24 Second), the time that write operation completes is generally shorter (several nanoseconds).Therefore, hardly to the electricity being stored in buoyancy aid Lotus interferes.

As shown in Figure 71 O to 71P, (single with selected storage for unselected representative storage element 450h WL, BL and SL electrode 70,74 and 72 is not shared by unit) for, SL electrode 72n+1 will keep positively charged, BL electrode 74b and WL Electrode 70n is grounded.It will be seen that storage element 450h will be in hold mode, and the storage in state logic-1 is single Unit will keep the electric charge in buoyancy aid 24, and reason is that intrinsic bipolar device 30 can produce holding electric current, supplement in buoyancy aid 24 it Electric charge；Additionally the storage element in state logic 0 can be maintained at neutral state.

Figure 72 illustrates storage element selected in storage arrays 480 in ionization by collision write logic-1 operating process The bias condition example of 450a.As previously discussed, with reference to the way of woods cited above, selected representative storage is single In the positive gate bias of the upper applying of WL electrode 70a of unit 450a and BL electrode 74a, the positive gate bias of applying cause the storage selected singly The buoyancy aid 24 of unit 450 occurs that hole is injected.In write logic-1 operating process, SL electrode 72b and underlayer electrode 78a to 78n+ 1 can be grounded.

Being further elucidated with in Figure 72, in specific non-limiting example, single to selected storage Unit 450a applies following bias condition: on SL electrode 72b, apply the current potential of about 0.0 volt, apply on BL electrode 74a The current potential of about+1.2 volts, applies the current potential of about+1.2 volts and to underlayer electrode 78a to 78n+1 on WL electrode 70a The current potential that upper applying is about 0.0 volt.As previously discussed, with reference to the way of woods cited above, due to ionization by collision mechanism Effect, this bias condition can cause selected representative storage element 450a to start to conduct electric current.At word On line electrode, it+1.2V electric current connects representative storage element with the association of it+1.2V electric current in bit line electrode 74a Bipolar device 30 (unrelated with the logic state before self) in 450a, and in buoyancy aid 24, produce enough hole electricity Lotus so that it is be in logic 1 state.

Figure 72 also illustrates the bias condition being applied on unselected electrode, and Details as Follows: to unselected SL electrode Apply the current potential of about+1.2 volts on 72a and 72c (not showing) to 72n+1, apply to unselected BL electrode 74b to 74p The current potential of about+0.0 volt, applies the current potential of about+0.0 volt and to substrate electricity to unselected WL electrode 70b to 70n+1 Pole 78a to 78n+1 applies the current potential of about+0.0 volt.

(with selected storage element 450a, same WL is shared for unselected representative storage element 450b Electrode 70a and BL electrode 74a, but do not share same SL electrode 72) for, BL and SL electrode is forward bias.Therefore, Between the emitter and collector end of n-p-n bipolar device 30, there is not electric potential difference, thus storage element 450b is the most no longer It is in hold mode.But, compared with the charge life of buoyancy aid 24 (several milliseconds), the time that write operation completes is the shortest (several nanoseconds).Therefore, hardly the electric charge being stored in buoyancy aid is interfered.

(with selected storage element 450a, same SL is shared for unselected representative storage element 450c Electrode 72b and BL electrode 74a, but do not share same WL electrode 70) for, SL electrode 72b is grounded the most, BL electrode For forward bias.Therefore, storage element 450c will be in hold mode, and the storage element in state logic 1 will keep buoyancy aid Electric charge in 24, reason is that intrinsic bipolar device 30 can produce holding electric current, supplements the electric charge in buoyancy aid 24；Additionally state Storage element in logical zero can be maintained at neutral state.

(with selected storage element 450a, same WL is shared for unselected representative storage element 450d Electrode 70a and SL electrode 72b, but do not share same BL electrode 74) for, SL electrode 72 and BL electrode 74 is connect now Ground.Therefore, between the emitter and collector end of n-p-n bipolar device 30, there is not electric potential difference, thus storage element 450d is not also in hold mode.But, compared with the charge life of buoyancy aid 24 (several milliseconds), the time that write operation completes Generally shorter (several nanoseconds).Therefore, hardly the electric charge being stored in buoyancy aid is interfered.

(with selected storage element 450a, same WL is shared for unselected representative storage element 450e Electrode 70a, but do not share same SL electrode 72, the most do not share BL electrode 74) for, SL electrode keeps forward bias.Cause This, storage element 450e will be still in hold mode, and storage element in state logic-1 will keep the electric charge in buoyancy aid 24, Reason is that intrinsic bipolar device 30 can produce holding electric current, supplements the electric charge in buoyancy aid 24；The additionally storage in state logic 0 Memory cell can be maintained at neutral state.In this case, storage element 450e is it is possible that write interference problem, for this Individual problem we will hereinafter discuss in detail together with Figure 73 A to 73B.

(with selected storage element 450a, same SL is shared for unselected representative storage element 450f Electrode 72b, but do not share same WL electrode 70, the most do not share same BL electrode 74) for, SL electrode 72 and BL electrode 74 are grounded now.Therefore, between the emitter and collector end of n-p-n bipolar device 30, there is not electric potential difference, because of And storage element 450f is no longer in hold mode.But, compared with the charge life of buoyancy aid 24 (several milliseconds), write behaviour The time made is generally shorter (several nanoseconds).Therefore, hardly the electric charge being stored in buoyancy aid is interfered.

(with selected storage element 450a, same BL is shared for unselected representative storage element 450g Electrode 74a, but do not share same WL electrode 70, the most do not share SL electrode 72) for, BL electrode 74a and SL electrode 72n+1 It is applied in forward bias.Therefore, between the emitter and collector end of n-p-n bipolar device 30, there is not electric potential difference, because of And storage element 450g is no longer in hold mode.But, compared with the charge life of buoyancy aid 24 (several milliseconds), write behaviour The time made is generally shorter (several nanoseconds).Therefore, hardly the electric charge being stored in buoyancy aid is interfered.

For unselected representative storage element 450h (with selected storage element do not share WL, BL and SL electrode 70,74 and 72) for, SL electrode 72n+1 will keep positively charged, and BL electrode 74b and WL electrode 70n is grounded.I It will be seen that storage element 450h will be in hold mode, and the storage element in state logic-1 will keep in buoyancy aid 24 Electric charge, reason is that intrinsic bipolar device 30 can produce holding electric current, supplements the electric charge in buoyancy aid 24；Additionally state logic Storage element in 0 can be maintained at neutral state.

The storage element 450e representative under the bias condition shown in Figure 72 of Figure 73 A and Figure 73 B show is partially Press strip part.Storage element 450e and text line electrode 70a (biasing under+1.2V), bit line electrode 74b (biasing under+0.0V) It is coupled with source line electrode 72a (biasing under+1.2V).Merit attention is, floater area 24 quilt of storage element 450e The capacitive couplings of bit line 70a is promoted, although thus the bias of generation 1.2 volts therein has generation at selected Otherwise the storage element 450a of table exists electromotive force mutually.If bipolar device 30 will be switched under these conditions, write Disturbed condition (writing unnecessary logic-1 in unselected storage element) it would appear that, cause logic-1 to be written into not In chosen storage element 450e.

One of them method solving to write in representative storage element 450e interference is exactly: store single in design During unit 450, it is to be ensured that when using the known method in this technology, source line electrode 72 produces when being in forward bias condition The efficiency of the ionization by collision of raw charge carrier produces the collision electricity of charge carrier when being in forward bias condition than bit line electrode 74 From efficiency low.The most just create enough electric currents, representative storage element 450e can be made to be in holding State, and produce higher electric current, enough by logic-1 write storage element 450a.

Or, the bias condition of one group of difference as shown in figure 37, can be used.Figure 37 illustrates use ionization by collision and will patrol Collect the another one example of storage element 450a selected in-1 write storage arrays 480.As previously discussed, with reference to drawing above With the way of woods, the positive grid of applying on the WL electrode 70a of the selected representative storage element 450a shown in Figure 72 On bias and BL electrode 74a, the positive gate bias of applying cause the buoyancy aid 24 of the storage element 450 selected to occur that hole is injected.Writing Entering in logic-1 operating process, SL electrode 72b and underlayer electrode 78a to 78n+1 can be grounded.This write logic-1 operation in it Difference is unselected bit line 74b to 74p and unselected source line 72a and 72c (in unlimited time) to the bias condition of 72n+1

Being further elucidated with in Figure 74, in specific non-limiting example, single to selected storage Unit 450a applies following bias condition: on SL electrode 72b, apply the voltage of about 0.0 volt, apply on BL electrode 74a The voltage of about+1.2 volts, applies the voltage of about+1.2 volts and to underlayer electrode 78a to 78n+1 on WL electrode 70a The voltage that upper applying is about 0.0 volt.As previously discussed, with reference to the way of woods cited above, due to ionization by collision mechanism Effect, this bias condition can cause selected representative storage element 450a to start to conduct electric current.At word On line electrode, it+1.2V electric current connects representative storage element with the association of it+1.2V electric current in bit line electrode 74a Bipolar device 30 (unrelated with the logic state before self) in 450a, and in buoyancy aid 24, produce enough hole electricity Lotus so that it is be in logic 1 state.

Figure 74 also illustrates the bias condition being applied on unselected electrode, and Details as Follows: to unselected SL electrode Apply the current potential of about+0.6 volt on 72a and 72c (not showing) to 72n+1, apply to unselected BL electrode 74b to 74p The current potential of about+0.6 volt, applies the current potential of about+0.0 volt and to substrate electricity to unselected WL electrode 70b to 70n+1 Pole 78a to 78n+1 applies the current potential of about+0.0 volt.

(with selected storage element 450a, same WL is shared for unselected representative storage element 450b Electrode 70a and BL electrode 74a, but do not share same SL electrode 72) for, BL and SL electrode is forward bias, applies Bias on BL is higher than the bias being applied on SL.Therefore, bipolar device 30 is switched on, and storage element 450b will be in guarantor Holding state, and the storage element in state logic-1 will keep the electric charge in buoyancy aid 24, reason is intrinsic bipolar device 30 Holding electric current can be produced, supplement the electric charge in buoyancy aid 24；Additionally the storage element in state logic 0 can be maintained at neutral state.

(with selected storage element 450a, same SL is shared for unselected representative storage element 450c Electrode 72b and BL electrode 74a, but do not share same WL electrode 70) for, SL electrode 72b is grounded the most, BL electrode For forward bias.Therefore, storage element 450c will be in hold mode, and the storage element in state logic-1 will keep buoyancy aid Electric charge in 24, reason is that intrinsic bipolar device 30 can produce holding electric current, supplements the electric charge in buoyancy aid 24；Additionally state Storage element in logical zero can be maintained at neutral state.

(with selected storage element 450a, same WL is shared for unselected representative storage element 450d Electrode 70a and SL electrode 72b, but do not share same BL electrode 74) for, SL electrode 72b is grounded the most, BL electrode There is slight forward bias in 74b.Therefore, storage element 450d will be in hold mode, and the storage element in state logic 1 To keep the electric charge in buoyancy aid 24, reason is that intrinsic bipolar device 30 can produce holding electric current, supplements the electricity in buoyancy aid 24 Lotus；Additionally the storage element in state logic 0 can be maintained at neutral state.

(with selected storage element 450a, same WL is shared for unselected representative storage element 450e Electrode 70a, but do not share same SL electrode 72, the most do not share BL electrode 74) for, SL electrode 72a and BL electrode 74b is equal Slight forward bias occurs.Therefore, between the emitter and collector end of n-p-n bipolar device 30, there is not electromotive force Difference, thus storage element 450e is no longer in hold mode.But, compared with the charge life of buoyancy aid 24 (several milliseconds), The time that write operation completes is generally shorter (several nanoseconds).Therefore, hardly the electric charge being stored in buoyancy aid is made Become interference.This also eliminates the need for having the representative storage element 450e of bias condition in shown in Figure 35,36A and 36B Potential write interference.

(with selected storage element 450a, same SL is shared for unselected representative storage element 450f Electrode 70b, but do not share same WL electrode 70, the most do not share BL electrode 74) for, SL electrode 72b is grounded, BL electrode There is slight forward bias in 74b.Therefore, storage element 450f will be in hold mode, and the storage in state logic-1 is single Unit will keep the electric charge in buoyancy aid 24, and reason is that intrinsic bipolar device 30 can produce holding electric current, supplement in buoyancy aid 24 it Electric charge；Additionally the storage element in state logic 0 can be maintained at neutral state.

(with selected storage element 450a, same BL is shared for unselected representative storage element 450g Electrode 74a, but do not share same WL electrode 70, does not the most share SL electrode 72) for, BL electrode 74a is applied in just It is applied in forward bias to biasing SL electrode 72n+1 to be less than.Therefore, storage element 450g will be in hold mode, and state Storage element in logic 1 will keep the electric charge in buoyancy aid 24, and reason is that intrinsic bipolar device 30 can produce holding electric current, Supplement the electric charge in buoyancy aid 24；Additionally the storage element in state logic 0 can be maintained at neutral state.

For unselected representative storage element 450h (with selected storage element do not share WL, BL and SL electrode 70,74 and 72) for, SL electrode 72n+1 and BL electrode 74b will appear from slight forward bias, and WL electrode 70n quilt Ground connection.Therefore, between the emitter and collector end of n-p-n bipolar device 30, there is not electric potential difference, thus storage element 450e is no longer in hold mode.But, compared with the charge life of buoyancy aid 24 (several milliseconds), when write operation completes Between generally shorter (several nanoseconds).Therefore, hardly the electric charge being stored in buoyancy aid is interfered.

We are with regard to the structure of difference of the representative storage arrays 480 being made up of multiple storage elements 450 It is discussed with operational approach.A lot of other examples may be also in the research range of the present invention.Such as, the first conductive-type The region of type can change N-shaped into from p-type, and the region of the second conduction type can change p-type into from N-shaped, and polarity phase is taked in the operation of difference Otherwise bias.Bias level itself is served only for demonstration, and along with the difference of design alternative, the bias level of different instances is the most different. Storage arrays 480 can be changed, in order to same source line 72 is shared in outside trip with adjacent trip, and uses special text line 70.The technical staff of this area can also remember a lot of other examples easily.Therefore, except additional claims Outward, the present invention limiting never in any form.

Merit attention is to use the storage element of the fin structure 52 or 52A structure of displaying in Figure 56 to 58B can be used for Replacing the storage element 450 in storage arrays 480, band shares text line or without shared source line, and to be similar to storage element The mode of 450 plays a role.Storage element 450 can also be carried out a lot of other changes.Such as, can be at storage element 450 Or the first conduction type and the second conduction type are exchanged by storage element 250V, the relative polarity of applied voltage is also carried out mutually Change.Above-mentioned all voltage levels are served only for demonstration, and along with the difference of design alternative, the bias level of different instances is the most different. Therefore, the present invention limiting never in any form.

Figure 75 A illustrates the another one example of internal memory part 450.Wherein by insulating barrier 28 adjacent area 16 separately by Contact 64 is shared one with BL electrode 74 and is connected.It is connected by sharing one with BL electrode 74, due to each two storage element 450 Have only to a contact, the compactest available storage element.

Figure 75 B show another one example of storage element 450.Wherein between adjacent storage element 450 now Not share bit lines region 16 and contact 64.Insulating regions 33 and bit line region 16 by the second conduction type can realize first The insulation in adjacent buoyancy aid 24 region of conduction type.

Figure 76 A to 76O illustrates the manufacture method of the storage element 450 of displaying in Figure 75 B.This method part uses more Change insulator technology (S_Kim and Oh discussed as discussed above) and produce insulating regions 33.

With reference to Figure 76 A to 76AA, the method for the manufacture storage element 450 shown in Figure 75 B will be described in detail.These are 27 years old Width figure is one group with three relevant views and arranges.Often the first width figure of group is top view, and often the second width figure of group is this group The vertical cross section (named I-I ') of the first width figure top view, often the 3rd width figure of group is the level of this group the first width figure top view Section (named II-II ').Therefore, Figure 76 A, 76D, 76G, 76J, 76M, 76P, 76S, 76V and 76Y is in the fabrication process A series of top views of the storage element 450 in each stage, and Figure 76 B, 76E, 76H, 76K, 76N, 76Q, 76T, 76W and 76Z Respective vertical cross section (named I-I '), Figure 76 C, 76F, 76I, 76L, 76O, 76R, 76U, 76X and 76AA be respective it Horizontal section (named II-II ').Neutralize relatively early figure as discussed above and describe simultaneously, it occurs in Figure 76 A to 76AA Relatively early in figure the identical reference number of uses represent be similar to it, the identical or structure of simulation.Here, " vertically " refer to Direction from top to bottom on the page of top view, and " level " refers on the page of top view from the left and direction on the right side.In storage In the instantiation of memory cell 450, for the surface of semiconductor device, two cross sections be " level " it.

As shown in Figure 76 A to 76C, grow on the substrate 12 a very thin conduction region 202 (the most representative it 300A in 130nm technique, although the process technology that can take along with example of this conduction region and the difference of geometry and become Change).Conduction region 202 takes the material different from substrate zone 12 to make, in order to optionally can be etched it subsequently, and Substrate 12 will not be also carried out unnecessary etching simultaneously.Such as, the material of conduction region 202 can take SiGe (SiGe), and serves as a contrast The end 12, can use silicon.

As shown in Figure 76 D to 76F, photoetching process can be taked to form the pattern of conduction region 202.Subsequently, 202 layers are lost Carve, be next exactly grown of another conduction region 204.For example, in representative 130nm technique, conduction The thickness in district 204 is about 500A.The material identical with substrate 12 can be taked in conduction region 204, such as, can use silicon.Next Can be planarized, to guarantee to obtain plane.The structure finally given is as shown in Figure 76 D to 76F.

As shown in Figure 76 G to 76H, groove forming technology to be carried out, its sequence of steps and the institute of Figure 36 G to 36H The order shown is similar to, and is namely initially formed silicon dioxide layer 220, polysilicon layer 222 and silicon nitride layer 224, passes through It is lithographically formed pattern, is finally etching process.The degree of depth of its degree of depth groove to be exceeded 208 is guaranteed when etching groove 216.Example As, in representative 130nm technique, the degree of depth of groove 208 is about 1200A, and the degree of depth of groove 216 is about 1600A.The structure finally given is as shown in Figure 76 G to 76I.

As shown in Figure 76 J to 76L, next to carry out is silicon oxidation step, namely at groove 208 and groove 216 Middle silicon dioxide thin film growth.Such as, in representative 130nm technique, the silicon dioxide of 4000A can be grown.Connect down Carry out chemical-mechanical polishing step to be carried out, the silica membrane finally given is polished, it is ensured that silicon dioxide layer is relative For silicon face be smooth it.In representative 130nm technique, to carry out subsequently is silicon dry etching, it is ensured that From silicon face amount, the height of remaining silicon dioxide layer is about 300A.Following removable silicon nitride layer 224 and polysilicon Layer 222, then carries out wet etching, to remove silicon dioxide layer 220 (and in groove 208 above and groove 216 region shape The part of silica thin film of one-tenth).Figure 76 J to 76L illustrates the insulating barrier 26 and 28 taking these steps to be formed.

As shown in Figure 76 M to 76O, followed by oxide etching, oxide region 26 and 28 is made to fall in (the most recessed About 1000A), and make conduction region 202 come out.Followed by wet etching process, in order to remove region selectively 202, the ledge in region 204 is formed below gap 203.The structure such as Figure 76 M to 76O finally given by these steps Shown in.

As shown in Figure 76 P to 76R, next the interstitial area 203 finally given is aoxidized, to form buried oxide District 33.Insulation layer 26 is stashed along substrate 12 surface, so can be easy to close, 202 regions are etched, between formation Gap district 203；Next in gap 203, carry out oxide growth, form buried oxide district 33.The ledge in region 204 Limit oxide growth in interstitial area 203, prevent buried oxide district 33 to superficial growth.The structure finally given is such as Shown in Figure 76 P to 76R.

As shown in Figure 76 S to 76U, followed by the oxide deposition of about 1000A, then it is planarized journey Sequence.Implement ion implanting step subsequently, form buried wellblock 22.Ion implantation energy is optimized, it is ensured that formed is buried Floor district 22 is more shallow than the bottom of insulating barrier 26.Therefore, insulating barrier 26 makes buried layer district 22 and the insulation of neighbouring storage element.Another Aspect, the formation insulating barrier to be guaranteed 28 and 33 in buried layer district 22 will not insulate with buried layer district 22 so that buried layer district 22 exists Keep successively on II-II ' hatching direction.The structure finally given by these steps is as shown in Figure 76 S to 76U.

As shown in Figure 76 V to 76X, next can at silicon face (such as, in representative 130nm technique about For 100A) on form silicon dioxide layer (or high-k material) 62, carry out polysilicon (or metal) door 60 subsequently and deposit (in representative 130nm technique, being about 500A).Followed by lithographic procedures, to form the figure of door and text line Case；In the place not lost color, polysilicon layer and silicon dioxide layer are etched subsequently.The structure finally given such as Figure 76 V To shown in 76X.

As shown in Figure 76 Y to 76AA, implement primary ions implantation step the most again, to form the second conduction type (i.e. n Type conduct) bitline regions 16.Door 60 and insulating barrier 26 and 28 play the effect of masking layer in ion implantation process, so The region of the second conduction type would not be formed outside bitline regions 16.To carry out subsequently is backend process, to form contact And metal level.

Figure 77 A to 77F illustrates an example without door half field transistor storage element.According to current invention, store Unit 550 thus can be able to obtain more not in use by the gate electrode of existence in early stage storage element (such as storage element 250) Compact layout, reason is that the size of minimum unit no longer will be caused shadow by some design rule (such as door-contact spacing) Ring.

Figure 77 A to 77F illustrates the buried layer 22, second of substrate 12, second conduction type of the first conduction type and conducts electricity The region 20 of bitline regions 16, second conduction type of type, the region 21 of the first conduction type, buried layer district 22, first conduct electricity The buoyancy aid 24 of type, insulation layer 26 and 28, source line electrode 72 and underlayer electrode 78.The function of storage element 550 with begged for above Function in the example storage element 250 of opinion is similar to.Storage element 550 discussed above and the Main Differences of storage element 250 It is not use door 60 and door insulator 62.In another one example, in storage element 550 border, semiconductor surface 14 is hidden There is not contact in buried regions 22.

The manufacture method of storage element 550 is very similar to the manufacturer of the storage element 250 shown in Figure 36 A to 36U Method.But there is some exception, that is, do not use the lithography step forming door 60, but need to use the lithography step of difference, shape Become the pattern of bitline regions 16, in order to carry out ion implanting or diffusion.

Figure 77 A illustrates the top view of storage element 550 and some close on ingredient.

Cross section shown in the top view of the single storage element 550 of Figure 77 B show and Figure 77 C and 77D is the most to hang down Straight cut line I-I ' and horizontal cut line II-II '.

Figure 77 E illustrates how its buried layer 22 is coupled to by storage element 550 by the region 20 of the second conduction type On source line electrode 72 and how by the region 21 of the first conduction type, substrate 12 is coupled on underlayer electrode 78.

The representative storage arrays 580 of Figure 77 F show.Following drawing is single to storing by this storage arrays of use The various operations of unit 550 illustrate.When storage element 550 is arranged into array, internal memory part can be produced.Storage arrays 580 is wrapped Include storage element 550a, 550b, 550c and 550d that part is representative.When selecting single storage element to operate, have The storage element 550a of representativeness represents selected storage element, and other representative storage element 550b, 550c and 550d represents various unselected storage element.These unselected storage elements and the representative storage element selected 550a shares same row, column or neither shares same a line, does not the most share same string.Equally, single file or single-row on grasp When work, representative storage element 550a will always be in the row or column selected.

And the first conduction type p-type is represented by these figures, the second conduction type N-shaped represents.Reason is above Example in, otherwise conduction type is probably.Due to the difference of design alternative in the example that some is specific, the first conduction type Becoming N-shaped, the second conduction type becomes p row.

Storage element state is represented by the electric charge in buoyancy aid 24, so can be to by buried well area 22, buoyancy aid 24 and The intrinsic n-p-n bipolar device 230 of BL bitline regions 16 formation is adjusted.If storage element 550 is deposited in body region 24 There is hole, compared with not storing the storage element 550 in hole in body region 24, the bipolar current of the first storage element 550 Higher (during read operation, i.e. flowing to the electric current of SL electrode from BL electrode).

Be stored in the positive charge in body region 24 can passage over time and reduce, reason is buoyancy aid 24, bitline regions 16 and the p-n diode leakage that formed of buried layer 22 and charge recombination.In the present invention, the unique technology of use exists In can be all in array storage element abreast carry out keep operation.

Figure 78 A illustrates complete array and keeps operating process, and Figure 78 B show single file keeps the process of operation.Can To take the mode similar with the holding of storage element 250 operation to carry out keeping operation, i.e. to back bias electrode (i.e. SL electrode 72) apply forward bias, electrode 74 and underlayer electrode 78 are carried out ground connection.If buoyancy aid 24 is positively charged, (state that is i.e. in is patrolled Collect 1), the n-p-n bipolar transistor 230 being made up of BL bitline regions 16, buoyancy aid 24 and buried wellblock 22 will be switched on.

Next a part of bipolar transistor current can flow into floating body region 24 (commonly referred to " base current ") and keep State logic 1 data.Can be by the bipolar device that buried wellblock 22, floating body region 24 and bitline regions 16 form be designed as low increasing The method of benefit type bipolar device improves the efficiency keeping operation, and bipolar gain may be defined as the current collection of outflow from SL electrode 72 Ratio between electrode current and the base current flow in floating body region 24.

For the storage element in state logic 0 data, will not turn on bipolar device, there will not be base stage subsequently Hole current flows into floating body region 24.Therefore, the storage element in state logic 0 will remain in state logic 0.

Can periodically apply positive voltage pulse to SL electrode 72, rather than apply constant forward bias, so can reduce The energy expenditure of storage element 550.

Provided hereinafter the example of the bias condition keeping operation: on BL electrode 74, apply no-voltage, to SL electrode 72 Upper applying positive voltage, and on underlayer electrode 78, apply no-voltage.In specific non-limiting example, apply to electrode 72 About+1.2 volts voltages, apply about 0.0 volt of voltage to electrode 74, and apply about 0.0 volt of voltage on electrode 78. But, along with the difference of design alternative, the voltage level of different instances is the most different.

Whole array in Figure 78 A displaying keeps in operating process, from the active line electrode of institute of 72a to 72n all at+1.2V Bias under voltage, all bias as 0.0V from all bit lines of 74a to 74p, all bias from all source electrodes of 78a to 78n and be 0.0V.The all storage elements in storage arrays 580 are thus made to be in hold mode.

Single file at Figure 78 B show keeps in operating process, and selected source line electrode 72a biases under+1.2V voltage, and From 72b (not showing), to 74n, all unselected source line electrodes all bias, from all bit lines of 74a to 74p under 0.0V voltage All bias under 0.0V voltage, all bias under 0.0V voltage from all source electrodes of 78a to 78n.Thus make storage number All storage elements in group 280 are in hold mode.

Figure 79 and Figure 80 A to 80H illustrates the read operation of single storage element.Utilize following bias condition, can be by inspection Storage element 550 is implemented read operation by the method surveying bipolar device 230 electric current: apply positive voltage on BL electrode 74, to SL Apply no-voltage on electrode 72, and on underlayer electrode 78, apply no-voltage.In keeping operating process, to selected BL electrode The positive voltage of upper applying should be less than the positive voltage of applying on SL electrode.Unselected BL electrode will keep no-voltage, unselected Fixed SL electrode will keep positive voltage.

Figure 79 illustrates storage element 550a selected in storage arrays 280 and unselected storage element 550b, 550c Bias condition with 550d.In the non-limiting example that this is specific, apply about 0.0 volt to selected SL electrode 72a Special voltage, and apply about 0.0 volt of voltage to unselected source line electrode 72b (not showing) to 72n；To selected BL electrode 74a applies about+1.2 volts voltages, and applies 0.0 volt of voltage to unselected bit line electrode 74b to 74p, and to substrate Electrode 78a to 78n applies about 0.0 volt of voltage.These voltage levels itself are served only for demonstration, the voltage level of different instances Can be different

Figure 80 A and 80B respectively show the bias condition of selected representative storage element 550a.Specific at this Non-limiting example in, apply about 0.0 volt of voltage to selected SL electrode 72a, apply to selected BL electrode 74a About+1.2 volts voltages, and apply about 0.0 volt of voltage to underlayer electrode 78 (not showing).So, due to bipolar Device 230 is disconnected, if buoyancy aid positively charged pressure, electric current will pass through intrinsic bipolar device；If buoyancy aid is not charged, the most not Have electric current to flow through.

Storage element unselected during read operation is shown in Figure 80 C to 80H.Share same with selected storage element 550a The bias condition of the storage element (i.e. storage element 550b) of a line is shown in Figure 80 C and 80D.Share with selected storage element 550a Figure 80 E and 80F is seen with the bias condition of the storage element (i.e. storage element 550c) of string.With selected storage element 550a both Do not share same a line, the most do not share and see Figure 80 G to 80H with the bias condition of the storage element (i.e. storage element 550d) of string.

As shown in Figure 80 C and 80D, storage element 550b (sharing same a line with selected storage element 550a) is come Saying, SL electrode 72a and BL electrode 74p is biased to 0.0V, and these storage elements are correspondingly not also in hold mode.So And, compared with the charge life of buoyancy aid 24 (several milliseconds), the time that read operation completes is generally shorter (several nanoseconds). Therefore, hardly the electric charge being stored in buoyancy aid is interfered.

As shown in Figure 80 E to 80F, storage element 550c (sharing same string with selected storage element 550a) is come Say, on BL electrode 74a and SL electrode 72n, apply positive voltage.Due between SL electrode 72 and BL electrode 74 (i.e. at n-p-n Between the emitter and collector end of bipolar device 230) there is not electric potential difference, do not have base current and flow into buoyancy aid 24.But, Compared with the charge life of buoyancy aid 24 (several milliseconds), the time that read operation completes is generally shorter (several nanoseconds).Cause This, interfere the electric charge being stored in buoyancy aid hardly.

As shown in Figure 80 G to 80H, for storage element 550d (neither share same a line with selected storage element 550a, The most do not share same string) for, SL electrode 72n will keep positive voltage, BL electrode 74p will keep ground connection.Representative storage Unit 550d will be in hold mode, and the storage element in state logic 1 will keep the electric charge in buoyancy aid 24, reason to be admittedly The bipolar device 230 having can produce holding electric current, supplements the electric charge in buoyancy aid 24；The additionally storage element meeting in state logic 0 It is maintained at neutral state.

Any of the above voltage bias is only used for demonstration.In each example, these voltage bias can be along with design alternative and use The difference of Technology and different.

Figure 81 illustrates single file write logical zero operation, and Figure 82 A and 82B illustrates unselected representative storage The bias condition of memory cell 550c and operation.In Figure 81, there is back bias voltage under 0.5V voltage in selected trip SL electrode 72a, And all bias as 0.0V from all unselected trip electrode SL of 72b (not showing) to 72n, equal from all BL electrodes of 74a to 74p Bias under 0.0V voltage, all bias under 0.0V voltage from all underlayer electrodes of 78a to 78n.Owing to buoyancy aid 24 is to buried The forward bias of applyings on layer 22, the storage element 550 thus making to select (the most representative storage element 550a with 550b) its bipolar device is connected, it is to avoid hole occurs in buoyancy aid 24.

Figure 82 A and 82B illustrates the operating process of unselected representative storage element 550c.At this example In, storage element 550c represents all storage elements 550 in storage arrays 280, is not in selected trip.Storage element 550c makes its SL electrode 72n bias under+1.2V voltage, and BL electrode 74a biases under 0.0V voltage, opens up in Figure 78 A and 78B The holding operation shown is corresponding.

Can be by writing for benchmark with row to the upper method applying back bias voltage of BL electrode 74 (rather than at SL electrode 72) Logical zero operates.SL electrode 72 is zero-bias or positive bias, and applies no-voltage on underlayer electrode 78.Under these conditions, All storage elements sharing same BL electrode 74 will be written into state logic 0, and the storage element of remaining the most all maintains Present situation.

As previously discussed, with reference to the way of woods cited above, can be carried out on storage element 550 by ionization by collision Write logic 1 operates.

Figure 83 and 84A to 84B illustrates and carries out writing storage element selected in logic 1 operating process by ionization by collision The bias condition example of 550a.On BL electrode 74, apply positive bias, apply on selected SL electrode 72 and underlayer electrode 78 No-voltage.In keeping operating process, on BL electrode 74, the positive bias of applying should exceed the positive electricity of applying on SL electrode 72 Pressure.It is applied to the positive bias on BL electrode should be enough to connect bipolar device 230, it is not necessary to consider number in selected storage element 550a According to original state.Thus have base stage hole current and flow to the buoyancy aid 24 of selected storage element 550a, it is filled Electricity, until logic 1 state.

In specific non-limiting example, in selected storage element 550a, apply following bias condition: Xiang Xuan Fixed SL electrode 72a applies about 0.0 volt of current potential, applies about+2.0 volts current potentials to selected BL electrode 74a, and to lining Hearth electrode 78a to 78n applies about 0.0 volt of current potential.Following bias condition is applied on unselected electrode: to SL electrode 72b (not showing) to 72n applies about+1.2 volts voltages, and applies about+0.0 volt voltage to BL electrode 74b to 74p. Figure 83 illustrates the bias condition of the storage element that selected sum is unselected in storage arrays 580.Any of the above voltage bias is only For demonstrating.In each example, these voltage bias can along with the difference of design alternative and the Technology of use the most not With.

In write logic 1 operating process, unselected storage element is shown in Figure 84 C to 84H.With selected storage element 550a Share and see Figure 84 C to 84D with the bias condition of the storage element (i.e. storage element 550b) of a line, with selected storage element 550a shares and sees Figure 84 E to 84F with the bias condition of the storage element (i.e. storage element 550c) of string, single with selected storage Unit 550a neither shares same a line, does not the most share and sees figure with the bias condition of the storage element (i.e. storage element 550d) of string 84G to 84H.

As shown in Figure 84 C and 84D, (share same with selected storage element for representative storage element 550b For OK), SL electrode 72a and BL electrode 74p is all grounded.Bipolar device 230 will be disconnected, and storage element 550b will not locate In hold mode.But, compared with the charge life of buoyancy aid 24 (several milliseconds), the time that write operation completes is the shortest (several nanoseconds).Therefore, hardly the electric charge being stored in buoyancy aid is interfered.

As shown in Figure 84 E and 84F, representative storage element 550c (is shared with selected storage element 550a Same string) for, on BL electrode 74a, the positive voltage of applying is more, and it is less to apply positive voltage on SL electrode 72n.Due to Electric potential difference (i.e. between the emitter and collector end of n-p-n bipolar device 230) between SL electrode 72 and BL electrode 74 Relatively low, the most little base current flows into buoyancy aid 24.But, compared with the charge life of buoyancy aid 24 (several milliseconds), write The time operated is generally shorter (several nanoseconds).Therefore, hardly the electric charge being stored in buoyancy aid is caused dry Disturb.

As shown in Figure 84 G to 84H, for representative storage element 550d (with selected storage element 550a neither Share same a line, the most do not share same string) for, positively charged pressure, BL electrode will be grounded by SL electrode 72.Representative storage Memory cell 550d will be in hold mode, and the storage element in state logic 1 will keep the electric charge in buoyancy aid 24, and reason is Intrinsic bipolar device 230 can produce holding electric current, supplements the electric charge in buoyancy aid 24；The additionally storage element in state logic 0 Neutral state can be maintained at.

Any of the above voltage bias is only used for demonstration.In each example, these voltage bias can be along with design alternative and use The difference of Technology and different.It addition, the first conduction type can change N-shaped into from p-type, the second conduction type can be from n Type changes p-type into, and the polarity being applied in bias may be reversed.Therefore, in addition to additional claim, the present invention is not It is restricted by any way.

The vertical stacks stack layer in the alternate conductivity region of the first conduction type and the second conduction type is in above-mentioned J_Kim side Being described in method, one of them door is capped, from two sides by surrounded for body region 24.After door is removed, permissible Obtaining the storage element more more compact than the storage element of report in J_Kim method, next we will enter in storage element 350 Row is discussed.

Figure 85 A to 85F illustrates the another one example without door half field transistor storage element.Allow bitline regions 16 complete Cover the floater area 24 in storage element 650, some design rule, the such as minimum spacing between diffusion row and insulation row (i.e. in storage element 550 distance) between 16 to 26, will no longer impact the size of storage element.Figure 85 A to 85F exhibition Show the bitline regions 16 of buried layer the 22, second conduction type of substrate 12, second conduction type of the first conduction type, second led The region 20 of electricity type, the buoyancy aid 24 of region the 21, first conduction type of the first conduction type, buried layer district 22, insulation layer 26 With 28, source line electrode 72 and underlayer electrode 78.In the function of storage element 550 and example storage element 650 discussed above Function be similar to.Differring primarily in that between storage element 650 and storage element set forth above 550, bitline regions 16 is complete Cover floater area 24 (present floater area 24 volume is less), thus obtain the compactest storage element.In another one In example, in storage element 650 border there is not contact in the buried layer 22 of semiconductor surface 14.

The manufacture method of storage element 650 is very similar to the storage element 250 and Figure 77 A shown in Figure 36 A to 36U Manufacture method to the storage element 550 shown in 77F.But have some exception, that is, according to current industry known and generally The ion implantation technology of employing, takes ion implantation technology to form bitline regions 16 on the material constituting substrate 12.Or, it is possible to To take solid-state diffusion method or epitaxial growth technology to form bitline regions 16.

Figure 85 A illustrates the top view of storage element 650 and some close on ingredient.

Cross section shown in the top view of the single storage element 650 of Figure 85 B show and Figure 85 C and 85D is the most to hang down Straight cut line I-I ' and horizontal cut line II-II '.

Figure 85 E illustrates how its buried layer 22 is coupled to by storage element 650 by the region 20 of the second conduction type On source line electrode 72 and how by the region 21 of the first conduction type, substrate 12 is coupled on underlayer electrode 78.

Figure 87 illustrates the representative storage arrays 680 being made up of multiple storage elements 650.These storage elements 650 are aligned to an array, form internal memory part.The circuit operation of storage element 650 is several with the circuit operation of storage element 550 Identical, will not be discussed further here.

We say another method operating storage element 250,350 and 450 now, i.e. utilize and are discussed above Silicon controlled rectifier (SCR) (SCR) principle, the method that refer to Widjaja.

As shown in Figure 86, inherently with P1-N2-P3-N4 silicon controlled rectifier (SCR) in storage element 250,350 and 450 (SCR) (being made up of bipolar device that is 32 and 34 of two interconnection, substrate 78 wherein plays the effect in P1 district, buried layer to device 22 effects playing N2 district, body region 24 plays the effect in P3 district, and the effect in N4 district is played in bitline regions 16.In this example, Underlayer electrode 78 plays the effect of anode, and electrode 74 plays the effect of negative electrode, and the effect of p base stage is played in body region 24, in order to Connect SCR device.If body region 24 positively charged, silicon controlled rectifier (SCR) (SCR) device (is connect by substrate, buried well, buoyancy aid and BL Head composition) will be switched on；If body region 24 is in neutral state, SCR device will be disconnected.

Can carry out keeping operation by applying following bias: on BL electrode 74, apply no-voltage, execute on WL electrode 70 Add no-voltage or negative voltage, on underlayer electrode 78, apply positive voltage, and make SL electrode 72 be maintained at floating state.At these Under part, if storage element 250 is in storage/data mode logic 1, buoyancy aid 24 positively charged pressure, the SCR device of storage element 250 Part can be switched on, thus hold mode logic one data.Owing to the voltage in buoyancy aid 24 is not real positive voltage, state is patrolled The storage element collected in 0 can be maintained at blocked state.Therefore, buoyancy aid 24 will not connect SCR device.Therefore, electric current does not flows through SCR device, these storage elements will keep these state logic 0 data.It is typically attached on underlayer electrode 78, and in main body In district 24, those storage elements 250 with positive voltage will utilize logic one data state to regenerate, and is typically attached to On underlayer electrode 78, not having those storage elements 250 of positive voltage will be maintained at blocked state in body region 24, reason exists SCR device in them will not be switched on, and therefore will not keep storing state logical zero in these storage elements.So, All storage elements 250 being typically attached on underlayer electrode will accurately be kept/regeneration, to keep its data mode. After applying a voltage on underlayer electrode 78 this process the most automatically with parallel it, non-algorithm it, efficient step starts. In specific non-limiting example, apply about 0.0 volt of voltage to electrode 74, apply about 1.0 volts to electrode 70 Voltage, and on electrode 78, apply about+0.8 volt voltage.But, these voltage levels may keep between them it It is varied from during relativeness.

As shown in Figure 87, by applying positive voltage to underlayer electrode 78, apply positive voltage to BL electrode 74 (less than to substrate The positive voltage of applying on electrode 78), apply positive voltage to WL electrode 70 and the method that makes SL electrode 72 be in floating state is carried out Read operation.If storage element 250a is in state logic 1, body region 24 has hole, silicon controlled rectifier (SCR) (SCR) Device (being made up of substrate, buried well, buoyancy aid and BL joint) will be switched on；Compared with being in state logic 0, in body region 24 The storage element 250a not having hole comes, and the storage element electric current observed now is higher (flows to BL electrode from underlayer electrode 74 74).Positive voltage is applied, with a line selected in storage element array 80 (such as, seeing Figure 87) on WL electrode 70a；And for For any unselected trip, apply negative voltage to WL electrode 70b (not showing) to 70n.By Capacitance Coupled, the negative electricity of applying Pressure reduces the electromotive force of buoyancy aid 24 in unselected row, and is disconnected the SCR device of each storage element 250 in each unselected row Part.In specific non-limiting example, apply about+0.8 volt voltage to underlayer electrode 78a to 78n, to electrode 70a (for select row) applies about+0.5 volt voltage, applies about+0.4 volt voltage to selecting bit line electrode 74a, to Unselected text line electrode 70b (not showing) applies about-1.0 volts voltages and to unselected bit line electrode 74b to 74 to 70n Apply about+0.8 volt voltage.But, these voltage levels may be varied from.

For sharing with the storage element (i.e. storage element 250b) of a line with selected storage element, BL electrode and Underlayer electrode is positive bias, and SCR is disconnected.Correspondingly these storage elements will be not at hold mode.But, compared with buoyancy aid The charge life (several milliseconds) of 24, the time that read operation completes is generally shorter (several nanoseconds).Therefore, hardly The electric charge being stored in buoyancy aid can be interfered.

For sharing with the storage element (i.e. storage element 250c) of string with selected storage element, underlayer electrode 78 keep positive bias, and BL electrode 74 is positive bias (lower than the positive bias being applied on underlayer electrode 78).It will be seen that These storage elements will be in hold mode, and the storage element in state logic-1 will keep the electric charge in buoyancy aid 24, state Storage element in logical zero is maintained at neutral state.

For neither sharing same a line with selected storage element, do not share and (i.e. store list with the storage element of string Unit 250d) for, BL electrode and underlayer electrode are positive bias, and SCR is disconnected.Correspondingly these storage elements will be not at protecting Hold state.But, compared with the charge life of buoyancy aid 24 (several milliseconds), the time that read operation completes is the shortest (about Several nanoseconds).Therefore, hardly the electric charge being stored in buoyancy aid is interfered.

With reference to Figure 88, it is (i.e. near that the silicon controlled rectifier (SCR) device of selected storage element 250a can be placed into state logic 1 Write logic 1 operates).Following bias is applied: on BL electrode 74, apply no-voltage, execute on WL electrode 70 to selected electrode Add positive voltage, on underlayer electrode 78, apply positive voltage, and make SL electrode 72 be in floating state.By Capacitance Coupled, apply Positive voltage on WL electrode 70 can increase the electromotive force of buoyancy aid 24, and produces feedback program, SCR device is connected.Once store The SCR device of unit 250 is in conduction state (being switched " on "), and SCR will be " locked "；WL electrode can be applied to Voltage on 70 is removed, and does not interferes with the " on " state of SCR device.In specific non-limiting example, to electrode 74 apply about 0.0 volt of voltage, apply about+0.5 volt voltage to electrode 70, and apply about+0.8 volt on electrode 78 Special voltage.But, as it was noted above, these voltage levels may become when keeping applying the relativeness between voltage Change.It is to say, the voltage being applied on electrode 78 is higher than the voltage being applied on electrode 74.

For sharing with the storage element (i.e. storage element 250b) of a line with selected storage element, underlayer electrode For positive bias.But, owing to BL electrode 74 is also positive bias, between underlayer electrode and BL electrode, there is not electric potential difference, SCR is broken Open.Correspondingly these storage elements will be not at hold mode.But, compared with the charge life of buoyancy aid 24 (several milliseconds), The time that write logic 1 has operated is generally shorter (several nanoseconds).Therefore, hardly to the electricity being stored in buoyancy aid Lotus interferes.

For sharing with the storage element (i.e. storage element 250c) of string with selected storage element, underlayer electrode 78 keep positive bias, and BL electrode 74 is grounded now.It will be seen that these storage elements will be in hold mode, And the storage element in state logic 1 will keep the electric charge in buoyancy aid 24, the storage element in state logic 0 is maintained at middle character State.

For neither sharing same a line with selected storage element, do not share and (i.e. store list with the storage element of string Unit 250d) for, BL electrode and underlayer electrode are positive bias, and SCR is disconnected.Correspondingly these storage elements will be not at protecting Hold state.But, compared with the charge life of buoyancy aid 24 (several milliseconds), the time that write logic 1 has operated is the shortest (several nanoseconds).Therefore, hardly the electric charge being stored in buoyancy aid is interfered.

With reference to Figure 89, the write logical zero operation of selected storage element 250a is described.By applying following bias, Silicon controlled rectifier (SCR) device is set to obturation (disconnection) state: on BL electrode 74a, apply no-voltage, on WL electrode 70a Apply positive voltage, on underlayer electrode 78, apply no-voltage, and make SL electrode 72a be in floating state.Under these conditions, cloudy Voltage difference (being determined by the voltage on underlayer electrode 78 and BL electrode 74) between pole and anode will become the least, it is impossible to will SCR device is maintained at conduction state.Therefore, the SCR device of storage element 250a will be disconnected.In specific non-limiting reality In example, apply about 0.0 volt of voltage to electrode 74, apply about+0.5 volt voltage to electrode 70, and execute on electrode 78 Add about 0.0 volt of voltage.But, as it was noted above, these voltage levels may keep relative between applying electric charge It is varied from during relation.

For sharing with the storage element (i.e. storage element 250b) of a line with selected storage element, underlayer electrode 78 are grounded, and SCR is disconnected.Correspondingly these storage elements will be not at hold mode.But, compared with the electric charge longevity of buoyancy aid 24 Life (several milliseconds), the time that write operation completes is generally shorter (several nanoseconds).Therefore, hardly to being stored in Electric charge in buoyancy aid interferes.

For sharing with the storage element (i.e. storage element 250c) of string with selected storage element, underlayer electrode 78 is positive bias, and BL electrode 74a is grounded the most.It will be seen that these storage elements will be in hold mode, and Storage element in state logic 1 will keep the electric charge in buoyancy aid 24, and the storage element in state logic 0 is maintained at middle character State.

For neither sharing same a line with selected storage element, do not share and (i.e. store list with the storage element of string Unit 250d) for, BL electrode and underlayer electrode are positive bias, and SCR is disconnected.Correspondingly these storage elements will be not at protecting Hold state.But, compared with the charge life of buoyancy aid 24 (several milliseconds), the time that write logical zero has operated is the shortest (several nanoseconds).Therefore, hardly the electric charge being stored in buoyancy aid is interfered.

We are it has been described that the example of storage element 250 and the method that uses SCR operation, other example and operation side Method is also possible to realize it.Such as, the first conduction type and the second conduction type can be overturned, make the first conduction type Becoming N-shaped, the second conduction type becomes p-type, and SCR becomes a N1-P2-N3-P4 device, and the pole of the voltage of reverse applying Property.The voltage be given in various demonstrations is served only for demonstration, and along with the difference of design alternative, the voltage level of different instances is also Different.In view of the continuity of technical term be easy to statement, substrate 12 is referred to as substrate.In other buried well, substrate 12 are probably a buried well, and in the structure similar with the structure shown in prior figures 43B, substrate 12 is likely to be again one Real substrate.Substrate 12 serves as buried well and during non-real substrate, contributes to lining required in some SCR operating process The end 12 voltage level operates.A lot of other replacement examples and method are also possible to realize it, therefore, enumerate it herein In any case example is the most restrictive.

Achieve the novel semi-conductor internal memory of charged buoyancy aid storage element.Present invention also offers and utilize the non-algorithm cycle again Raw parallel operation keeps the function of storing state.Therefore, can carry out incessantly storing operation.We further describe the present invention it Other a lot of examples.There is the people of general skill and will be considered that these examples are only used for demonstration, in order to each that the present invention is described is former Reason.By reading this explanation and studying the drawing enclosed, the people of superb skill is it is also conceivable that a lot of other example.

We have a look Figure 91 now, which show and meet one of present example storage element 750.Store single Unit 750 makes at SOI (silicon in dielectric substrate) substrate 12, uses the first conduction type (such as p-type conduction).Storage element 750 also include buried oxide layer (BOX) 22.

First region 16 using the second conduction type (such as N-shaped) is there is on substrate 12.This region is exposed to surface On 14.Second region 18 using the second conduction type is there is also on substrate 12.This region is the most also exposed on surface 14. It addition, the interval between Two Areas 18 and first region 16 is as shown in Figure 1.According to current industry known and generally adopt With ion implantation technology, the material of composition substrate 12 is taked ion implantation technology form first region 16 and second Region 18.Or, it is also possible to take solid-state diffusion method to form first region 16 and Two Areas 18.

Use the floater area 24 of the first conduction type (such as p-type electric-conducting type) by region, 14, first, surface 16 with Two Areas 18, buried oxide layer 22 and the restriction of substrate 12.Can be by taking ion to note on the material of composition substrate 12 The method entering technique forms floater area 24, or takes epitaxial growth method.Door 60 is placed between region 16 and region 18, is positioned at table Above face 14.Door 60 is insulated with surface 14 by insulating barrier 62.The material of insulating barrier 62 may select silicon dioxide and/or other it Dielectric material, such as high-k material, include but are not limited to peroxidating tantalum, titanium oxide, zirconium oxide, hafnium oxide and/ Or aluminium oxide.The material of door 60 may select polycrystalline silicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitride.

Storage element 750 can be further divided into text line (WL) electrode 70 (being connected on door 60 by electric-powered manner), source Polar curve (SL) electrode 72 (being connected on region 16 by electric-powered manner), bit line (BL) electrode 74 (are connected to by electric-powered manner On region 18) and underlayer electrode 78 (being connected to be positioned on the substrate 12 below insulator 22 by electric-powered manner).By multiple storages Figure 92 A is shown in by the schematic diagram of the storage arrays 780 of memory cell 750 composition.

At " the 1T-DRAM storage element of capacitorless " (author: S.Okhonin et al.；The page number: 85～87；IEEE electronics Device bulletin, the second phase, volume 23；In February, 2002) in describe the operational approach of storage element and (also illustrate storage simultaneously The operational approach of unit 750).These contents are also intactly merged in these shelves for reference.Storage element state is with buoyancy aid 24 In electric charge represent.If storage element 750 has hole in floater area 24, then the threshold value of this storage element 750 Voltage (i.e. the gate voltage when transistor is switched on) is than the threshold value of the storage element 750 that there is not hole in floater area 24 Voltage is low.

The electric charge of storage in buoyancy aid 24 can be detected by the electric current of monitoring storage element 750.If at storage element 750 In state " 1 ", and there is hole in floater area 24, compared with being in state " 0 ", floater area 24 do not exists the storage in hole Unit 750, the threshold voltage (i.e. the gate voltage when transistor is switched on) of this storage element by relatively low, correspondingly storage element Electric current (i.e. flowing to the electric current of SL electrode from BL electrode) is higher.Testing circuit/reading circuit 90 is typically attached to storage arrays On the BL electrode 74 of 780 (i.e. reading circuit shown in Figure 92 B).This circuit available determines the data mode of storage element. " small-power and high speed embedding internal memory door is being used to cause drain leakage (GIDL) current design capacitorless 1T-DRAM to store single Unit " (author: Yoshida et al.；The page number: 913～918；International Electron meeting, 2003) and；U.S. Patent number: 7, 301,803 " with the bipolar sensing techniques of storage element of electricity floating body transistor " give the example of this read operation. These contents are also intactly merged in these shelves for reference.At " 18.5ns128MbSOIDRAM of band buoyancy aid storage element " (author: Oshawa et al.；The page number: 458～459,609；IEEE ISSCC, 2005) testing circuit is given in Example.These contents are also intactly merged in these shelves for reference.

Read operation can be carried out: on selected BL electrode 74, apply positive voltage, Xiang Xuan by applying following bias condition On fixed WL electrode 70, the positive voltage of applying is higher than the positive voltage of applying on selected BL electrode 74, to selected SL electrode Apply no-voltage on 72, on underlayer electrode 78, apply no-voltage.Unselected BL electrode will keep no-voltage, unselected it WL will keep no-voltage or negative voltage, unselected SL electrode will keep no-voltage.

In the non-limiting example that this is specific, apply about 0.0 volt of voltage, Xiang Xuan to selected SL electrode 72 Fixed electrode 74 applies about+0.4 volt voltage, applies about+1.2 volts voltages to selected electrode 70, and to substrate electricity Pole 78 applies about 0.0 volt of voltage.Unselected electrode 74 keeps 0.0 volt of voltage, unselected electrode 70 to keep 0.0 volt Special voltage, unselected SL electrode 72 keeps 0.0 volt of voltage.Figure 93 illustrates storage element selected in storage arrays 780 750a and the bias condition of unselected storage element 750b, 750c and 750d.Figure 94 A also illustrates selected storage element The bias condition example of 750a.But, these voltage levels may be varied from.

The bias condition of storage element unselected during the representative read operation described in above-mentioned Figure 93 See Figure 94 B to 94D.With the bias strip that selected storage element 750a shares the storage element (i.e. storage element 750b) with a line Part, and share the bias condition of the storage element (i.e. storage element 750c) with string respectively with selected storage element 750a See Figure 94 B and Figure 94 C, neither share same a line with selected storage element 750, the most do not share the storage element with string (i.e. Storage element 750d) bias condition see Figure 94 D.

For sharing with the storage element (i.e. storage element 750b) of a line with selected storage element, WL electrode 70 For positive bias.But owing to BL electrode 74 is grounded, between BL electrode and SL electrode, there is not electric potential difference, these storage elements yet phase It is disconnected (see Figure 94 B) with answering.

For sharing with the storage element (i.e. storage element 750c) of string with selected storage element, BL electrode 74 On be applied in positive voltage.But, owing to unselected WL electrode 70 is applied in no-voltage or negative voltage, these storage elements also by Disconnect (see Figure 94 C).

For neither sharing same a line with selected storage element, do not share and (i.e. store with the storage element 750 of string Unit 750d) for, WL electrode and BL electrode are all grounded.Therefore, these storage elements are disconnected (see Figure 94 D).

Representative write " 0 " operation of storage element 750 is described by we with reference to Figure 95 now.To SL electrode 72 apply back bias voltage, apply zero potential or nagative potential to WL electrode 70, apply no-voltage and to underlayer electrode 78 to BL electrode 74 Apply no-voltage.Unselected SL electrode 72 keeps ground state.Under these conditions, the buoyancy aid of selected storage element 750 P-n joint between 24 and region 16 is forward bias, it is to avoid hole occur in buoyancy aid 24.At specific non-limiting example In, apply about-1.2 volts voltages to electrode 72, apply about 0.0 volt of voltage to electrode 70, and on electrode 74 and 78 Apply about 0.0 volt of voltage.But, as it was noted above, these voltage levels may keep the phase between being biased It is varied from during to relation.

In write " 0 " operating process, the bias condition example of the storage element 750 that selected sum is unselected is shown in Figure 96 A extremely 96B.Owing to write " 0 " operates the negative voltage on the SL electrode 72 relating only to be applied to select, all unselected storages are single The bias condition of unit be all identical it.It will be seen that unselected storage element carries out keeping operation, BL electrode is maintained at About 0.0 volt, WL electrode is maintained at no-voltage or negative voltage, and unselected SL electrode is maintained at 0.0 volt.

Or, can grasp by carrying out writing " 0 " to the upper method applying back bias voltage of BL electrode 74 (rather than at SL electrode 72) Make.SL electrode 72 will be grounded, and apply no-voltage on underlayer electrode 78, apply no-voltage or negative electricity on WL electrode 70 Pressure.As shown in Figure 97, under these conditions, all storage elements sharing same BL electrode 74 will be written into state " 0 ".

In Figure 95 to 97 indication write " 0 " operation have one disadvantage in that, that is, share same SL electrode 72 or with All storage elements 750 of one BL electrode 74 will be simultaneously written to.Write consequently, it is possible to also do not allow for carrying out single position Enter, be i.e. written in the bit of storage of single storage element 750.Multiple data are write in the storage element 750 of difference, first On all storage elements, first perform write " 0 " operation, on one or more selected positions, perform write " 1 " the most again Operation.

Another write " 0 " operation allows to carry out single position write.Concrete grammar is just to apply on WL electrode 70 Voltage, applies negative voltage on BL electrode 74, applies no-voltage or positive voltage, apply on underlayer electrode 78 on SL electrode 72 No-voltage.Under these conditions, the current potential of buoyancy aid 24 can be by Capacitance Coupled on the basis of the positive voltage being applied to WL electrode 70 Raise.The reason of negative voltage raising due to buoyancy aid 24 current potential and being applied on BL electrode 74, buoyancy aid 24 and region 18 it Between p-n joint be forward bias, it is to avoid there is hole in buoyancy aid 24.Reduce other storage elements in storage arrays 780 Unnecessary write " 0 " interference of 750, be optimized the current potential of applying in following manner: if the buoyancy aid of state " 1 " 24 current potentials are referred to as VFB1, then the voltage that reply is applied on WL electrode 70 configures, to be increased by the current potential of buoyancy aid 24 VFB1/2, and the current potential being applied on BL electrode 74 is-VFB1/2.

In specific non-limiting example, in selected storage element 750a, apply following bias condition: to SL Apply the current potential of about 0.0 volt on electrode 72, on BL electrode 74, apply the current potential of about 0.2 volt, execute on electrode 70 Add the current potential of about+0.5 volt and on underlayer electrode 78, apply the current potential of about 0.0 volt.Meanwhile, to unselected SL electricity Apply about 0.0 volt of current potential on pole 72, on unselected BL electrode 74, apply about 0.0 volt of current potential, to unselected it Apply about 0.0 volt of current potential on WL electrode 70 and on unselected electrode 78, apply about 0.0 volt of current potential.Figure 83 shows The bias condition of the storage element that selected sum is unselected in storage arrays 780 in the above-mentioned case.But, these voltage electricity Put down and may be varied from.

The bias condition of the storage element 750a selected in write " 0 " operating process shown in Figure 98 will be at Figure 99 A In further illustrate and show.As it was noted above, the voltage between buoyancy aid 24 and region 18 (and BL electrode 74 links together) Difference is shown in Figure 99 A.The rising of voltage difference can produce forward biased current, it is to avoid hole occurs in buoyancy aid 24.

The bias condition example of storage element 750 unselected in write " 0 " operating process described in above-mentioned Fig. 8 is shown in Figure 99 B to 99D.With the bias condition that selected storage element 750a shares the storage element (i.e. storage element 750b) with a line See Figure 99 B, share with selected storage element 750a and see with the bias condition of the storage element (i.e. storage element 750c) of string Figure 99 C, neither shares same a line with selected storage element 750, does not the most share storage element (the i.e. storage element with string Bias condition 750d) is shown in Figure 99 D.

Due to the Capacitance Coupled of WL electrode 70, share the storage element with a line with selected storage element (see Figure 99 B) Buoyancy aid 24 current potential add VFB.For being in the storage element of state " 0 ", due to by buoyancy aid 24 and joint 16 and 18 The forward biased current of the p-n diode of composition can avoid occurring in buoyancy aid 24 that hole, buoyancy aid 24 current potential can't continue to increase Go down.Therefore, buoyancy aid 24 current potential can return to original state " 0 " equilibrium potential.Come for being in the storage element of state " 1 " Saying, buoyancy aid 24 current potential is just starting to increase VFB, thus avoids hole occur in buoyancy aid 24.Positive bias quilt on WL electrode 70 After removing, buoyancy aid 24 current potential can reduce VFB.If initial buoyancy aid 24 current potential of state " 1 " is referred to as VFB1, write " 0 " operation Buoyancy aid 24 current potential reforms into VFB1-VFB afterwards.Accordingly, it would be desirable to WL current potential is optimized, it is ensured that storage element in state " 1 " The floating body potential of 750 will not be greatly lowered.Such as, due to Capacitance Coupled in WL current potential, maximum floating body potential not over VFB1/2。

For sharing with the storage element of string with selected storage element, apply to BL electrode 74 (see Figure 99 C) Negative voltage, makes the electric potential difference between buoyancy aid 24 and region 18 (being connected on BL electrode 74) increased.Therefore, buoyancy aid 24 and connecing Between 18, the p-n diode of formation there will be forward bias.For being in the storage element of state " 0 ", buoyancy aid 24 electricity The increase of position will not change original state " 0 ", and reason is in buoyancy aid 24 initially to there is not hole.For being in state " 1 " Storage element for, final result is buoyancy aid 24 current potential can be reduced after write " 0 " operation.Therefore, it is also desirable to BL electricity Position is optimized, it is ensured that in state " 1 ", the floating body potential of storage element 750 will not be greatly lowered.Such as, can be to BL electrode 74 The current potential of upper applying-VFB1/2.

For neither sharing same a line, for not sharing with the storage element of string, to SL with selected storage element Electrode applies no-voltage, applies no-voltage to BL electrode 74, applies no-voltage or negative voltage, to underlayer electrode on WL electrode 70 No-voltage is applied on 78.Therefore, can avoid that hole occurs in buoyancy aid 24.

" 1 " can be entered by the method for above-mentioned ionization by collision in the enterprising row write of storage element 750 to operate.Such as " band strengthens The novel 1TDRAM storage element of floater effect " (author: Lin Hechang；The page number: 23～27；IEEE storing technology, design and test Seminar, 2006) just describe this method.These shelves also add related content wherein.Or can also be by band to band Mechanism then of wearing enters " 1 " operation in the enterprising row write of storage element 750.Such as " small-power and high speed embedding internal memory door is used to cause leakage Pole leakage (GIDL) current design capacitorless 1T-DRAM storage element " (author: Yoshida et al.；The page number: 913～918； International Electron meeting, 2003) just describe this method.These shelves also add related content wherein.

Use band that band is worn mechanism then and write the bias condition model of storage element 750 selected in " 1 " operating process Example is shown in Figure 100 and 101A.On WL electrode 70 applying back bias voltage and on BL electrode 74 positive bias of applying to produce electronics tunneling. So can produce electronics flowing on BL electrode 74, produce hole.Hole may be subsequently poured into selected storage element 750 Buoyancy aid 24.In write " 1 " operating process, SL electrode 72 and base electrode layer 78 can be grounded.

In specific non-limiting example, in selected storage element 750a, apply following bias condition: to SL Apply the current potential of about 0.0 volt on electrode 72, on BL electrode 74, apply the current potential of about+1.2 volts, on WL electrode 70 Apply the current potential of about-1.2 volts and on underlayer electrode 78, apply the current potential of about 0.0 volt.And following bias condition quilt It is applied on unselected electrode: on SL electrode 72, apply about 0.0 volt of current potential, on BL electrode 74, apply about 0.0 Volt current potential, applies about 0.0 volt of current potential on WL electrode 70 and applies about 0.0 volt of current potential on underlayer electrode 78. Figure 100 illustrates the bias condition of the storage element that selected sum is unselected in storage arrays 780.But, these voltage levels May be varied from.

The bias condition of storage element unselected in write " 1 " operating process of the type described in above-mentioned Figure 100 Example is shown in Figure 101 B to 101D.With selected storage element 750a share the storage element (i.e. storage element 750b) with a line it Bias condition is shown in Figure 101 B, and storage element (i.e. storage element 750c) with string shared with selected storage element 750a is partially Press strip part is shown in Figure 101 C.Neither share same a line with selected storage element 750a, the most do not share the storage element with string (i.e. Storage element 750d) bias condition see Figure 101 D.

For sharing with the storage element of a line with selected storage element, electrode 72 and electrode 74 are all grounded, And apply about-1.2 volts voltages to WL electrode 70 (see Figure 101 B).Be enough to cause band that band is worn then occur it owing to not existing Electric potential difference, the buoyancy aid 24 of storage element 750b does not haves the situation of hole injection.

For sharing with the storage element of string with selected storage element, to BL electrode 74 apply positive voltage (see Figure 101 C).Owing to WL electrode 70 is grounded, these storage elements do not have the situation of hole injection.

For neither sharing same a line with selected storage element, do not share with the storage element 750 of string, SL Electrode 72 and BL electrode 74 all keeps ground state (see 101D).Correspondingly, these storage elements do not have write operation.

The bias condition example using ionization by collision to carry out writing storage element 750 selected in " 1 " operating process is shown in figure 102 and 103A to 103D.On selected WL electrode 70, apply positive bias, on all SL electrodes 72, apply positive voltage, Xiang Xuan Apply positive bias on fixed BL electrode 74, and the underlayer electrode 78 of selected storage element keeps ground connection.These conditions cause Occur that hole is injected on the buoyancy aid 24 of selected storage element (i.e. storage element 750a in Figure 103 A).

In specific non-limiting example, in selected storage element 750a, apply following bias condition: to SL Apply the current potential of about 0.0 volt on electrode 72, on BL electrode 74, apply the current potential of about+1.2 volts, to selected WL electricity Apply the current potential of about+1.2 volts on pole 70 and on underlayer electrode 78, apply the current potential of about 0.0 volt.Bias below and Condition is applied on unselected electrode: apply about 0.0 volt of current potential on unselected SL electrode 72, to unselected it Apply about 0.0 volt of current potential on BL electrode 74, on unselected WL electrode 70, apply about 0.0 volt of current potential and to unselected About 0.0 volt of current potential is applied on fixed electrode 78.It is partially that Figure 103 A illustrates the storage element selected in above-mentioned example Press strip part.Example shown in above-mentioned Figure 102 shares the bias condition of the storage element with a line with selected storage element See Figure 103 B.Example shown in above-mentioned Figure 102 shares the bias strip of the storage element with string with selected storage element Part is shown in Figure 103 C.Example shown in above-mentioned Figure 102 neither shares same a line with selected storage element, does not the most share same The bias condition of the storage element of row is shown in Figure 103 D.But, these voltage levels may be varied from.

If floater area 24 has positive charge, the positive charge of storage can passage over time and reduce, reason is point The not diode leakage electric current of the p-n joint between buoyancy aid 24 and region 16 and region 18；Another one reason is exactly Charge recombination.Can execute to region 16 (connecting together with SL electrode 72) and/or region 18 (connecting together with BL electrode 74) Add positive bias, and apply no-voltage or negative voltage to WL electrode 70 and underlayer electrode 78.

In specific non-limiting example, in selected storage element 750, apply following bias condition: to SL electricity Apply the current potential of about 0.0 volt on pole 72, on BL electrode 74, apply the current potential of about+1.2 volts, execute on WL electrode 70 Add the current potential of about 0.0 volt and on underlayer electrode 78, apply the current potential of about 0.0 volt.Under these conditions, be positioned at floating P-n joint between body 24 and region 16 and region 18 is reverse biased, extends the positive charge being stored in floater area 24 Life-span.

Being connected between the region 16 of storage element 750 and SL electrode 72, and the region 18 of storage element 750 is electric with BL Connection between pole 74 realizes it typically by conductive contact.The material of conductive contact can use polysilicon or tungsten.Figure 104 exhibition Contact 72 and the contact 73 of join domain 18 and BL electrode 74 of join domain 16 and SL electrode 72 are shown.The molding of contact can be met To a lot of difficulties.Such as, must separate, to avoid closing between contact and other electrodes (such as gate electrode or the contact closed on) Conduction region be short-circuited.U.S. Patent Application Publication (the numbering 2010/ of entitled " semiconductor device and manufacture method thereof " 0109064) difficulty relevant to contact molding and the solution of some possibilities are described.These contents are also intactly closed Go forward side by side in these shelves for reference.

For simplifying the fabrication schedule of storage element 750, reducing the size of storage element 750, the storage element closed on is setting Timing is it is contemplated that share a public territory 16 (with SL electrode 72) or public territory 18 (with BL electrode 74).Such as, such as figure Shown in 105, U.S. Patent number 6,937,516 " semiconductor device " (inventor: Fazan and Okhonin) illustrate the storage closed on Memory cell shares contact 50 and the layout of contact 52.These contents are also intactly merged in these shelves for reference.So One, the quantity of contact is not from two contacts of each storage element (adjacent storage element is shared in the case of closing on contact) The number of contacts of the storage element being reduced to connection adds 1 equal to the quantity of storage element.Such as, in Figure 105, interconnect it The quantity of storage element (cross-sectional view shows with the storage element of interconnection in string) is 4, and the quantity of contact is 5.

The invention provides the semiconductor memory part with multiple buoyancy aid storage elements.These buoyancy aid storage element or strings Connection, is formed and stores string；In parallel, formed and store chain link.Need between storage element to couple together, single to reduce each storage The quantity of contact required in unit.In some example, on the chain link of the one or both ends or some storage elements that store string Make the control line (such as source line or bit line) of storage element, so can avoid owing to not providing contact by these storage elements even Receiving control online, they become " contactless " storage element at end.More precisely, these storage elements are direct and oneself Adjacent other storage elements contact.Owing to some storage elements are directly connected together in series or in parallel, permissible Obtain the compactest storage element.

Figure 106 A illustrates the canonical schema storing string 500, including multiple storage element 750 (750a in Figure 106 A ～750n, but the quantity of storage element 750 may be different), and bowing of storage element array 780 of Figure 106 B show View.This top view illustrates two storage strings 500 of the storage element 750 between SL electrode 72 and BL electrode 74.Each storage Depositing multiple storage elements 750 that string 500 includes being connected in NAND structure, wherein these storage elements 750 connect in a series arrangement Pick up, form one of storage element and store string.During series connection, identical electric current flows through each storage element 750, from BL electrode 74 flow to SL electrode 72, or in turn.Storing string 500 and include " n " individual storage element 750, wherein " n " is positive integer, generally Between 8 and 64 (this numeral is also possible to such as be equally likely to less than 8-2, or higher than 64).In one example, n At least will be equal to 16.The region 18 being positioned at the second conduction type storing string one end is connected on BL electrode 74, and is positioned at storage The source region 16 of the second conduction type depositing string other end is connected on SL electrode 72.Although Figure 106 B says with schematic diagram Understand one containing two store strings arrays, but it may be noted that be, the invention is not limited in two store go here and there.

Each storage element transistor 750 includes the floater area 24 of the first conduction type, first of the second conduction type Region 20 and Two Areas 20 (are equivalent to first region in the single storage element example of above-mentioned storage element 750 16 and Two Areas 18).They are separated from each other, form channel region.Floater area 24 and bulk are served as a contrast by buried insulator layer 22 Insulate in the end.Door 60 is placed in the surface of buoyancy aid 24.This door is between first region 20 and Two Areas 20.Door 60 And between buoyancy aid 24, have insulating barrier 62, in order to door 60 and buoyancy aid 24 are insulated.From Figure 106 A to 106B it will be seen that only The two ends storing string 500 are had just can control line SL electrode and BL electrode 74 to be coupled together.SL electrode 72 and region 16 are passed through Contact 71 couples together, and BL electrode 74 and region 18 are coupled together by contact 73.Store string 500 in storage element 750 it Region 20 does not make contact, causes the storage element at end contactless storage element intermediate occur.In some example, storage The transistor (i.e. storage element 750a and 750n in Figure 106 A) depositing string 500 ends may be designed to store the reading crystalline substance of string 500 Body pipe, and the electric charge being stored in association buoyancy aid 24 (i.e. 24a and 24b in Figure 106 A example) fails to read.

Figure 107 illustrates the example of the equivalent circuit of a storage arrays 780 in Figure 106 B.In Figure 107, storage element Being aligned to grid, storage arrays trip can determine by WL electrode 70, and arrange and can be determined by BL electrode 74.More than in each column Individual storage element 750 couples together in a series arrangement, is formed and stores string 500.Adjacent row are separated (see figure by the row of insulation layer 26 106B), such as shallow trench insulation (STI).

Refer to Figure 108 and Figure 109 A to 109B read operation is described.Can by apply following bias condition it Mode carries out read operation.Storage element 750c is selected to be illustrated in this example: to execute on selected BL electrode 74 Adding positive voltage, on selected WL electrode 70, the positive voltage of applying is higher than the positive voltage of applying on selected BL electrode 74, On selected SL electrode 72, apply no-voltage, on underlayer electrode 78, apply no-voltage.Unselected BL electrode 74 will keep No-voltage, unselected SL electrode 72 will keep no-voltage.Positive electricity is applied on transmission electrode 70a, 70b, 70l, 70m and 70n Pressure, this positive voltage is higher than the positive voltage (see Figure 108 and 109A to 109B) on the WL electrode 70c being applied to select.WL passes Passing electrode to be connected to transmit on the door of storage element, be i.e. connected to by series system on the storage element 750c that selectes is unselected Fixed storage element (i.e. 750a, 750b, 750l, 750m and 750n in Figure 108).It is applied to transmit the electricity on storage element door Pressure transmission transistor to be guaranteed can be connected, it is not necessary to considers the current potential of they floater areas.Need to connect transmission storage element, reason Being in series system, electric current flows to SL electrode 72 (or flowing to BL electrode 74 from SL electrode 72) from BL electrode 74, therefore Electric current can flow through each storage element 750.Therefore, transmission storage element can be applied to the electricity on SL electrode 72 and BL electrode 74 Position is delivered to the source area 20b and drain region 20c of the storage element 750c selected.Such as, storage element 750n can be applied to Voltage on BL electrode 74 passes to be connected to the region 20m of storage element 750n (and 750m).Storage element 750m can be subsequently This voltage is passed to the region 201 being connected on storage element 750l.Adjacent transmission storage element can transmit applying subsequently Voltage on BL electrode 74, until this voltage reaches the region 20c of selected storage element 750c.

In specific non-limiting example, in selected storage element 750c, apply following bias condition: to SL Apply the current potential of about 0.0 volt on electrode 72, on BL electrode 74, apply the current potential of about+0.4 volt, to selected WL electricity Apply the current potential of about+1.2 volts on pole 70, on WL transmission electrode 70, apply the current potential of about+3.0 and to underlayer electrode 78 The current potential that upper applying is about 0.0 volt.And following bias condition is applied on unselected electrode: to SL electrode 72 (figure 109A does not shows unselected SL electrode 72) about 0.0 volt of current potential of upper applying, apply about 0.0 volt to BL electrode 74 Current potential, other WL electrodes 70 (Figure 109 A does not shows) outside WL transmission electrode apply about 0.0 volt of current potential and to substrate The current potential of about 0.0 volt is applied on electrode 78.Figure 108 and 109A to 109B illustrates in storage arrays 780 and selectes sum not The bias condition of selected storage element.But, these voltage levels may be varied from.

Under these conditions, the door 60 to selected storage element 750c applies about+1.2 volts voltages, 0.00 volt Can be respectively passed in the region 20b and region 20c of storage element 750c selected with 0.4 volt of voltage, be similar to Figure 94 A Shown readout condition.As it was noted above, transmission storage element is in bias state, in order to its channel can conduct electricity.Therefore, from storage The electric current of BL electrode 74 and SL electrode 72 outflow depositing string 500 depends on the electricity of the floater area 24 of the storage element 750c selected Position.If storage element 750c is in state " 1 ", and has hole in floater area 24, compared with being in state " 0 ", at buoyancy aid District 24 does not exist the storage element 750c in hole, threshold voltage (the i.e. door electricity when transistor is switched on of this storage element Pressure) by relatively low, correspondingly electric current is higher.

Testing circuit/reading circuit 90 is typically attached on the BL electrode 74 of storage arrays 780 (i.e. shown in Figure 109 B Reading circuit).This circuit available determines the data mode of storage element." band buoyancy aid storage element it 18.5ns128MbSOIDRAM " (author: Ohsawa et al.；The page number: 458～459,609；IEEE ISSCC, 2005) example of testing circuit is given in.These contents are also intactly merged in these shelves for reference.

By Figure 110 to 111, write " 0 " operation is described.The bias condition of display includes: apply to SL electrode 72 No-voltage, applies no-voltage to WL electrode 70, applies negative voltage to BL electrode 74, and underlayer electrode 78 is grounded.At these Under part, in storage string, the p-n joint between buoyancy aid 24 and the region 20 of each storage element is forward bias, it is to avoid in buoyancy aid 24 Hole occurs.In specific non-limiting example, apply about-1.2 volts voltages to electrode 74, apply greatly to electrode 70 About 0.0 volt of voltage, applies about 0.0 volt of voltage to electrode 72 and applies about 0.0 volt of voltage to electrode 78.Or, On WL electrode 70 apply positive voltage, it is ensured that be applied to the negative voltage on BL electrode 74 can be delivered to store string 500 in all it Storage element.But, as it was noted above, these voltage levels may when keeping applying the relativeness between electric charge Change.

Another write " 0 " operation allows to carry out single position write, refers to Figure 112 A to 112B.Concrete grammar be to Apply negative voltage on BL electrode 74, on SL electrode 72, apply no-voltage, on underlayer electrode 78, apply no-voltage and pass to WL Pass electrode and apply positive voltage.First selected WL electrode is carried out ground connection, until the electricity being applied on SL electrode 72 and BL electrode Pressure can arrive separately at the region 20b and region 20c of selected storage element 750c.Subsequently, WL electrode 70 that will be selected is (at this model For 70c in example) current potential be increased to positive voltage, and guarantee to be higher than the positive voltage being applied on WL transmission electrode.At these Under part, the goalkeeper of selected storage element (i.e. storage element 750c in Figure 112 A to 112B) can be applied in positive voltage, subsequently Buoyancy aid 24 current potential will have been raised on the basis of the positive voltage being applied on WL electrode 70 by Capacitance Coupled.Transmission stores The negative voltage that unit (i.e. storage element 750l, 750m and 750n) is applied on BL electrode 74 pass to storage element 750c it Region 20c, and transmit the no-voltage that storage element 750a and 750b be applied on SL electrode 72 and pass to storage element 750c Region 20b.Under these conditions, the bias condition of selected storage element 750c is similar to the condition described in Figure 99 A.By In the reason of negative voltage that buoyancy aid 24 current potential raises and is applied on BL electrode 74, the p-n between buoyancy aid 24c and region 20c connects Head is forward bias, it is to avoid hole occur in buoyancy aid 24.Reduce in storage arrays 780 other storage elements 750 need not Write " 0 " interference wanted, be optimized the current potential of applying in following manner: if the buoyancy aid 24 current potential quilt of state " 1 " It is referred to as VFB1, then the voltage that reply is applied on WL electrode 70 configures, so that the current potential of buoyancy aid 24 is increased VFB1/2, and The current potential being applied on BL electrode 74 is-VFB1/2.The voltage being applied to transmit the WL electrode of storage element is optimized, really Guarantor has sufficiently high voltage to be delivered on BL electrode 74 by the negative voltage of applying；But voltage can not be too high, to avoid passing The electromotive force of the buoyancy aid 24 passing storage element becomes too high, so can avoid appearance in the transmission storage element being in state " 1 " Hole.The no-voltage of applying passes to SL electrode 72 (be i.e. positioned at the WL on the left of selected WL electrode 70c and transmit electrode, such as figure 70a and 70b in 112A) WL transmission electrode on the positive voltage that is applied in be higher than the negative voltage of applying passed to BL electrode The voltage being applied on the WL transmission electrode of 74 (are i.e. positioned at the WL on the right side of selected WL electrode 70c and transmit electrode).Reason is, Compared with the negative voltage being applied on electrode 74, the voltage being applied on electrode 72 is higher, it may be necessary to higher transfer gate electricity Pressure, in order to transmission transistor is connected.

In specific non-limiting example, apply following bias condition to storing in string 500: execute on SL electrode 72 Add the current potential of about 0.0 volt, on BL electrode 74, apply the current potential of about 0.2 volt, apply on selected WL electrode 70 The current potential of about+0.5 volt, applies the current potential of about+0.2 on WL transmission electrode 70 and applies about on underlayer electrode 78 The current potential of 0.0 volt.Meanwhile, on unselected SL electrode 72, about 0.0 volt of current potential is applied, to unselected BL electrode 74 About 0.0 volt of current potential of upper applying, to unselected WL electrode 70 (non-transmission electrode) upper apply about 0.0 volt of current potential and to About 0.0 volt of current potential is applied on unselected electrode 78.Figure 112 A illustrates the selected transmission in selected storage string 500 The bias condition of storage element, and the bias of the storage element that selected sum is unselected in Figure 112 B show storage arrays 780 Condition, wherein storage element 750c is selected storage element.But, these voltage levels may be varied from.

Under these bias conditions, on the door 60 of selected storage element 750c, apply positive voltage, and be applied to BL electricity Negative voltage on pole 74 will be passed in the region 20c of storage element 750c selected, zero electricity being applied on SL electrode 72 Pressure will be passed in the region 20b of storage element 750c selected.This condition is similar to the condition described in Figure 99 A, can keep away Exempt from that hole occurs in the buoyancy aid 24 of storage element 750c.

Use band that band is worn mechanism then and write the bias condition model of storage element 750 selected in " 1 " operating process Example is shown in Figure 113 A and 113B.On selected WL electrode 70, apply back bias voltage, on WL transmission electrode 70, apply positive voltage, to SL Electrode 72 (and all SL electrodes 72) applies no-voltage, apply on selected BL electrode 74 positive bias (to unselected it BL electrode 74 applies no-voltage), and underlayer electrode 78 is grounded.These conditions cause at selected storage element (i.e. Figure 113 A Storage element 750c to 113B) buoyancy aid 24 on occur that hole is injected.

In specific non-limiting example, in selected storage string 500, apply following bias condition: to SL electrode Apply the current potential of about 0.0 volt on 72, on BL electrode 74, apply the current potential of about+1.2 volts, to selected WL electrode 70 The current potential that upper applying is about-1.2 volts, applies the current potential of about+3.0 on WL transmission electrode 70 and executes on underlayer electrode 78 Add the current potential of about 0.0 volt.And following bias condition is applied on unselected electrode: apply about on SL electrode 72 0.0 volt of current potential, applies about 0.0 volt of current potential on BL electrode 74, to unselected WL electrode 70 (non-transmission electrode) (figure 113B does not shows) above apply about 0.0 volt of current potential and on underlayer electrode 78, apply about 0.0 volt of current potential.Figure 113 A Illustrate the bias condition of selected transmission storage element in selected storage string 500, and Figure 113 B show storage arrays The bias condition of the storage element that selected sum is unselected in 780, wherein storage element 750c is selected storage element.So And, these voltage levels may be varied from.

Under these bias conditions, on the door 60 of selected storage element 750c, apply negative voltage, and be applied to BL electricity Positive voltage on pole 74 will be passed in the region 20c of storage element 750c selected, zero electricity being applied on SL electrode 72 Pressure will be passed in the region 20b of storage element 750c selected.This condition is similar to the condition described in Figure 101 A, can keep away Exempt from that the buoyancy aid 24 of storage element 750c occurs that hole is injected.

The bias condition example of storage element 750 selected in ionization by collision write " 1 " operating process is shown in Figure 114 A extremely 114B.On selected WL electrode 70, apply positive bias, apply, on WL transmission electrode 70, the WL electrode 70 that ratio is applied to select The positive voltage that upper positive voltage is higher, executes on SL electrode 72 (including the SL electrode 72 selected and other all SL electrodes 72) Add no-voltage, on selected BL electrode 74, apply positive bias (applying no-voltage on unselected BL electrode), and substrate is electric Pole 78 is grounded.These conditions cause the buoyancy aid at selected storage element (i.e. storage element 750c in Figure 114 A to 114B) Occur on 24 that hole is injected.

In specific non-limiting example, in selected storage string 500, apply following bias condition: to SL electrode Apply the current potential of about 0.0 volt on 72, on BL electrode 74, apply the current potential of about+1.2 volts, to selected WL electrode 70 The current potential that upper applying is about+1.2 volts, applies the current potential of about+3.0 on WL transmission electrode 70 and executes on underlayer electrode 78 Add the current potential of about 0.0 volt.And following bias condition is applied on unselected electrode (i.e. selected storage element place Storage string beyond storages go here and there in electrode): on SL electrode 72, apply about 0.0 volt of current potential, execute on BL electrode 74 Add about 0.0 volt of current potential, to WL electrode 70 (not showing in Figure 114 B) about 0.0 volt of current potential of upper applying and to underlayer electrode About 0.0 volt of current potential is applied on 78.The transmission storage element selected that Figure 114 A illustrates in selected storage string 500 is partially Press strip part, and the bias condition of the storage element that selected sum is unselected in Figure 114 B show storage arrays 780, wherein store Unit 750c is selected storage element.But, these voltage levels may be varied from.

Utilization is alternately written into and can carry out multistage write operation with verification algorithm, is first applied to write pulse store On unit 750, carry out write operation the most again, to verify whether to reach the storing state of expection.If being also not reaching to pre- The storing state of phase, applies new write pulse on storage element 750, carries out write verification operation the most again.Repeat into The above operation of row, until reaching the storing state of expection.

Such as, utilize band that band hot hole is injected, apply positive voltage to BL electrode 74, on SL electrode 72, apply zero electricity Pressure, applies negative voltage on selected WL electrode 70, applies positive voltage, and apply on underlayer electrode 78 on WL transmission electrode No-voltage.The positive voltage of different amplitude is applied, in order in buoyancy aid 24, write the state of difference on BL electrode 74.Thus can Cause the floating body potential 24 of difference, from different positive voltage or to have been applied to the positive voltage pulse quantity on BL electrode 74 relative Should.In specific non-limiting example, carry out write operation by applying following bias condition: apply on SL electrode 72 The current potential of about 0.0 volt, applies the current potential of about-1.2 volts on selected WL electrode 70, executes on WL transmission electrode 70 Add the current potential of about+3.0 and on underlayer electrode 78, apply the current potential of about 0.0 volt, being simultaneously applied on BL electrode 74 it Current potential will be incremented by.Such as, in non-limiting example, first apply 25 millivolts of current potentials to BL electrode 74, read subsequently Go out verification operation.(storage element electric current is to show to have reached the state of expection by storage element electric current if the read out verification operation Reach the state corresponding with 00,01,10 or 11 states), then multistage write operation can be terminated.If not yet reaching to expect it State, then the voltage being applied on BL electrode 74 should be improved.Such as bring up to 50 millivolts from 25 millivolts.Followed by once Read verification operation, and this process of repetitive operation, until it reaches the state of expection.But, above-mentioned voltage level there may be Changed.Read operation is carried out, to verify storing state after write operation.

Store string 500 and can be used as plane storage element, the such as example shown in Figure 91 and 106A；It also is used as fin three Dimension storage element, such as the example shown in Figure 115 A to 115B.It can also be changed, change or use replacement to store Unit 750, without departing from the scope of the invention and functional.

We have a look Figure 23 now, which show and meet one of present example storage element 150.Store single Unit makes in the bulk substrate 12 of the first conduction type (such as p-type electric-conducting).Additionally provide the second conductive-type on the substrate 12 The buried layer 22 of type (such as N-shaped conduction), is buried in substrate 12, as shown in the figure.Can be by ion injecting process at substrate 12 Material on formed buried layer 22.Or, it is also possible to form buried layer 22 by the mode of epitaxial growth.

First region 16 using the second conduction type is there is on substrate 12.This region is exposed on surface 14.Substrate Second region 18 using the second conduction type is there is also on 12.This region be the most also exposed on surface 14 and with first Region 16 separates.According to current industry known and the ion implantation technology of generally employing, composition substrate 12 material on adopt Take ion implantation technology and form first region 16 and Two Areas 18.Or, solid state diffusion process can be used to form first Individual region 16 and Two Areas 18.

Use the floater area 24 of the first conduction type (such as p-type electric-conducting type) by region, 14, first, surface 16 with Two Areas 18, insulating barrier 26 and the restriction of buried layer 22.For example, insulating barrier 26 (i.e. shallow trench insulation (STI)) can Use silicon dioxide material.When being connected in array 180 by multiple storage elements 150, insulating barrier 26 can make storage element 150 With neighbouring storage element 150 phase insulation.Can be by taking the method shape of ion implantation technology on the material of composition substrate 12 Become floater area 24, or take epitaxial growth method.Door 60 is placed between region 16 and region 18, is positioned at above surface 14.Door 60 Insulated with surface 14 by insulating barrier 62.The material of insulating barrier 62 may select silicon dioxide and/or other dielectric material, such as High-k material, includes but are not limited to peroxidating tantalum, titanium oxide, zirconium oxide, hafnium oxide and/or aluminium oxide.Door 60 Material may select polycrystalline silicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitride.

Storage element 150 can be further divided into text line (WL) electrode 70 (being connected on door 60 by electric-powered manner), source Line (SL) electrode 72 (being connected on region 16 by electric-powered manner), bit line (BL) electrode 74 (are connected to district by electric-powered manner On territory 18), buried well (BW) electrode 76 (being connected on buried layer 22) and underlayer electrode 78 (be connected to be positioned at by electric-powered manner On substrate 12 below insulator 22).

" by low cost eDRAM application program CMOS90nm technique construction quantify 1T-Bulk device " (author: Ranica et al.；The page number: 38～41, technical volume；VLSI technical brief and collection of thesis, 2005) and entitled " maintain charged buoyancy aid The method of the state of the semiconductor memory of transistor " application (sequence number: 12/797,334) in describe storage element in detail The operation of 150.These contents are also intactly merged in these shelves for reference.

The state of storage element is represented by the electric charge in buoyancy aid 24.If storage element 150 is deposited in floater area 24 There is hole, then threshold voltage (i.e. the gate voltage when the transistor is switched on) ratio of this storage element 150 is at floater area The threshold voltage of the storage element 150 that there is not hole in 24 is low.

As shown in figure 25 above, this storage element 150 example is inherently with n-p-n bipolar device 130a and 130b, by hidden Bury wellblock 22, buoyancy aid 24, district 18 of SL district 16 and BL form.Electrode 72 can be made by applying forward and reverse bias on BW electrode 76 And/or the method for electrode 74 ground connection, utilize n-p-n bipolar device 130a and 130b to carry out keeping operation.If buoyancy aid 24 band is just Electric charge (is i.e. in state " 1 "), and the bipolar transistor 130a being made up of SL district 16, buoyancy aid 24 and buried wellblock 22 will be connect Logical, the bipolar transistor 130b being simultaneously made up of BL district 18, buoyancy aid 24 and buried wellblock 22 also will be switched on.

Next a part of bipolar transistor current can flow into floating body region 24 (commonly referred to " base current ") and keep State " 1 " data.Can be by bipolar device 130a and 130b that buried wellblock 22, floating body region 24 and region 16/18 are formed The method being designed as low gain type bipolar device improves the efficiency keeping operation, and bipolar gain may be defined as from BL electrode 76 Ratio between collector current and the base current flow in floating body region 24 of outflow.

For the storage element in state " 0 " data, will not turn on bipolar device 130a and 130b, the most not Have base stage hole current and flow into floating body region 24.Therefore, the storage element in state " 0 " will remain in state " 0 ".

It is applied to storage element 150 to carry out keeping the bias condition example of operation to include: on BL electrode 74, apply zero Voltage, applies no-voltage on SL electrode 72, applies no-voltage or negative voltage, just apply on BW electrode 76 on WL electrode 70 Voltage also applies no-voltage on underlayer electrode 78.In specific non-limiting example, apply about 0.0 volt to electrode 72 Special voltage, applies about 0.0 volt of voltage to electrode 74, applies about 0.0 volt of voltage to electrode 70, apply greatly to electrode 76 About+1.2 volts of voltages also apply about 0.0 volt of voltage to electrode 78.But, these voltage levels may be varied from.

Figure 116 A illustrates the energy band schematic diagram of intrinsic n-p-n bipolar device 130, and now floater area 24 is positively charged, Buried wellblock 22 is applied in positive bias.Dotted line represents the Fermi level in n-p-n transistor 130 regional.Fermi energy level In solid line 17 (represent valency can the top of band, the bottom of band gap) and solid line 19 (bottom of expression conductive strips, the top of band gap Portion) between band gap in.Positive charge in floater area 24 reduces inflow floater area 24 (base region of n-p-n bipolar device) In the energy barrier of electron stream.Once electronics is injected into floater area 24, owing to being applied to the effect of positive bias on buried wellblock 22, Buried wellblock 22 (being connected on BW electrode 76) will be poured in.Due to the reason of positive bias, electronics injection rate can be accelerated, pass through Ionization by collision mechanism produces hot carrier (hot hole and thermoelectron to).Thus the thermoelectron of generation can flow into BW electrode 76, and produces The hot hole of life can subsequently flow into floater area 24.Electric charge is stored on buoyancy aid 24 by this process again, reaches top level；And And the electric charge in floater area 24 can be remained stored in.So can ensure that n-p-n bipolar device 130 in an ON state, directly To by BW electrode 76, positive bias is applied in buried wellblock 22.

If buoyancy aid 24 band neutral charge (voltage on buoyancy aid 24 is equal with the voltage on the bitline regions 16 of ground connection), i.e. locate In the state corresponding with state " 0 ", bipolar device will not be switched on, and does not the most just have base stage hole current to flow into floater area 24.Therefore, the storage element in state " 0 " will remain in state " 0 ".

Figure 116 B show energy band schematic diagram of intrinsic n-p-n bipolar device 130, now floater area 24 band neutrality electricity Lotus, buried wellblock 22 is applied in bias.In this state, the energy level of the band gap limited by solid line 17A and 19A is at n-p-n The regional of bipolar device 130 is the most different.Owing to the current potential of floater area 24 is identical with the current potential of bitline regions 16, thus take Close energy level is invariable, thus produces energy barrier between bitline regions 16 and floater area 24.Solid line 23 represents bitline regions 16 and floats Energy barrier between body district 24, for reference.Energy barrier can prevent electron stream from flowing to from bitline regions 16 (being connected to BL electrode 74) Floater area 24.Therefore, n-p-n bipolar device 130 can remain open.

Although bipolar device 130 is referred to as n-p-n transistor by the example in Figure 25,116A and 116B, there is general skill People can consider at any time to exchange the first conduction type and the second conduction type, and the relative value of the voltage of reverse applying.Storage Memory cell 150 should comprise bipolar device 130, and it is p-n-p transistor.Selection p-n-p transistor is as example, to simplify figure 25, the explanation of 116A and 116B.This selection is restricted never in any form.Additionally, the discussion in Figure 25,116A and 116B Employ bipolar device 130b (being made up of bitline regions 18, floater area 24 and buried wellblock 22).This principle is also applied for bipolar device Part 130a (is made up of Yuan Xian district 16, floater area 24 and buried wellblock 22).

The electric charge of storage in buoyancy aid 24 can be detected by the electric current of monitoring storage element 150.If at storage element 150 In state " 1 ", and there is hole in floater area 24, compared with being in state " 0 ", floater area 24 do not exists the storage in hole Unit 150, the threshold voltage (i.e. the gate voltage when transistor is switched on) of this storage element by relatively low, correspondingly storage element Electric current (i.e. flowing to the electric current of SL electrode from BL electrode) is higher.Read operation example has a detailed description in lower gear: " using Small-power and high speed embedding internal memory door cause drain leakage (GIDL) current design capacitorless 1T-DRAM storage element " (make Person: Yoshida et al.；The page number: 913～918；International Electron meeting, 2003)；" band buoyancy aid storage element it 18.5ns128MbSOIDRAM " (author: Ohsawa et al.；The page number: 458～459,609；IEEE ISSCC, 2005)；U.S. Patent number: 7,301,803 " with the bipolar sensing techniques of storage element of electricity floating body transistor ".These contents Also intactly it is merged in these shelves for reference.

Read operation can be carried out on storage element 150: on BW electrode 76, apply zero by applying following bias condition Voltage, applies no-voltage on SL electrode 72, applies positive voltage, execute on selected WL electrode 70 on selected BL electrode 74 In addition positive voltage is higher than the positive voltage of applying on selected BL electrode 74, applies no-voltage on underlayer electrode 78.Work as storage (referring to Figure 117) when memory cell 150 is in the array 180 of storage element 150, unselected BL electrode 74 will keep zero electricity Pressure, unselected WL electrode 70 will keep no-voltage or negative voltage.As shown in Figure 117, in specific non-limiting example, Apply about 0.0 volt of voltage to electrode 72, apply about+0.4 volt voltage to electrode 74a, apply to selected electrode 70a About+1.2 volts voltages, apply about 0.0 volt of voltage to electrode 76 and apply about 0.0 volt of voltage to electrode 78.

Write " 0 " operation of storage element 150 is described by we with reference to Figure 118 now.In this example, in order to Carry out writing " 0 " operation to storage element 150, on SL electrode 72, apply negative voltage, on BL electrode 74, apply no-voltage, to Apply no-voltage or negative voltage on WL electrode 70, on BW electrode 76, apply no-voltage or positive voltage and execute on underlayer electrode 78 Add no-voltage.The SL electrode 72 by the unselected storage element 150 on the unified storage element 150a being connected to and selecting will not Keep ground connection.Under these conditions, the p-n joint between buoyancy aid 24 and region 16 is forward bias, it is to avoid occur in buoyancy aid 24 Hole.In specific non-limiting example, apply about-1.2 volts voltages to electrode 72, apply about to electrode 74 0.0 volt of voltage, applies about 0.0 volt of voltage to electrode 70, applies about 0.0 volt of voltage and to electrode 78 to electrode 76 Apply about 0.0 volt of voltage.But, as it was noted above, these voltage levels may keep the phase between applying electric charge It is varied from during to relation.Under these conditions, all storage elements sharing same SL electrode 72 will be written into state “0”。

Can operate by carrying out writing " 0 " to the upper method applying back bias voltage of BL electrode 74 (rather than at SL electrode 72).SL Electrode 72 will be grounded, and apply no-voltage or positive voltage on BW electrode 76, apply no-voltage on underlayer electrode 78, to WL electricity No-voltage or negative voltage is applied on pole 70.Under these conditions, all storage elements sharing same BL electrode 74 will be write Enter state " 0 ".

In Figure 118, write " 0 " operation of indication has one disadvantage in that, that is, share same SL electrode 72 or same All storage elements 150 of BL electrode 74 will be simultaneously written to.Consequently, it is possible to do not allow for carrying out single position write yet, I.e. it is written in the bit of storage of single storage element 150.Multiple data are write, first in the storage element 150 of difference All storage elements perform write " 0 " operation, on one or more selected positions, performs write " 1 " behaviour the most again Make.

Another write " 0 " operation allows to carry out single position write.With write " 0 " behaviour shown in Figure 118 above Making difference, this method is applying positive voltage on WL electrode 70, applies negative voltage, execute on SL electrode 72 on BL electrode 74 Add no-voltage or positive voltage, on BW electrode 76, apply no-voltage or positive voltage, and on underlayer electrode 78, apply no-voltage.Figure 119 examples illustrating this method.Under these conditions, the current potential of buoyancy aid 24 can be applied to WL electrode by Capacitance Coupled Raise on the basis of the positive voltage of 70.The reason of the negative voltage raised due to buoyancy aid 24 current potential and be applied on BL electrode 74, P-n joint between buoyancy aid 24 and region 18 is forward bias, it is to avoid hole occur in buoyancy aid 24.It is applied to the WL electrode selected 70 can affect unselected storage element 150 (with selected storage element 150 potentially with the bias on selected BL electrode 74 Share same WL electrode or BL electrode) state.Reduce other storage elements 150 unnecessary in storage arrays 180 Write " 0 " interference, in following manner the current potential of applying is optimized: if buoyancy aid 24 current potential of state " 1 " is claimed For VFB1, then the voltage that reply is applied on WL electrode 70 configures, so that the current potential of buoyancy aid 24 is increased VFB1/2, and execute The current potential being added on BL electrode 74 is-VFB1/2.Thus by storage element 150 unselected in state " 1 " (with selected storage Memory cell 150 shares same BL electrode) in buoyancy aid 24 current potential become VFB1/2 from VFB1.For with selected storage element For 150 storage elements 150 of the state that is in " 0 " sharing same WL electrode, unless buoyancy aid 24 current potential increases to obtain a lot (examples As, at least increase VFB/3, see below), otherwise n-p-n bipolar device 130a and 130b will not be switched on)；Or base stage is protected Hold electric current of a sufficiently low, it is impossible to enough make buoyancy aid 24 current potential increase along with the change of write operation time.Can be true according to the present invention Fixed is that, if buoyancy aid 24 current potential increases the words of VFB/3, this increments is sufficient for low, can suppress the increasing of buoyancy aid 24 current potential Add.Positive voltage can be applied, to reduce unnecessary write " 0 " operation further to other storages in storage arrays on SL electrode 72 The interference of memory cell 150.Unselected storage element will be in hold mode, say, that applies no-voltage on WL electrode 70 Or negative voltage, on BL electrode 74, apply no-voltage.

In specific non-limiting example, for selected storage element 150, apply about to electrode 72 0.0 volt of voltage, applies about 0.2 volt of voltage to electrode 74, applies about+0.5 volt voltage to electrode 70, to electrode 76 Apply about 0.0 volt of voltage and apply about 0.0 volt of voltage to electrode 78.For with selected storage element 150 not altogether For enjoying the unselected storage element of same WL electrode or BL electrode, apply about 0.0 volt of voltage to electrode 72, to electricity Pole 74 applies about 0.0 volt of voltage, applies about 0.0 volt of voltage to electrode 70, applies about 0.0 volt of electricity to electrode 76 Pressure also applies about 0.0 volt of voltage to electrode 78.Figure 119 illustrates storage element selected in array 180 set forth above 150 and the bias condition of other storage elements 150.But, these voltage levels may be varied from.

" 1 " can be entered by the method for above-mentioned ionization by collision in the enterprising row write of storage element 150 to operate.Such as " band strengthens The novel 1TDRAM storage element of floater effect " (author: woods et al.；The page number: 23～27；IEEE storing technology, design and test Seminar, 2006) just describe this method.These shelves also add related content wherein.Or can also be by band to band Mechanism then of wearing enters " 1 " operation in the enterprising row write of storage element 150.Such as " small-power and high speed embedding internal memory door is used to cause leakage Pole leakage (GIDL) current design capacitorless 1T-DRAM storage element " (author: Yoshida et al.；The page number: 913～918； International Electron meeting, 2003) just describe this method.These shelves also add related content wherein.

Use band that band is worn mechanism then and write the bias condition model of storage element 150 selected in " 1 " operating process Example is shown in Figure 120 A.It is applied to the upper back bias voltage of WL electrode 70 (being 70a in Figure 120 A) and is applied to BL electrode 74 (at Figure 120 A In be 74a) upper positive bias causes the buoyancy aid 24 of the storage element 150 (being 150a in Figure 120 A) selected to occur that hole is noted Enter.In write " 1 " operating process, SL electrode 72 (being 72a in Figure 120 A) and underlayer electrode 78 (being 78a in Figure 120 A) It is grounded；Can be to upper no-voltage or the positive voltage of applying of BW electrode 76 (being 76a in Figure 120 A) (as we keep grasping above Discussed in work, it, can apply positive voltage, to keep the positive charge finally obtained on buoyancy aid 24).Unselected WL electrode 70 (being 70n in Figure 31) and unselected BL electrode 74 (being 74n in Figure 120 A) will keep ground connection.

In specific non-limiting example, in selected storage element 150a, apply following bias condition: to SL Apply the current potential of about 0.0 volt on electrode 72, on BL electrode 74, apply the current potential of about+1.2 volts, on WL electrode 70 Apply the current potential of about-1.2 volts, on BW electrode 70, apply the current potential of about 0.0 volt, and apply on underlayer electrode 78 The current potential of about 0.0 volt.And following bias condition is applied on unselected electrode: apply about on SL electrode 72 0.0 volt of current potential, applies about 0.0 volt of current potential on BL electrode 74, applies about 0.0 volt of current potential on WL electrode 70, Apply on BW electrode 76 about 0.0 volt of current potential (or apply+1.2 volts of current potentials, make unselected storage element keep Operation) and on underlayer electrode 78, apply about 0.0 volt of current potential.Figure 120 A illustrates the bias of selected storage element 150 Condition.But, these voltage levels may be varied from.

Figure 120 B show selected storage element 150 (150a) and unselected in ionization by collision write " 1 " operating process The bias condition of fixed storage element 150 (150b, 150c and 150d).To selected WL electrode 70 (i.e. 70a in Figure 120 B) Apply positive voltage, apply positive voltage to selected BL electrode 74 (i.e. 74a in Figure 120 B).By SL electrode 72 (i.e. in Figure 120 B 72a), BW electrode 76 (i.e. 76a in Figure 120 B) and underlayer electrode 78 (i.e. 78a in Figure 120 B) ground connection.These condition meetings In channel region formed be enough to produce the lateral electric fields of thermoelectron, can produce subsequently electronics to and hole pair.Next hole quilt It is injected in selected storage element floater area 24.Unselected WL electrode 70 and unselected BL electrode 74 are grounded, and not Selected BW electrode can apply positive voltage with ground connection or to it, to keep the state of unselected storage element.

In specific non-limiting example, in selected storage element 150a, apply following bias condition: to SL Apply the current potential of about 0.0 volt on electrode 72, on BL electrode 74, apply the current potential of about+1.2 volts, on WL electrode 70 Apply the current potential of about+1.2 volts, apply about 0.0 volt of voltage to BW electrode 76, and apply about on underlayer electrode 78 The current potential of 0.0 volt.And following bias condition is applied on unselected electrode: apply about 0.0 volt on SL electrode 72 Special current potential, applies about 0.0 volt of current potential on BL electrode 74, applies about 0.0 volt of current potential on WL electrode 70, to BW electricity Apply on pole 76 about 0.0 volt of current potential (or apply+1.2 volts of current potentials, make unselected storage element carry out keep operation) And on underlayer electrode 78, apply about 0.0 volt of current potential.The bias condition of the storage element 150 that Figure 120 B show is selected. But, these voltage levels may be varied from.

Figure 121 A illustrates the canonical schema storing string 520, including multiple storages linked together in a series arrangement Unit 150；And Figure 121 B show top view of storage element array 180.This top view illustrates SL electrode 72 and BL electrode Two storage strings of the storage element 520 between 74.Although Figure 121 B stores string to schematically illustrate one containing two Array, but it may be noted that be, the invention is not limited in two store string.Reason is can also be in above-mentioned mode equally Make one or more and store string.Each storage string 520 includes the multiple storage elements 150 being connected in NAND structure, Wherein these storage elements 150 couple together in a series arrangement, form one of storage element and store string.During series connection, identical it Electric current flows through each storage element 150, flows to SL electrode 72 from BL electrode 74, or in turn.Store string 500 and include that " n " is individual Storage element 750, wherein " n " is positive integer, generally between 8 and 64.In one example, n at least will be equal to 16.So And, this numeral is also possible to such as be equally likely to less than 8-2, or higher than 64.It is positioned at the second conductive-type storing string one end The region 18 of type is connected on BL electrode 74, and is positioned at source region 16 quilt of the second conduction type storing string other end It is connected on SL electrode 72.

Each storage element transistor 150 includes the floater area 24 of the first conduction type, first of the second conduction type Region 20 and Two Areas 20 (are equivalent to first region in the single storage element example of above-mentioned storage element 150 16 and Two Areas 18).They are separated from each other, form channel region.Store the region 20 of storage element adjacent in string 520 It is joined together by conduction region 64.

Floater area 24 and bulk substrate are insulated by buried layer 22, and insulating barrier 26 will be located between adjacent storage units 150 Floater area 24 insulate.Door 60 is placed in the surface of buoyancy aid 24.This door is positioned at first region 20 and Two Areas 20 Between.Insulating barrier 62 is had, in order to door 60 and buoyancy aid 24 are insulated between door 60 and buoyancy aid 24.

Figure 121 C illustrates the example of the equivalent circuit of a storage arrays 180.Storage arrays 180 includes storing string 520a, store string 520b and some other storages is gone here and there.In Figure 121 C, storage element is aligned to grid, storage arrays 180 Trip can determine by WL electrode 70, and arrange and can be determined by BL electrode 74.Multiple storage elements 150 in each column are with series connection side Formula couples together, and is formed and stores string 520.Adjacent row are separated by the row of insulation layer, such as shallow trench insulation (STI).

The storage element operational circumstances that store string 520 is described below.It will be seen that this stores string 520 examples Operating principle with described above store string 500 operating principle similar.Wherein store the reverse biased electrode in string 520 76 can be used for carrying out keeping operation.In some example, store transistor (the i.e. storage element in Figure 121 A of string 520 ends 150a and 150n) may be designed to store the readings transistor of string 520, and be stored in associate buoyancy aid 24 (i.e. in Figure 121 A example it 24a and 24n) in electric charge fail read.

Refer to Figure 122, Figure 123 A and 123B read operation is described.Can be by applying the side of following bias condition Formula carries out read operation.The storage element 150c stored in string 520a is selected to be illustrated in this example: to selecting it Applying positive voltage on BL electrode 74, on selected WL electrode 70, the positive voltage of applying is higher than and executes on selected BL electrode 74 In addition positive voltage, applies no-voltage on selected SL electrode 72, applies no-voltage or positive voltage and to lining on BW electrode 76 No-voltage is applied on hearth electrode 78.As shown in Figure 123 A, unselected BL electrode 74 will keep no-voltage, unselected SL electrode 72 will keep no-voltage.Applying positive voltage on WL transmission electrode 70a, 70b, 70l, 70m and 70n, this positive voltage is higher than It is applied to the positive voltage (see Figure 122 and 123A to 123B) on the WL electrode 70c that selectes.WL transmission electrode is connected to transmission and stores On the door of unit, i.e. it is connected to unselected storage element (the i.e. Figure 122 on the storage element 150c that selectes by series system In 150a, 150b, 150l, 150m and 150n).Being applied to transmit the voltage transmission transistor to be guaranteed on storage element door can Connect, it is not necessary to consider the current potential of they floater areas.Needing to connect transmission storage element, reason is in series system, electricity Flowing and flow to SL electrode 72 (or flowing to BL electrode 74 from SL electrode 72) from BL electrode 74, therefore electric current can flow through each and store list Unit 150.Therefore, the storage that the current potential that transmission storage element can be applied on SL electrode 72 and BL electrode 74 is delivered to select is single The source area 20b and drain region 20c of unit 150c.Such as, the voltage transmission that storage element 150n can be applied on BL electrode 74 Give the region 20m being connected to storage element 150n (and 150m).This voltage can be passed to be connected to by storage element 150m subsequently Region 201 on storage element 150l, etc..Adjacent transmission storage element can transmit the electricity being applied on BL electrode 74 subsequently Pressure, until this voltage reaches the region 20c of selected storage element 50c.

In specific non-limiting example, in selected storage element 150, apply following bias condition: to SL electricity Apply the current potential of about 0.0 volt on pole 72, on BL electrode 74, apply the current potential of about+0.4 volt, to selected WL electrode Apply the current potential of about+1.2 volts on 70, on WL transmission electrode 70, apply the current potential of about+3.0, execute on BW electrode 76 Add the current potential of about 0.0 and on underlayer electrode 78, apply the current potential of about 0.0 volt.And following bias condition is applied to not On selected electrode: apply about 0.0 volt of current potential on SL electrode 72, apply about 0.0 volt of current potential on BL electrode 74, To WL electrode 70 (non-WL transmits electrode) about 0.0 volt of current potential of upper applying, on BW electrode 76, apply about 0.0 volt of current potential (or on BW electrode 76, applying+1.2 volts of current potentials, to keep the state of unselected storage element) on underlayer electrode 78 Apply about 0.0 volt of current potential.Figure 123 A to 123B illustrate in storage arrays 180 the unselected storage element of selected sum it Bias condition.But, these voltage levels may be varied from.

Under these conditions, applying about+1.2 volts voltages to door 60c, 0.00 volt and 0.4 volt of voltage can be distinguished It is passed in the region 20b and region 20c of storage element 150c selected, is similar to the readout condition shown in Figure 117.As front Literary composition is described, and transmission storage element is in bias state, in order to its channel can conduct electricity.Therefore, from BL electrode 74 He storing string 520 The electric current of SL electrode 72 outflow depends on the current potential of the floater area 24 of the storage element 150c selected.If at storage element 150c In state " 1 ", and there is hole in floater area 24, compared with being in state " 0 ", floater area 24 do not exists the storage in hole Unit 150c, by relatively low, correspondingly electric current is relatively for the threshold voltage (i.e. the gate voltage when transistor is switched on) of this storage element High.

As shown in Figure 123 B, the reading circuit 90 being fixed on BL electrode 74 is next used to flow to SL to from BL electrode 74 The electric current of electrode 72 measures or detects.As shown in Figure 123 B, by by storing state and reference generator circuit 92 The reference value that (being connected to store on the reference cell in string 520R) is produced compares and may determine that storing state.

With reference to Figure 124 to 125, write " 0 " operation is described, applies following bias condition: apply zero to SL electrode 72 Voltage, applies no-voltage to WL electrode 70, applies negative voltage to BL electrode 74, and BW electrode 76 and underlayer electrode 78 are grounded. Under these conditions, during storage is gone here and there, the p-n joint between buoyancy aid 24 and the region 20 of each storage element is forward bias, it is to avoid There is hole in buoyancy aid 24.In specific non-limiting example, apply about-1.2 volts voltages to electrode 74, to electrode 70 apply about 0.0 volt of voltage, and apply about 0.0 volt of voltage on electrode 72,76 and 78.Can also be to WL electrode 70 Upper applying positive voltage, it is ensured that be applied to the negative voltage on BL electrode 74 and can be delivered to store storage elements all in string 520.So And, as it was noted above, these voltage levels may be varied from when keeping applying the relativeness between electric charge.

Another write " 0 " operation allows to carry out single position write, refers to Figure 126 to 127.Concrete grammar is to BL Apply negative voltage on electrode 74, on SL electrode 72, apply no-voltage, on BW electrode 76, apply no-voltage, to underlayer electrode 78 Upper applying no-voltage also applies positive voltage to WL transmission electrode.First selected WL electrode is carried out ground connection, until being applied to SL Voltage on electrode 72 and BL electrode can arrive separately at the region 20b and region 20c of selected storage element 150c.Subsequently, will The current potential of selected WL electrode 70 is increased to positive voltage, and guarantees to be higher than the positive voltage being applied on WL transmission electrode.At this Under the conditions of Xie, the goalkeeper of selected storage element (i.e. storage element 150c in Figure 126 to 127) can be applied in positive voltage, with Rear buoyancy aid 24 current potential will have been raised on the basis of the positive voltage being applied on WL electrode 70 by Capacitance Coupled.Transmission storage The negative voltage that memory cell (i.e. storage element 150l, 150m and 750n) is applied on BL electrode 74 passes to storage element 150c Region 20c, and transmit the no-voltage that storage element 150a and 150b be applied on SL electrode 72 and pass to storage element The region 20b of 150c, is similarly to the condition shown in Figure 119.Owing to buoyancy aid 24 current potential raises and is applied on BL electrode 74 it The reason of negative voltage, the p-n joint between buoyancy aid 24c and region 20c is forward bias, it is to avoid hole occur in buoyancy aid 24.Want Reduce unnecessary write " 0 " interference of other storage elements 150 in storage arrays 180, be in following manner to applying Current potential be optimized: if buoyancy aid 24 current potential of state " 1 " is referred to as VFB1, then the electricity that is applied on WL electrode 70 of reply Pressure configures, and so that the current potential of buoyancy aid 24 is increased VFB1/2, and the current potential being applied on BL electrode 74 is-VFB1/2.To executing The voltage being added to transmit the WL electrode of storage element is optimized, it is ensured that have sufficiently high voltage to be passed by the negative voltage of applying It is delivered on BL electrode 74；But voltage can not be too high, to avoid the electromotive force transmitting the buoyancy aid 24 of storage element to become too high, so Can avoid, in the transmission storage element being in state " 1 ", hole occurs.The no-voltage of applying is passed to SL electrode 72 (ascend the throne WL on the left of selected WL electrode 70c transmits electrode, 70a and 70b as in Figure 126) WL transmission electrode on be applied in it Positive voltage is higher than and the negative voltage of applying passes to BL electrode 74 (is i.e. positioned at the WL transmission electricity on the right side of selected WL electrode 70c Pole) WL transmission electrode on the voltage that is applied in.Reason is, compared with the negative voltage being applied on electrode 74, is applied to electricity Voltage on pole 72 is higher, it may be necessary to higher transfer gate voltage, in order to connected by transmission transistor.

In specific non-limiting example, apply following bias condition to storing in string 520: execute on SL electrode 72 Add the current potential of about 0.0 volt, on BL electrode 74, apply the current potential of about 0.2 volt, apply big on selected electrode 70 The current potential of about+0.5 volt, applies the current potential of about+0.2 on WL transmission electrode 70, applies about 0.0 volt on BW electrode 76 The current potential of spy, and on underlayer electrode 78, apply the current potential of about 0.0 volt.Apply about on unselected SL electrode 72 0.0 volt of current potential, applies about 0.0 volt of current potential on unselected BL electrode 74, applies about 0.0 volt on BW electrode 76 Special current potential (or on BW electrode 76, apply+1.2 volts of current potentials, and make unselected storage element carry out keeping operation), to WL electricity Pole 70 (non-WL transmits electrode) is upper applies about 0.0 volt of current potential, and applies about 0.0 volt of current potential on underlayer electrode 78. Figure 126 to 127 illustrates the bias condition of the storage element that selected sum is unselected, wherein storage element in storage arrays 180 150c is selected storage element.But, these voltage levels may be varied from.

Under these bias conditions, on the door 60 of selected storage element 150c, apply positive voltage, and be applied to BL electricity Negative voltage on pole 74 will be passed in the region 20c of storage element 150c selected, zero electricity being applied on SL electrode 72 Pressure will be passed in the region 20b of storage element 150c selected.This condition is similar to the condition described in Figure 119, can keep away Exempt from that hole occurs in the buoyancy aid 24 of storage element 150c.

Use band that band is worn mechanism then and write the bias condition model of storage element 150 selected in " 1 " operating process Example is shown in Figure 128 and 129.On selected WL electrode 70, apply back bias voltage, on WL transmission electrode 70, apply positive voltage, to SL electricity Pole 72 applies no-voltage, applies positive bias on BL electrode 74, applies zero-bias, and underlayer electrode 78 is connect on BW electrode 76 Ground.These conditions cause occurring sky on the buoyancy aid 24 of selected storage element (the storage element 150c during i.e. Figure 128 is to 129) Cave is injected.

In specific non-limiting example, in selected storage element 150c, apply following bias condition: to SL Apply the current potential of about 0.0 volt on electrode 72, on BL electrode 74, apply the current potential of about+1.2 volts, to selected WL electricity Apply the current potential of about-1.2 volts on pole 70, on WL transmission electrode 70, apply the current potential of about+3.0, on BW electrode 76 Apply the current potential of about 0.0 and on underlayer electrode 78, apply the current potential of about 0.0 volt.And following bias condition is applied to On unselected electrode: apply about 0.0 volt of current potential on SL electrode 72, on BL electrode 74, apply about 0.0 volt of electricity Position, to WL electrode 70 (non-WL transmits electrode) about 0.0 volt of current potential of upper applying, applies about 0.0 volt on BW electrode 76 Current potential (or applying+1.2 volts of current potentials on BW electrode 76, to keep the state of unselected storage element) to underlayer electrode About 0.0 volt of current potential is applied on 78.It is partially that Figure 129 illustrates the storage element that in storage arrays 180, selected sum is unselected Press strip part, wherein storage element 150c is selected storage element.But, these voltage levels may be varied from.

Under these bias conditions, on the door 60 of selected storage element 150c, apply negative voltage, and be applied to BL electricity Positive voltage on pole 74 will be passed in the region 20c of storage element 150c selected, zero electricity being applied on SL electrode 72 Pressure will be passed in the region 20b of storage element 150c selected.This condition is similar to the condition described in Figure 120 A, can keep away Exempt from that the buoyancy aid 24 of storage element 150c occurs that hole is injected.

The bias condition example of storage element 150 selected in ionization by collision write " 1 " operating process is shown in Figure 130 A extremely 130B.On selected WL electrode 70, apply positive bias, apply, on WL transmission electrode 70, the WL electrode 70 that ratio is applied to select The positive voltage that upper positive voltage is higher, applies no-voltage on SL electrode 72, applies positive bias on selected BL electrode 74, to Apply no-voltage on BW electrode 76, and underlayer electrode 78 is grounded.These conditions cause at selected storage element (i.e. Figure 130 A Storage element 150c to 130B) buoyancy aid 24 on occur that hole is injected.

In specific non-limiting example, in selected storage element 150c, apply following bias condition: to SL Apply the current potential of about 0.0 volt on electrode 72, on BL electrode 74, apply the current potential of about+1.2 volts, to selected WL electricity Apply the current potential of about+1.2 volts on pole 70, on WL transmission electrode 70, apply the current potential of about+3.0, on BW electrode 76 Apply the current potential of about 0.0 and on underlayer electrode 78, apply the current potential of about 0.0 volt.And following bias condition is applied to On unselected electrode: apply about 0.0 volt of current potential on SL electrode 72, on BL electrode 74, apply about 0.0 volt of electricity Position, to WL electrode 70 (non-WL transmits electrode) about 0.0 volt of current potential of upper applying, applies about 0.0 volt on BW electrode 76 Current potential (or applying+1.2 volts of current potentials on BW electrode 76, to keep the state of unselected storage element) to underlayer electrode About 0.0 volt of current potential is applied on 78.The storage element that in Figure 130 B show storage arrays 180, selected sum is unselected is partially Press strip part, wherein storage element 150c is selected storage element.But, these voltage levels may be varied from.

Utilization is alternately written into and can carry out multistage write operation with verification algorithm, is first applied to write pulse store On unit 150, carry out write operation the most again, to verify whether to reach the storing state of expection.If being also not reaching to pre- The storing state of phase, applies new write pulse on storage element 150, carries out write verification operation the most again.Repeat into The above operation of row, until reaching the storing state of expection.

Such as, utilize band that band hot hole is injected, apply positive voltage to BL electrode 74, on SL electrode 72, apply zero electricity Pressure, applies negative voltage on selected WL electrode 70, applies positive voltage, apply zero electricity on BW electrode 76 on WL transmission electrode Pressure, and on underlayer electrode 78, apply no-voltage.The positive voltage of different amplitude is applied, in order in buoyancy aid 24 on BL electrode 74 The state of write difference.So may result in the floating body potential 24 of difference, from different positive voltage or have been applied to BL electrode 74 Upper positive voltage pulse quantity is corresponding.In specific non-limiting example, write by applying following bias condition Enter operation: on SL electrode 72, apply the current potential of about 0.0 volt, apply on selected WL electrode 70 about-1.2 volts it Current potential, applies the current potential of about+3.0 on WL transmission electrode 70, applies the current potential of about 0.0 volt on BW electrode 76, and Applying the current potential of about 0.0 volt on underlayer electrode 78, being simultaneously applied to the current potential on BL electrode 74 will be incremented by.Such as, In non-limiting example, first apply 25 millivolts of current potentials to BL electrode 74, carry out subsequently reading verification operation.If the read out Verification operation show storage element electric current reached expection state (storage element electric current reached with 00,01,10 or 11 shapes The state that state is corresponding), then multistage write operation can be terminated.If not yet reaching the state of expection, then applying should be improved Voltage on BL electrode 74.Such as bring up to 50 millivolts from 25 millivolts.Followed by once reading verification operation, and repeat Operate this process, until it reaches the state of expection.But, above-mentioned voltage level may be varied from.After write operation Carry out read operation, to verify storing state.

Store string 520 to be made up of multiple plane storage elements, the such as example shown in Figure 23 and 121A；Also can be by fin Type three-dimensional storage unit forms, such as the example shown in Figure 32 to 33.It can also be changed, change or use replacement Storage element 150, without departing from the scope of the invention and functional.

Figure 131 A to 131B illustrates the another one example of storage arrays 880.Wherein 131A illustrates storage arrays The top view of 880.Storage arrays includes two storage strings of the storage element 540 between SL electrode 72 and BL electrode 74. Figure 131 B show stores the cross-sectional view of string 540.Although Figure 131 B stores string to schematically illustrate one containing two Array, but it may be noted that be, the invention is not limited in two store string.Reason is can also be in above-mentioned mode equally Make one or more and store string.

Each storage string 540 of storage arrays includes multiple storage elements 850 of being connected in NAND structure, wherein these Storage element 850 couples together in a series arrangement, forms one of storage element and stores string.Store string 540 and include " n " individual storage Unit 850, wherein " n " is positive integer, generally between 8 and 64.In one example, n at least will be equal to 16.But, just As above-mentioned example is not limited to described scope, one stores string and potentially includes less than 8 storage elements, and also having can Can include more than 64 storage elements.The region 18 being positioned at the second conduction type storing string one end is connected to by contact 73 On BL electrode 74, and the source region 16 being positioned at the second conduction type storing string other end is connected to SL by contact 71 On electrode 72.In some example, the transistor (i.e. storage element 850a and 850n in Figure 131 B) storing string 540 ends can It is designed to store the reading transistor of string 540, and is stored in association buoyancy aid 24 (i.e. 24a and 24n in Figure 131 B example) it Electric charge fails to read.

In Figure 131 B, storage element 850 can include the substrate 12 of the first conduction type, such as p-substrate.Substrate 12 leads to Make frequently with silicon material, and be also possible to containing other materials, such as germanium, SiGe, GaAs, carbon nanotubes or other it Semi-conducting material.Substrate 12 comprises the buried layer 22 of the second conduction type, such as N-shaped.Can be by ion injecting process at substrate Buried layer 22 is formed on the material of 12.Or, it is also possible to formed buried by the mode carrying out epitaxial growth at substrate 12 top Layer 22.

The floater area 24 of the first conduction type (such as N-shaped) is by the second conductivity type regions 16 (or region 18, or region 20) it is fixed on top.Insulating barrier 62 is fixed on side by the second conductivity type regions 16 (or region 18, or region 20).Insulation Layer 30 and 26 (such as shallow trench insulation (STI)) can use silicon dioxide material as shown in Figure 131 B, and the second conduction type is absolutely Edge layer 30 and region 16 (or region 18, or region 20) make the floater area 24 on I-I ' direction insulate；As shown in Figure 131 A, insulation Layer 28 makes the buoyancy aid 24 on II-II ' direction insulate.

The region 16,18 and 20 using the second conduction type (such as N-shaped) is there is on substrate 12.These regions are exposed to table On face 14.According to current industry known and the ion implantation technology of generally employing, composition substrate 12 material on take from Sub-injection technology forms region 16,18 and 20.Or, it is also possible to take solid-state diffusion method to form region 16,18 and 20.Although district Territory 16,18 and 20 has identical conduction type (such as N-shaped), and the doping content forming these regions can (but not necessarily) Different.In Figure 131 A and 131B, region 16 and region 18 are positioned at the one end storing string 540, and region 20 is positioned at storage string 540 Internal, the floater area 24 closed in the storage element 850 that will close on insulate.

Door 60 is placed in the surface of buoyancy aid 24.This door is positioned at first region 20 and Two Areas 20 (or district Territory 16 and region 20 or region 18 and region 20) between.Insulate with floater area 24 by this door 60 of insulating barrier 62.

The material of insulating barrier 62 may select silicon dioxide and/or other dielectric material, such as high-k material, bag Include but be not limited only to peroxidating tantalum, titanium oxide, zirconium oxide, hafnium oxide and/or aluminium oxide.The material of door 60 may select polysilicon Material or metal gate electrode, such as tungsten, tantalum, titanium and their nitride.

Store string 540 also to include being connected electrically to door 60 zigzag (WL) terminal 70, be connected electrically to the source row in district 16 (SL) terminal 72, are connected electrically to bit line (BL) terminal 74 in district 18, are connected to buried regions (BW) terminal 76 and the electricity of buried regions 22 Gas connects the substrate terminal 78 of substrate 12.

The BW terminal 76 being connected to buried regions district 22 plays the effect of a feedback bias voltage terminal, is i.e. positioned at semiconductor transistor One of module backside terminal, generally at the opposite side of transistor gate.

The one manufacture method of memory array 880, is described introduction in Figure 132 A～132U.These figures are correlated with three kinds Organizing form arrangement more than view, often first figure of group is the top view of internal storage location 850, and often second figure of group is this group I-I ' the The vertical cross-section of top view in one figure, and often organizing the 3rd figure is that the vertical of top view in this group II-II ' first figure cuts Face.

Figure 132 A～132C, the initial step of this technique can be from the beginning of one thick conduction region 202 of development, by constituting substrate zone Different materials composition planted by one of 12 materials.Etch to conduction region 202 property of can be chosen, and do not remove substrate zone 12.Such as, Conduction region 202 can be made up of SiGe (SiGe) material, and substrate 12 is then made up of silicon, although the material of these layers has difference.

Shown in Figure 132 D～132F, an overlay area and become pattern 30 ' (Figure 132 S～132U of insulator region 30 Shown in final structure figure) formed by photoetching process.Then conduction region 202 is etched according to photoengraving pattern.

Figure 132 G～1321, the conduction region 204 being made up of the same material such as forming substrate 12 (just as, such as silicon one Sample) growth.Then built up membrane is ground by carrying out chemical mechanical milling tech, it is ensured that the flatness of silicon face.With After, a thin layer of silicon dioxide layer 206 is grown on the surface of thin film 204.It is the precipitation of polysilicon layer 208 subsequently, is finally The precipitation of silicon nitride layer 210.

It follows that form a pattern, become insulator region 28 for opened areas.This pattern can pass through photoetching process shape Become.Dry ecthing order is followed successively by: silicon nitride layer 210, polysilicon layer 208, silicon dioxide layer 206 and silicon layer 204, excavates irrigation canals and ditches Shown in 212, Figure 132 J and 132L (irrigation canals and ditches 212 do not embody in Figure 132 K view).

It is then carried out a kind of selectivity and removes the wet etching process in district 202, stay by the gap of district 204 mechanical support.So After the interstitial area of synthesis aoxidized form embedding zoneofoxidation 30, as shown in Figure 132 N and 132O.Then by the silicon nitride layer of residue 210, polysilicon layer 208 and silicon dioxide layer 206, removed by silicon oxide deposition technique and chemical mechanical milling tech, Thus polish the silica membrane of synthesis, ultimately form silicon dioxide dielectric district 28, as shown in Figure 132 M and 132O.Or Person, can use siliceous deposits technique before removing silicon nitride layer 210, polysilicon layer 208 and silicon dioxide layer 206.

Figure 132 P and 132R, next uses a kind of ion implantation technology to form buried layer district 22.Then, a titanium dioxide Silicon layer (or high dielectric material layer) 62 is formed on a silicon surface (Figure 132 Q～132R), is polysilicon (or metal) layer 214 subsequently Deposition (Figure 132 Q～132R).

Next make an overlay area and be made into the pattern of door 60, by such as photoetching process method.Pattern is formed Step is polysilicon (or metal) layer 214 and the dry etching steps of silicon dioxide (or high dielectric material) layer 62 after completing.Then Carry out ion implanting thus form the district 20 of the second conductivity type (such as n-type).It is positioned at the conduction region below a district 60 204 impacts being protected from ion implantation technology, and on present Ze You district 20, limit, insulating barrier 30 and insulating barrier 28 surround, and The buried layer 22 of substrate 12 and the insulating barrier 62 on surface constitute floater area 24 (see Figure 132 T).Subsequently for forming contact and gold Belong to the backend process (not having embodiment in figure) of layer.

Another embodiment of memory array, then be the memory array 980 shown in Figure 133, and wherein memory array 980 is by one The link composition of the multiple internal storage location 950 in parallel of individual connection.Figure 134 A is the top view of isolation internal storage location 950, and Figure 134 B Then being respectively with 134C, internal storage location 950 is along the sectional view of circuit I-I ' and II-II '.

Figure 134 B and 134C, unit 950 is the silicon on insulator in the first conductivity type, such as p-type (SOI) it is assembled on substrate 12.Substrate 12 is made by silicon is special, but also can be by such as germanium, germanium silicon, GaAs, CNT Form Deng semi-conducting material.Substrate 12 then has buried insulator layer 22, such as buried oxide (BOX).

The floater area 24 of the first conductivity type such as p-type, draws an analogy, and is to be surrounded by insulating barrier 62 up, side District 20 and insulating barrier 26 by the second conductivity type surround, and bottom is surrounded by buried layer 22.Insulating barrier 26 (just as, such as Shallow trench isolation (STI)) can be made up of the material of silicon dioxide etc.When multiple unit 950 concentrate on an array 980 and shape When becoming memory element, unit 950 will be isolated by insulating barrier 26 with adjacent unit 950, the explanation of Figure 133 and 135.

There is the district 20 of the second conductivity type such as n-type, draw an analogy, be present in substrate 12, and be exposed to surface 14.According to any known and injection technology of art Special use, district 20 is formed at composition lining by injection technology Above the material at the end 12.Or, form district 20 by solid state diffusion process.

Door 60 is positioned on floater area 24 and district 20.Door 60 is isolated with floater area 24 by an insulating barrier 62.Insulating barrier 62 Material can be silicon dioxide and/or other dielectric materials, including high-k dielectric material etc., but is not limited only to, peroxidating tantalum, oxidation Titanium, zirconium oxide, hafnium oxide and/or aluminium oxide.Door 60 can be by, such as polycrystalline silicon material or metal gate electrode, as tungsten, tantalum, titanium and Its nitride is made.

District 20 is continuously it (conductivity) (see Figure 134 A) along II-II ' direction, and can be used to connect multiple internal memory in parallel Unit 950, is shown in that shown in the equivalent circuit representation of memory array 980 in Figure 47 and 49, (wherein, district 20 is connected to bit line (BL) eventually End 74).Connection between district 20 and bit line (BL) terminal 74a and 74b, can the contact 73 at edge in parallel realize (see figure 133).A pair neighbouring continuum 20 can be used to a joint unit 950 in parallel.Unit 950 also includes the word being connected electrically to door 60 Line (WL) terminal 70 and the substrate terminal 78 (see Figure 134 B～134C) being connected electrically to substrate 12.In a certain parallel connection, apply All almost (may be led due to the pressure drop around bit line greatly by the voltage on all internal storage location 950 surfaces in BL terminal 74 Cause little difference), and electric current only flows through the internal storage location 950 of selection.

Because only connecting at edge in parallel, it is possible to reduce the connection number being connected to BL terminal to greatest extent, so Can reduce the quantity of contact, the most each parallel connection is reduced to two contacts.Exactly because in memory array 980, not on limit in parallel Internal storage location 950 district 20 of edge does not has contact, just causes not at the contactless internal storage location of edge (end) position.Number of contacts Can increase, to reduce the resistance of parallel connection, if the words of needs.

The relevant read operation of Figure 136-137 illustrates, wherein internal storage location 950b selected (as shown in Figure 136).Can apply Following bias condition a: positive voltage is applied to BL terminal 74b, no-voltage is applied to BL terminal 74c, and a positive voltage is applied to WL terminal 70b, no-voltage is applied to substrate terminal 78.Unselected BL terminal (BL terminal 74a in such as Figure 136, 74d ..., 74p) floated, the WL terminal (WL terminal 70a in such as Figure 136,70m, 70n) of selection not will be maintained at zero Voltage, unselected substrate terminal 78 will be maintained at no-voltage.Or, BL terminal (no-voltage unselected on the right side of BL terminal 74c The position applied) can be with ground connection.One same-amplitude positive voltage being applied to BL terminal 74b, can be applied to be positioned at BL terminal Unselected BL terminal on the left of 74b.Because this district 20b (is connected to BL terminal 74b), sharing with adjacent unit 950a, BL is eventually Unselected BL terminal (position of a certain positive voltage applying) on the left of end 74b needs to float, or has positive voltage to apply, to prevent from appointing What parasite current BL terminal on the left of BL terminal 74b flows to BL terminal 74b.Or, BL terminal 74b and 74c (are connected to choosing Determine the district 20 of internal storage location 950b) bias condition be likely to be obtained torsion.

In a specific unrestricted embodiment, below bias condition be applied to the internal storage location 950b that selectes Upper: the voltage of about 0.4 volt acts in BL terminal 74b, and the voltage of about 0.0 volt acts in BL terminal 74c, about+1.2 volts The voltage of spy acts in WL terminal 70b, and the voltage of about 0.0 volt acts in substrate terminal 78, and following bias condition It is applied to those not selected terminals: the voltage of about 0.0 volt acts in unselected WL terminal, the electricity of about 0.0 volt Pressure acts in unselected substrate terminal, and unselected BL terminal is then floated.

Shown in Figure 137, the voltage of about+1.2 volts acts on a 60b, and the voltage of about+0.4 volt acts on district 20b (being connected in BL terminal 74b), the voltage of about 0.0 volt acts on district 20c (being connected in BL terminal 74c), about 0.0 volt it Voltage acts on the substrate 12 of selected memory unit 950b.The size of current of BL terminal 74c is flowed to then by selecting from BL terminal 74b The voltage of cell 950b floater area 24 is determined.

When there being state " 1 " in hole during unit 950b is in floater area 24, then internal storage location then have one relatively low Threshold voltage (gate voltage when transistor is opened), and without passing during state " 0 " in hole in unit 950b is in floater area 24 Lead one and compare bigger electric current.Cell current can be by, and the sense amplifier circuit being such as connected to BL terminal 74b is sensed.

Figure 138-～139 is relevant writes " 0 " operating instruction, wherein applies following bias condition: no-voltage acts on WL eventually End 70, negative voltage acts on BL terminal 74b, substrate terminal 78 then ground connection.Under these conditions, the buoyancy aid of internal storage location 950 Any p-n junction between 24 and district 20b is positive bias, empties any hole from buoyancy aid 24.Unselected BL terminal 74 can be floated Or ground connection, unselected WL terminal 70 maintains no-voltage, and unselected substrate terminal 78 maintains no-voltage.

In a specific unrestricted embodiment, the voltage of about-1.2 volts acts in terminal 74b, about 0.0 volt The voltage of spy acts in terminal 70, and the voltage of about 0.0 volt acts in terminal 78.Despite this, these magnitudes of voltage can be with Changing and change, and maintain the relativeness between applied electric charge, see above description.Owing to BL terminal 74b is connected to multiple On internal storage location 950, all internal storage locations being connected to BL terminal 74b, then it is written to state " 0 ", sees in Figure 138 in dotted line frame Memory cell indicates.

Another is available and allows more multi-selection position to write it, writes " 0 " operation, sees Figure 140～141 explanation, and leads to Cross and apply negative voltage in BL terminal 74b, apply no-voltage in substrate terminal 78, and apply the mode of positive voltage in WL terminal 70b Realize.Unselected WL terminal can maintain no-voltage, and unselected BL terminal is then floated or ground connection, and unselected substrate is eventually End 78 then maintains no-voltage.

Under these conditions, a positive voltage is acted on the (internal storage location in such as Figure 140 on the door of selected memory unit 950a and 950b, is shown in the door 60b in Figure 141 simultaneously), buoyancy aid 24 voltage will pass through from the positive voltage acting on WL terminal 70 subsequently Capacitance Coupled increases.Increase due to buoyancy aid 24 voltage and apply negative voltage, the p-n junction between 24 and district 20b in BL terminal 74b Point is positive bias, empties any hole from buoyancy aid 24.By reducing in memory array 980, other internal storage locations 950 are brought Unnecessary write " 0 " trouble, the voltage acted on can optimize as follows: when state " 1 " buoyancy aid 24 voltmeter is shown as V_FB1, then make The voltage being configurable to increase buoyancy aid 24 for selecting the voltage of WL terminal 70 is V_FB1/ 2, and-V_FB1/ 2 act on BL eventually On end 74b.Under these conditions, internal storage location 950a and 950b can be written as state " 0 " (contrast above-mentioned before write " 0 ", its Cause all internal storage locations to share same BL terminal 74b and be written as state " 0 ").

In a specific unrestricted embodiment, below bias condition be applied on internal storage location 950: about-0.2 The voltage of volt acts in BL terminal 74b, and the voltage of about+0.5 volt acts in WL terminal 70b, the voltage of about 0.0 volt Acting in substrate terminal 78, unselected BL terminal 74 is then floated, and the voltage of about 0.0 volt acts on unselected WL eventually The voltage holding 70, about 0.0 volt acts in unselected terminal 78.Figure 140 gives in memory array 980 selected and unselected The bias condition of internal storage location, and internal storage location 950a and 950b is selected unit.While it is true, these magnitudes of voltage can be with change And change.

Figure 142～143, bias condition one example on the relevant next selected memory unit 950b of ionization by collision one writing operation Introduction explanation.One positive bias acts in selected WL terminal 70b, and no-voltage acts in BL terminal 74c, positive bias effect In BL terminal 74b, substrate terminal 78 then ground connection.This condition creates a transverse electric field, it is sufficient to generate high energy electron, thus Generate electron-hole pair, be followed by injected into selected memory unit (the unit 950b in such as Figure 142～143) for hole floating On body 24.Unselected WL terminal (WL terminal 70a in such as Figure 142,70c, 70m and 70n) ground connection, unselected BL terminal (example Such as BL terminal 74a in Figure 142,70d, 70m, 70n, 70o and 70p) float, unselected substrate terminal 78 also ground connection.Or, BL Unselected BL terminal (position that no-voltage is applied) on the right side of terminal 74c can ground connection.One is applied to the identical of BL terminal 74b Amplitude positive voltage can be applied to the unselected BL terminal being positioned on the left of BL terminal 74b.Because this district 20b (is connected to BL terminal 74b), sharing with adjacent unit 950a, the unselected BL terminal (position of a certain positive voltage applying) on the left of BL terminal 74b needs Float or have positive voltage to apply, to prevent any parasite current from flowing to the BL terminal on the left of BL terminal 74b from BL terminal 74b On, bring unnecessary one writing to operate can to most probably the unselected internal storage location 950 of at least one.

In a specific unrestricted embodiment, below bias condition be applied to the internal storage location 950b that selectes Upper: the voltage of about 0.0 volt acts in BL terminal 74c, and the voltage of about+1.2 volts acts in BL terminal 74b, about+1.2 The voltage of volt acts in WL terminal 70b, and the voltage of about 0.0 volt acts in substrate terminal 78, and following bias strip Part is applied to the terminal that those are not selected: the voltage of about 0.0 volt acts on (such as Figure 142 in unselected WL terminal 70 In WL terminal 70a, 70m and 70n), the voltage of about 0.0 volt acts in unselected substrate terminal 78, and unselected it BL terminal 74 (BL terminal 74c in such as Figure 142,74d, 74m, 74n, 74o and 74p) is then floated.Figure 142～143 gives Selected and the bias condition of unselected internal storage location in memory array 980 (there is as selected unit internal storage location 950b). While it is true, these magnitudes of voltage can change with change.Or, BL terminal 74b and 74c (are connected to selected memory unit 950b District 20 on) bias condition be likely to be obtained torsion.

Figure 144 schematic diagram mode describes, according to the memory array of another embodiment of the present invention.Memory array 1080 is wrapped Include multiple internal storage location 1050.Figure 145 A is the top isolated views of internal storage location 1050, and Figure 145 B and Figure 145 C is then for respectively Sectional view along the internal storage location 1050 of Figure 145 A circuit I-I ' and II-II '.

Figure 145 B and 145C, unit 1050 includes the substrate 12 of the first conductivity type such as p-type.Substrate 12 is general It is made up of silicon, but also can be made up of semi-conducting materials such as such as germanium, germanium silicon, GaAs, CNTs.Substrate 12 then has The buried layer 22 of the second conductivity type such as n-type.Buried layer 22 can be obtained by the ion implantation technology on substrate 12 material Arrive.Or, buried layer 22 also can be in substrate 12 top epitaxial growth.

The floater area 24 of the first conductivity type such as p-type, draws an analogy, and Shi You district 20 and insulating barrier 62 wrap up Enclosing, side is surrounded by insulating barrier 26, and bottom is surrounded by buried layer 22.Insulating barrier 26 (just as, such as shallow trench isolation (STI)) can It is made up of the material of silicon dioxide etc.When multiple unit 1050 concentrate on an array 1080 and form memory element Waiting, unit 1050 will be isolated with adjacent unit 1050, be seen that Figure 144 illustrates by insulating barrier 26.

There is the district 20 of the second conductivity type such as n-type, draw an analogy, be present in substrate 12, and be exposed to surface 14.According to any known and injection technology of art Special use, district 20 can be by constituting above substrate 12 material Injection technology formed.Or, form district 20 by solid state diffusion process.

Door 60 is positioned on floater area 24, district 20 and insulating barrier 26.Door 60 is isolated with floater area 24 by an insulating barrier 62. Insulating barrier 62 material can be silicon dioxide and/or other dielectric materials, including high-k dielectric material etc., but is not limited only to, peroxidating Tantalum, titanium oxide, zirconium oxide, hafnium oxide and/or aluminium oxide.Door 60 can be by, such as polycrystalline silicon material or metal gate electrode, as tungsten, Tantalum, titanium and its nitride are made.

District 20 is continuously it (conductivity) (see Figure 145 A) along II-II ' direction, and can be used to connect multiple internal memory in parallel Unit 1050, is shown in that shown in the equivalent circuit representation of memory array 1080 in Figure 144 and 146, (wherein, district 20 is connected to bit line (BL) terminal 74).Connection between district 20 and bit line (BL) terminal 74a and 74b can the contact 73 at edge in parallel realize (see Figure 144).A pair neighbouring continuum 20 can be used to a joint unit 1050 in parallel.In a certain parallel connection, it is applied to BL terminal 74 and leads to The voltage crossing all internal storage location 1050 surfaces is all almost big (may cause little difference due to the pressure drop around bit line), and Electric current only flows through the internal storage location 1050 of selection.Unit 1050 also includes being connected electrically to door 60 zigzag (WL) terminal 70, even Receive burying well (BW) terminal 76 and being connected electrically to the substrate terminal 78 (see Figure 145 B～145C) of substrate 12 of buried layer 22.

Because only connecting at edge in parallel, it is possible to reduce the connection number being connected to BL terminal to greatest extent, so Can reduce the quantity of contact, the most each parallel connection is two contacts.The internal storage location contact at edge in parallel not there is no need, because of For the unit that these contactless internal storage location Shi You districts 20 are continuously coupled.If the words of needs, number of contacts can increase, to subtract The resistance of few parallel connection.

Figure 147-148 illustrates about a certain example read operation of Figure 144-145C embodiment, and wherein internal storage location 1050b is selected In (as shown in Figure 147).Can apply following bias condition: a positive voltage is applied to BL terminal 74a, no-voltage is applied to BL eventually End 74b, a positive voltage is applicable to WL terminal 70b, and no-voltage is applied to substrate terminal 78, and no-voltage is applied to substrate terminal 78 On.Unselected BL terminal (BL terminal 74c in such as Figure 147,74d ..., 74p) will be maintained at no-voltage, do not select WL terminal (WL terminal 70a in such as Figure 147,70m, 70n) will be maintained at no-voltage, unselected BW terminal 76 will maintain No-voltage (or applying a positive voltage to keep the state of unselected internal storage location), unselected substrate terminal 78 will dimension Hold in no-voltage.Or, the bias condition of BL terminal 74a and 74b (being connected to the district 20 of selected memory unit 1050b) may obtain To reversing.

In a specific unrestricted embodiment, below bias condition be applied to the internal storage location 1050b that selectes Upper: the voltage of about+0.4 volt acts in BL terminal 74a, and the voltage of about 0.0 volt acts in BL terminal 74b, about+1.2 The voltage of volt acts in WL terminal 70b, and the voltage of about 0.0 volt acts in BW terminal 76, and the voltage of about 0.0 volt is made For substrate terminal 78, and following bias condition is applied to terminals that those are not selected: the voltage effect of about 0.0 volt In unselected BL terminal, the voltage of about 0.0 volt acts in unselected WL terminal, the voltage effect of about 0.0 volt In unselected BW terminal (or the voltage of+1.2 volts acts on the shape maintaining unselected internal storage location in BW terminal 76 State), and the voltage of about 0.0 volt acts in unselected substrate terminal.

Shown in Figure 148, the voltage of about+1.2 volts acts on and (is connected in terminal 70b) on a 60b, about+0.4 volt it Voltage acts on district 20a (being connected in BL terminal 74a), and the voltage of about 0.0 volt acts on district 20b and (is connected to BL terminal 74b On), the voltage of about 0.0 volt acts on buried layer 22, and the voltage of about 0.0 volt acts on, selected memory unit 1050b it On substrate 12.The size of current of BL terminal 74b is flowed to then by the voltage institute of selected unit 1050b floater area 24 from BL terminal 74a Determine.

When there being state " 1 " in hole during unit 1050b is in floater area 24, then internal storage location then have one relatively low Threshold voltage (gate voltage when transistor is opened), and in unit 1050b is in floater area 24 without state " 0 " in hole time, Conduct one and compare bigger electric current.Cell current can be sensed by circuit, and the reading being such as connected to BL terminal 74a is amplified Device.

Figure 149-～150 is relevant writes " 0 " operating instruction, wherein applies following bias condition: no-voltage acts on BL eventually End 74b, no-voltage acts on BL terminal 74b, and no-voltage acts on WL terminal 70, and negative voltage acts on BL terminal 74a, and BW is eventually End 76 and substrate terminal 78 then ground connection.Under these conditions, any p-n junction between buoyancy aid 24 and the district 20a of internal storage location 1050 For positive bias, from buoyancy aid 24, empty any hole.Unselected BL terminal 74 can be floated or ground connection, unselected WL terminal 70 Maintaining no-voltage, unselected substrate terminal 78 maintains no-voltage.In a specific unrestricted embodiment, about- The voltage of 1.2 volts acts in terminal 74a, and the voltage of about 0.0 volt acts in terminal 70, and the voltage of about 0.0 volt is made For terminal 76 and 78.While it is true, these magnitudes of voltage can change with change, and remain relative between applied electric charge Relation, see above description.Or, write the bias condition reality that " 0 " operation also can be applied in BL terminal 74a and 74b by reverse Existing.

Another " 0 " operation of writing that is available and that allow independent position to write is shown in that Figure 151～152 illustrates and passes through in BL terminal 74a applies negative voltage, applies no-voltage in BL terminal 74b, apply no-voltage in BW terminal 76, apply zero electricity in substrate terminal 78 Pressure and apply the mode of positive voltage in WL terminal 70 and realize.Under these conditions, a positive voltage is acted on selected memory unit Door on (the internal storage location 1050b in such as Figure 151-152), buoyancy aid 24 voltage will be from the positive electricity acting on WL terminal 70 subsequently Pressure is increased by Capacitance Coupled.Increase due to buoyancy aid 24 voltage and apply negative voltage in BL terminal 74a, between 24 and district 20a Any p-n junction be positive bias, from buoyancy aid 24 empty any hole.For reducing in memory array 1080 other internal storage locations 1050 unnecessary write " 0 " brought bother, and the voltage acted on can optimize as follows: when state " 1 " buoyancy aid 24 voltmeter is shown as V_FB1, then acting on the voltage of selected WL terminal 70 and being configurable to increase the voltage of buoyancy aid 24 is V_FB1/ 2, and-V_FB1/ 2 Act in BL terminal 74a.

In a specific unrestricted embodiment, below bias condition be applied on internal storage location 1050b: about The voltage of 0.0 volt acts in BL terminal 74b, and the voltage of about-0.2 volt acts in BL terminal 74a, about 0.5 volt it Voltage acts in selected WL terminal 70b, and the voltage of about 0.0 volt acts in BW terminal 76, and the voltage of about 0.0 volt is made For substrate terminal 78, and the voltage of about 0.0 volt acts in unselected BL terminal 74, and the voltage of about 0.0 volt is made For BW terminal 76 (or the voltage of+1.2 volts acts on and maintains the state of unselected internal storage location in BW terminal 76), about The voltage of 0.0 volt acts in unselected WL terminal 70, and the voltage of about 0.0 volt acts in unselected terminal 78.Figure 151-152 gives selected in the memory array 1080 and bias condition of unselected internal storage location, and internal storage location 1050b is choosing Cell.While it is true, these magnitudes of voltage can change with change.Or, write " 0 " operation, it is possible to be applied to BL by reverse Bias condition in terminal 74a and 74b realizes.

Carrying out band-to-band tunnelling one writing and operate it, a bias condition example, is shown in one of on selected memory unit 1050b Figure 153 and 154 explanations.Back bias voltage acts in selected WL terminal 70b, and no-voltage acts in BL terminal 74b, and positive bias is made For BL terminal 74a, no-voltage acts in BW terminal 76, substrate terminal 78 then ground connection.These conditions order about electron stream To BL terminal 74a, produce the hole being subsequently injected in floater area 24 going.

In a specific unrestricted embodiment, below bias condition be applied on internal storage location 1050b: about The voltage of 0.0 volt acts in BL terminal 74b, and the voltage of about+1.2 volts acts in BL terminal 74a, about-1.2 volts it Voltage acts in selected WL terminal 70b, and the voltage of about 0.0 volt acts in BW terminal 76, and the voltage of about 0.0 volt is made For substrate terminal 78；And bias condition below is applied in unselected terminal: the voltage of about 0.0 volt acts on not Selected BL terminal 74 (BL terminal 74c in such as Figure 153,74,74m, 74n, 74o and 74p), the voltage of about 0.0 volt is made For unselected WL terminal 70 (WL terminal 70a in such as Figure 153,70m and 70n), the voltage of about 0.0 volt acts on not Selected BW terminal 76 (or the voltage applying+1.2 volts maintains the state of unselected internal storage location), the electricity of about 0.0 volt Pressure acts in unselected substrate terminal 78.Figure 153-154 gives selected in memory array 1080 and unselected interior deposit receipt The bias condition of unit, and internal storage location 1050b is selected unit.While it is true, these magnitudes of voltage can change with change.Or Person, one writing operation also can be realized by the bias condition that reverse is applied in BL terminal 74a and 74b.

Carrying out ionization by collision one writing and operate it, a bias condition example, is shown in Figure 155 one of on selected memory unit 1050b With 156 explanations.One positive bias acts in selected WL terminal 70b, and no-voltage acts in BL terminal 74b, positive bias effect In BL terminal 74a, no-voltage acts in BW terminal 76, substrate terminal 78 then ground connection.These conditions produce a horizontal electricity , it is sufficient to generate high energy electron, thus generate electron-hole pair, be followed by injected into selected memory unit for hole and (such as scheme Unit 1050b in 155～156) buoyancy aid 24 on.

In a specific unrestricted embodiment, below bias condition be applied on internal storage location 1050b: about The voltage of 0.0 volt acts in BL terminal 74b, and the voltage of about+1.2 volts acts in BL terminal 74a, about+1.2 volts it Voltage acts in selected WL terminal 70b, and the voltage of about 0.0 volt acts in BW terminal 76, and the voltage of about 0.0 volt is made For substrate terminal 78；And bias condition below is applied in unselected terminal: the voltage of about 0.0 volt acts on not Selected BL terminal 74 (BL terminal 74c in such as Figure 155,74,74m, 74n, 74o and 74p), the voltage of about 0.0 volt is made For unselected WL terminal 70 (WL terminal 70a in such as Figure 155,70m and 70n), the voltage of about 0.0 volt acts on not Selected BW terminal 76 (or apply the voltage of+1.2 volts maintain the state of unselected internal storage location to BW terminal 76), about The voltage of 0.0 volt acts in unselected substrate terminal 78.Figure 155-156 gives memory array 1080 (such as selected list Unit equally has internal storage location 1050b) in the selected and bias condition of unselected internal storage location.While it is true, these magnitudes of voltage Can change with change.Or, the bias condition reality that one writing operation also can be applied in BL terminal 74a and 74b by reverse Existing.

Figure 157 describes another selection embodiment of memory array 1090, and wherein proximity 20 is by a conduction region 64 It is connected in a BL terminal 74 shared.Assemble on the operation of memory array 1090 and silicon on insulator (SOI) surface Memory array 980 operation be close it, wherein district 20 is shared between two neighbouring internal storage locations 950.

Figure 158 A describes another embodiment of memory array 1180.Memory array 1180 is by multiple internal storage locations 1150 groups Become.Figure 158 B describes isolation purgation internal storage location 1150, and Figure 158 C and 158D then gives, along line in Figure 158 B Road I-I ' and the sectional view of II-II ' internal storage location 1150.

Internal storage location 1150 includes the substrate 12 of the first conductivity type such as p-type.Substrate 12 is by the special system of silicon Become, but also can be made up of semi-conducting materials such as such as germanium, germanium silicon, GaAs, CNTs.Substrate 12 then there is the second pass The buried layer 22 of conductivity types, such as n-type.Buried layer 22 can be obtained by the ion implantation technology on substrate 12 material.Or Person, buried layer 22 also can be in substrate 12 top epitaxial growth.

The floater area 24 of the first conductivity type such as p-type, draws an analogy, and Shi You district 16 and insulating barrier 62 wrap up Enclosing, side is surrounded by insulating barrier 26 and 28, and bottom is surrounded by buried layer 22, sees Figure 158 C～158D.Insulating barrier 26 and 28 is (just Picture, such as shallow trench isolation (STI)) can be made up of the material of silicon dioxide etc.When multiple unit 1150 concentrate on a number When organizing 1180 and form memory element, unit 1150 and adjacent unit 1150 will be isolated by insulating barrier 26 and 28, see figure 158A explanation.Floater area 24 and the buried region 22 of adjacent unit are kept apart (see Figure 158 C) by insulating barrier 26, and insulating barrier 28 Then will adjacent to floater area 24 isolate, and do not include buried layer 22, it is allowed to buried layer 22 in same orientation (along Figure 158 D Shown in II-II ' direction) continuously (i.e. conductivity).

There is the district 16 of the second conductivity type such as n-type, draw an analogy, be present in substrate 12, and be exposed to surface 14.According to any known and injection technology of art Special use, district 16 can be by constituting above substrate 12 material Injection technology formed.Or, form district 16 by solid state diffusion process.District 16 is it (fax continuously along II-II ' direction Lead) (see Figure 158 B), and can be used to connect multiple internal storage location 950 in parallel, see the equivalent circuit of memory array 1180 in Figure 159 Shown in representation.

Between Men60 district 16 and insulating barrier 26, on floater area 24.Door 60 by insulating barrier 62 and floater area 24 every From, see Figure 158 C.Insulating barrier 62 material can be silicon dioxide and/or other non-conducting materials, including high K insulant Deng, but be not limited only to, peroxidating tantalum, titanium oxide, zirconium oxide, hafnium oxide and/or aluminium oxide.Door 60 can be by, such as polysilicon material Material or metal gate electrode, as tungsten, tantalum, titanium and its nitride are made.

Connection between bit line (BL) terminal 74a and district 16 and source line (SL) terminal 72a and buried layer 22 can be on limit in parallel Edge realizes.Unit 1150 also includes being connected electrically to door 60 zigzag (WL) terminal 70 and being connected electrically to the substrate of substrate 12 eventually End 78.District 16 (being connected to BL terminal 74) and buried layer 22 (being connected to SL terminal 72) can be used to a joint unit 1150 in parallel.? In a certain parallel connection, it is applied to SL the terminal 72 and BL terminal 74 voltage by all internal storage locations 1150, all almost big (due to Pressure drop around bit line and little difference may be caused), and electric current only flows through the internal storage location 1150 of selection.

Figure 159 is the equivalent circuit representation of memory array 1180, and plurality of internal storage location 1150 is connected in parallel.Because Only likely being connected to SL and BL terminal at edge in parallel, so the quantity of contact can be reduced, the most each parallel connection is reduced to only There are two contacts.Except the internal storage location 1150 at edge in parallel in memory array 1180, the district 16 and 22 of internal memory 1150 does not all have Contact connects.Therefore, those unit 1150 at marginal position in parallel are not all contactless internal storage locations.Certainly, the need to Words, number of contacts can increase, with reduce parallel connection resistance.

Figure 160 A is the equivalent circuit representation of internal storage location 1150, including one by burying wellblock 22, buoyancy aid 24 and district 16 The n-p-n dipole elements 30 of composition, door 60 is then coupled on floater area 24.

When grounding terminals 74, the positive feedback being acted on SL terminal 72 by application biases and utilizes n-p-n dipole elements The characteristic of 30 carries out preserving operation.If buoyancy aid 24 positively charged (i.e. state " 1 "), then open by BL district 16, buoyancy aid 24 and bury The bipolar transistor of wellblock 22 composition.

The sub-fraction electric current of bipolar transistor will flow into floater area 24 (commonly referred to " base current ") and keep shape State " 1 " data.Preserve operation and can be designed to low by the n-p-n dipole elements 30 being made up of buried region 22, buoyancy aid 24 and district 16 The mode of gain (i.e. as far as possible close to the 1.1 of reality) dipole elements improves efficiency, and what wherein bipolar gain referred to is to flow out SL terminal The collector current of 72, and the ratio flow between the base current of floater area 24.

For state " 0 " data purgation internal storage location, dipole elements 30 will not be opened, and base stage hole current is also subsequently May not flow into floater area 24.Therefore, state " 0 " purgation internal storage location can hold mode " 0 ".

Be applied to unit 1150 carry out preserve operation bias condition one example include: no-voltage acts on BL terminal 74 On, positive voltage acts in SL terminal 72, zero or negative voltage act in WL terminal 70, and no-voltage acts on substrate terminal 78 On.In a specific unrestricted embodiment, the voltage of about+1.2 volts acts in terminal 72, the electricity of about 0.0 volt Pressure acts in terminal 74, and the voltage of about 0.0 volt acts on middle lonely 70, and the voltage of about 0.0 volt acts on terminal 78 On.While it is true, these magnitudes of voltage are it may happen that change.

Figure 160 B is that floater area 24 is positively charged and positive bias voltage, acts on when burying wellblock 22, at n-p-n in Figure 160 B The energy band schematic diagram of dipole elements 30.Dotted line represents the fermi level in n-p-n transistor 30 different regions.According to this area institute Known it, fermi level is positioned at and represents and (can carry bottom the solid line 17 (bottom of band gap) at valance band top and expression conduction band Top, gap) solid line 19 between band gap in.Positive charge in floater area reduces the electron stream energy of base region Potential barrier.Once injecting floater area 24, act in positive bias and bury wellblock 22 times, electrons is swept into burying wellblock 22 and (is connected to SL Terminal 72).Due to positive bias, by ionization by collision mechanism, electronics accelerates and produces extra heat carrier (hot hole and a heat Electronics to).Thus the thermoelectron of generation flows into SL terminal 72, and the hot hole of generation simultaneously flows into floater area 24 the most therewith.This Charge-restoring on process floater area 24 is to maximum, and remains stored in the electric charge in floater area 24, thus by SL eventually End 72 keeps n-p-n bipolar transistor 30 to be in opening when burying and applying positive bias on wellblock 22.

If buoyancy aid 24 band neutral charge (i.e. the voltage of buoyancy aid 24 is substantially the same with the voltage on ground connection bit line 16), corresponding One of state " 0 " state, dipole elements will not open, and do not has base stage hole current can flow to floater area 24 subsequently.Therefore, State " 0 " purgation internal storage location can be maintained under state " 0 ".

Figure 160 C is floater area 24 band neutral charge, and bias voltage acts on when burying wellblock 22, at n-p-n in Figure 160 A The energy band schematic diagram of dipole elements 30.In this condition, by the energy level of solid line 17A and the band gap of 19A encirclement at n-p-n The different regions of transistor are differences.Because the voltage of floater area 24 and bitline regions 16 is substantially the same, fermi level is constant, Between bitline regions 16 and floater area 24, thus produce an energy barrier.Solid line 23 represents, in order to reference to mesh it, bitline regions 16 And the energy barrier between floater area 24.Energy barrier avoids electron stream to flow to buoyancy aid from bitline regions 16 (being connected to BL terminal 74) District 24.Therefore, n-p-n dipole elements 30 remains closed.

In order to carry out preserving operation, positive voltage period pulse can be applied to returning of internal storage location 1150 by SL terminal 72 On feedback bias voltage terminal, contrary with applying constant positive bias, thus reduce the power consumption of internal storage location 1150.

Although in order to describe, the dipole elements 30 in Figure 160 A to 160C embodiment illustrates as n-p-n transistor, Those of ordinary skill in the art can notify in time, by first and second kinds of conductivity type of conversion, and converts in applying voltage The relative value of memory cell 1150 just may make up the dipole elements 30 of a p-n-p transistor.Therefore, n-p-n transistor is selected to make For the illustrative example of explanation convenient in Figure 160 A to 160C, it is construed as limiting in no instance.

The relevant reading operations of Figure 161-162 illustrates, wherein internal storage location 1150b selected (as shown in Figure 161).Can apply Following bias condition a: positive voltage is applied to BL terminal 74a, no-voltage is applied to SL terminal 72a, and a positive voltage is applied to WL terminal 70b, no-voltage is applied to substrate terminal 78.Unselected BL terminal (BL terminal 74b in such as Figure 161, 74c ... 74p) maintain no-voltage, the SL terminal of not selection (SL terminal 72b in such as Figure 161,72c, ... 74p) maintain no-voltage, the WL terminal (WL terminal 70a in such as Figure 161,70m, 70n) of selection will not maintain In no-voltage, unselected substrate terminal 78 will be maintained at no-voltage.Or, voltage can be acted on be connected to buried layer district it In unselected BL terminal, maintain the state of unselected internal storage location.

In a specific unrestricted embodiment, following bias condition can be applicable to the internal storage location 1150b selected Upper: the voltage of about+0.4 volt acts in BL terminal 74a, and the voltage of about 0.0 volt acts on SL terminal 72a, about+1.2 volts The voltage of spy acts in WL terminal 70b, and the voltage of about 0.0 volt acts in substrate terminal 78, and following bias condition can Apply in unselected terminal: the voltage of about 0.0 volt acts in unselected BL terminal that (or the voltage of+1.2 volts can Act on and be connected to buried layer district, maintain in the SL terminal of unselected internal storage location state), the voltage effect of about 0.0 volt In unselected WL terminal, the voltage of about 0.0 volt acts in unselected substrate terminal.

As shown in Figure 162, the voltage of about+1.2 volts acts on a 60b, and the voltage of about 0.4 volt acts in district 16 (being connected to BL terminal 74a), the voltage of about 0.0 volt acts on and (is connected to SL terminal 72a) in buried layer district 22, about 0.0 volt The voltage of spy acts on buried layer 22, and the voltage of about 0.0 volt acts on the substrate 12 of selected memory unit 1150b.From BL terminal 74a flows to the size of current of SL terminal 72a and is then determined by the voltage of selected unit 1150b floater area 24.

When there being state " 1 " in hole during unit 1150b is in floater area 24, then internal storage location then have one relatively low Threshold voltage (gate voltage when transistor is opened), and in unit 1150b is in floater area 24 without state " 0 " in hole time, Conduct one and compare bigger electric current.Cell current can be by, and the sense amplifier circuit being such as connected to BL terminal 74a is felt Should.

Or, carry out read operation by reverse effect in the condition of BL terminal 74 and SL terminal 72.

Figure 163-～164 is relevant writes " 0 " operating instruction, wherein applies following bias condition: no-voltage acts on SL eventually End 72a, no-voltage acts on WL terminal 70, and negative voltage acts on BL terminal 74a, substrate terminal 78 then ground connection.At these Under part, any p-n junction between buoyancy aid 24 and the district 20b of internal storage location 1150 is positive bias, empties any hole from buoyancy aid 24. The all internal storage locations 1150 sharing same BL terminal 74a are written to state " 0 ".Unselected WL terminal, unselected BL is eventually End, unselected SL terminal and unselected substrate terminal then ground connection.

In a specific unrestricted embodiment, the voltage of about-1.2 volts acts in terminal 74a, about 0.0 volt The voltage of spy acts in SL terminal 72a, and the voltage of about 0.0 volt acts in terminal 70, and the voltage of about 0.0 volt acts on In terminal 78.Unselected BL terminal 74 (such as BL terminal 74b, 74c ... 72o and 74p) will be maintained at 0.0 volt of electricity Pressure, unselected SL terminal 74 (such as SL terminal 72b, 72c ... 72o and 74p) will be maintained at 0.0 volt of voltage, and not Selected substrate terminal 78 will be maintained at 0.0 volt of voltage.Despite this, these magnitudes of voltage can change with change, and Maintaining the relativeness between applied electric charge, see above description.

Or, the bias condition being applied in BL terminal 74 and SL terminal 72 by reverse achieves that writes " 0 " operation.

Another is available and that allow independent position to write write " 0 " operates, and sees that Figure 165～166 illustrates and passes through at BL eventually End 74a applies negative voltage, applies no-voltage in SL terminal 72a, apply no-voltage in substrate terminal 78, and applies in WL terminal 70 The mode of positive voltage realizes.Under these conditions, a positive voltage is acted on the door of selected memory unit (such as Figure 165- Internal storage location 1150b in 166), buoyancy aid 24 voltage will be increased by Capacitance Coupled from acting on the positive voltage of WL terminal 70 subsequently Long.Increasing due to buoyancy aid 24 voltage and apply negative voltage in BL terminal 74a, any p-n junction between 24 and district 16 is positive bias, Any hole is emptied from buoyancy aid 24.Write by reducing in memory array 1180 other internal storage locations 1150 are brought unnecessary " 0 " bothers, and the voltage acted on can optimize as follows: when state " 1 " buoyancy aid 24 voltmeter is shown as V_FB1, then act on selected WL The voltage of terminal 70, the voltage being configurable to increase buoyancy aid 24 is V_FB1/ 2, and-V_FB1/ 2 act in BL terminal 74a.

In a specific unrestricted embodiment, below bias condition be applied on internal storage location 1150: about 0.0 The voltage of volt acts in SL terminal 72a, and the voltage of about-0.2 volt acts in BL terminal 74a, the electricity of about+0.5 volt Pressure acts in selected WL terminal 70b, and the voltage of about 0.0 volt acts in substrate terminal 78, and the voltage of about 0.0 volt Acting in unselected BL terminal 74, the voltage of about 0.0 volt acts on unselected SL terminal, the voltage of about 0.0 volt Acting in unselected WL terminal 70, the voltage of about 0.0 volt acts in unselected terminal 78.Or, a positive electricity Pressure, such as+1.2 volts, may act in unselected SL terminal, is connected in buried layer district 22, maintains unselected internal memory The state of unit.Figure 165-166 gives, the selected and bias condition of unselected internal storage location in memory array 1180, wherein Internal storage location 1150b is selected unit.While it is true, these magnitudes of voltage can change with change.

Or, write " 0 " operation and also can pass through, reverse the bias condition being applied in BL terminal 74 and SL terminal 72 and realize.

Carrying out band-to-band tunnelling one writing and operate it, a bias condition example, is shown in one of on selected memory unit 1150b The explanation of Figure 167 and 168.Back bias voltage acts in selected WL terminal 70b, and no-voltage acts in SL terminal 72a, positive bias Act in BL terminal 74a, substrate terminal 78 then ground connection.This condition is ordered about electronics and is flowed to BL terminal 74a, and generation is subsequently injected into Hole in floater area 24.

In a specific unrestricted embodiment, below bias condition be applied on internal storage location 1150b: about The voltage of 0.0 volt acts in SL terminal 72a, and the voltage of about+1.2 volts acts in BL terminal 74a, about-1.2 volts it Voltage acts in selected WL terminal 70b, and the voltage of about 0.0 volt acts in substrate terminal 78；And bias strip below Part is applied in unselected terminal: the voltage of about 0.0 volt acts on unselected BL terminal, and (BL in such as Figure 167 is eventually End 74b, 74c ... 74o and 74p), the voltage of about 0.0 volt acts on the unselected SL terminal (SL in such as Figure 167 Terminal 70b, 70c ... ..72o and 70p), the voltage of about 0.0 volt acts on unselected WL terminal 70 (in such as Figure 167 SL terminal 70b, 70c ... 72o and 70p), the voltage of about 0.0 volt acts in substrate terminal 78.Or one+ The positive voltage of 1.2 volts may act on (with seriality or intermittently with above-mentioned pulse mode, lower power consumption) unselected it In SL terminal, it is connected in buried layer district 22, maintains the state of unselected internal storage location.Figure 167-168 gives interior poke Selected and the bias condition of unselected internal storage location in group 1180, wherein internal storage location 1150b is selected unit.While it is true, These magnitudes of voltage can change with change.

One of carry out on the selected memory unit 1150b of ionization by collision one writing operation a bias condition example see Figure 169 and 170 explanations.One positive bias acts in selected WL terminal 70b, and no-voltage acts in SL terminal 72a, and positive bias acts on BL terminal 74a, substrate terminal 78 then ground connection.These conditions produce a transverse electric field, it is sufficient to generate high energy electron, thus raw Become electron-hole pair, be followed by injected into the buoyancy aid of selected memory unit (the unit 1150b in such as Figure 169～170) for hole On 24.

In a specific unrestricted embodiment, below bias condition be applied on internal storage location 1150b: about The voltage of 0.0 volt acts in SL terminal 72a, and the voltage of about+1.2 volts acts in BL terminal 74a, about+1.2 volts it Voltage acts in selected WL terminal 70b, and the voltage of about 0.0 volt acts in substrate terminal 78；And bias strip below Part is applied in unselected terminal: the voltage of about 0.0 volt acts on the unselected BL terminal 74 (BL in such as Figure 169 Terminal 74b, 74c ... ..74o and 74p), the voltage of about 0.0 volt acts on unselected SL terminal 72 (in such as Figure 169 SL terminal 70b, 70c ... 72o and 70p), the voltage of about 0.0 volt acts on unselected WL terminal 70 (such as schemes SL terminal 70a in 169,70m and 70n), the voltage of about 0.0 volt acts in substrate terminal 78.Or one+1.2 volts Positive voltage may act on the SL terminal 72 that (with seriality or intermittently with above-mentioned pulse mode, lower power consumption) is unselected On, it is connected in buried layer district 22, maintains the state of unselected internal storage location.Figure 169-170 gives memory array 1180 In the selected and bias condition of unselected internal storage location, wherein internal storage location 1150b is selected unit.While it is true, these are electric Pressure value can change with change.

Or, achieved that by reverse effect bias condition in BL terminal 74 and SL terminal 72, above-mentioned interband tunnel Channel effect and the operation of ionization by collision mechanism purgation one writing.

Array 1180 is made up of multiple flat units according to the embodiment of introduction in Figure 158 C and 158D, or, by fin Three-dimensional element is constituted.Other change, amendment and replacement unit, can without departing substantially from the scope of the invention and its functional in the case of enter Row is open.

Hold and sayed, it can be seen that the invention discloses, a kind of semiconductor memory with electronic buoyancy aid.The present invention also carries Supply, the method keeping a kind of possibility of storing state or parallel non-algorithm regular update operation.Therefore, storing operation can not The mode of interruption is carried out.Above-mentioned in view of the present invention is introduced in written text so that a certain those of ordinary skill determines and use to recognize at present For optimal mode, those those of ordinary skill will understand that and notify the change of specific embodiment in the present invention, method and example, Combination and the existence of equivalent.Therefore, the present invention by the restriction of above-described embodiment, method and example, but should not want according to right Ask in the scope and spirit of the present invention disclosed in book it, except all embodiments and methods.In view of the present invention is according to its specific reality Execute example and be described explanation, then those skilled in the art it will be appreciated that different change can be made and replaces equivalent, In the case of the connotation of the present invention and scope.Additionally, can carry out many places amendment make a certain special circumstances, material, Material composition, technique, processing step adapt to the objective of the present invention, spirit and scope.These type of amendments all should be wanted in appended right Ask book disclosure in the range of.

The present invention discloses one and has the semiconductor memory of volatile and the most volatile function simultaneously, has merged flash memory The characteristic of EPROM and DROM.During energising, the most volatile DRAM runs as a canonical unit.Therefore, its performance (speed, merit Rate and reliability) suitable with a canonical DRAM cell.During power-off (or the backup operation periodically carried out), within volatile memory Hold and be stored in nonvolatile memory (referred to as " covering " process).During Power resumption, the content of nonvolatile memory returns to volatile (referred to here as " recovering " process) is thought highly of in storage.

Figure 171 is according to a certain embodiment of the present invention, carries out flow process Figure 100 of memory subassembly illustrative operation.In event In 102, when memory subassembly is energized first, memory subassembly is in the original state of volatile operational mode, and Nonvolatile memory sets Being set to a predetermined state, typical set-up has a positive charge.In event 104, in the case of energising all the time, within the present invention DRAM (DRAM (Dynamic Random Access Memory)) operator scheme depositing assembly and a tradition is the same, i.e. transports as volatile ram Make.But, power-off or have a power failure suddenly, or other event terminations any or when disturbing the power supply of memory subassembly of the present invention, volatile deposit The content of reservoir is deposited in the not volatile ram in event 106, and this process is referred to as " covering " (event 106) process, And the loss of data in volatile ram.Also can carry out covering (in this case, volatibility during performing backup operation Data in internal memory will not be lost), can be when DRAM operate for 104 stage, and/or user manually indicates any time of backup fixed Phase is carried out.When backup operation, the content of volatile ram copies in Nonvolatile memory, and volatile ram leads to all the time Electricity, makes the content of volatile ram the most also be saved in volatile ram.Or, owing to volatile ram operation ratio is in non-volatile Deposit content, consume more electricity, then this device was configurable in any period of its at least predefined phase on the shelf Perform masking process, thus transfer to, in Nonvolatile memory, save electricity by the content in volatile ram.Lift an example Son, this predefined phase can be about 30 minutes, but, the present invention is not limited only to this stage, owing to this device can almost appointed One predefined phase internal program design.

When covering operation, after the content in volatile ram being moved on to not in volatile ram, memory subassembly i.e. shuts down (when not being backup operation, power supply will not re-supply volatile ram).At this moment, memory subassembly is as a flash eprom device Equally run (erasable programming read only memory), because it can retain the data of storage in not volatile ram.In event Power resumption when 108, the content in nonvolatile memory, volatile ram is carried out by nonvolatile memory is transferred to Recovering, this process is referred to as " recovery " process, and after recovery, the replacement memory subassembly when event 110, memory subassembly sets again It is set to original state 102 and again with volatile mode operation, such as same DRAM memory subassembly, event 104.

In another embodiment/use, one of present invention memory subassembly, can be by not volatile ram when Power resumption The content of weight returns in volatile ram, and with volatile mode operation, and memory subassembly need not be reset first.Substitute at this In embodiment, volatile operation operates independent of nonvolatile memory data.Figure 172 is that another is according to a certain reality of the present invention Execute example and carry out flow process Figure 200 of memory subassembly illustrative operation.In event 202, during energising, memory subassembly of the present invention with easily The mode losing memory cell the same operates.Power-off or have a power failure suddenly, or other event terminations any or the interference present invention During the power supply of memory subassembly, nonvolatile memory resets to the default conditions in event 204, followed by for covering operation 206, wherein Content in volatile ram is deposited into not in volatile ram.

When covering operation, after the content in volatile ram being moved on to not in volatile ram, memory subassembly i.e. shuts down (unless the masking process carried out is backup operation, power supply will not re-supply volatile ram).At this moment, memory subassembly is as a sudden strain of a muscle Deposit EPROM device and equally run (erasable programming read only memory), because it can retain does not stores it in volatile ram Data.

The Power resumption when event 208, the content in nonvolatile memory is by transferring to nonvolatile memory content Being recovered in volatile ram, this process is referred to as " recovery " process, and after recovery, memory subassembly is again with volatile mould Formula is run, such as same DRAM memory subassembly, event 202.

In another embodiment/use, do not carry out not volatile ram reset operation.Such as, this is at not volatile ram Be used for store " permanent data " (data of change in value i.e. will not occur in routine use) in the case of be useful it.Such as, Volatibility bit of storage not can be used to store application software, program etc. and/or the data that will not frequently change, as operating system is reflected Picture, multimedia shelves etc..

Figure 173 A icon method describes, according to one of internal storage location 1250 of the present invention embodiment.Unit 1250 wraps Include such as the substrate 12 of the first conductivity type such as p-type conductivity type.Substrate 12 is generally to be made up of silicon, but also can be by such as The semi-conducting material composition that germanium, germanium silicon, GaAs etc. are known in the art.Substrate 12 has a surface 14.Have such as N-shaped etc. second The first district 16 planting conductivity type is present in substrate 12, and is exposed to surface 14.Have the of the second conductivity type Two districts 18 exist in substrate 12, and are exposed to surface 14, spaced apart with the first district 16.According to any known and affiliated skill The injection technology of art field Special use, the first and second districts 16 and 18 are formed at the material constituting substrate 12 by injection technology Above.

The buried layer 22 of the second conductivity type exists in substrate 12, and is embedded in substrate 12, as shown.District 22 also can be formed at above substrate 12 material by ion implantation technology.The floater area 24 of substrate 12 is by surface 14, the first and the Two districts 16,18, and insulating barrier 26 surrounds (such as shallow trench isolation (STI)), its material is the material of silicon dioxide etc.When many When the set of individual unit 1250 forms a memory subassembly, unit 1250 is kept apart by insulating barrier 26 with adjacent unit 1250.Resistance Barrier 60 is between district 16 and 18, above surface 14.Barrier layer 60 material can be silicon nitride, nanocrystal silicon or high k dielectric material Material or other dielectric material.Barrier layer 60 is run and is stored not volatibility internal storage data.It is many that barrier layer 60 allows each unit to have Storage location 62a, 62b of individual physical isolation, thus create the most volatile functional of multidigit.And this process can be via district 16 Apply electric charge for the first time and store not volatile data at storage location 62a, and apply second time electric charge in bit of storage via district 18 Putting 62b to store not volatile data and realize, details see below description.

Control gate 64 is positioned at above barrier layer 60, words so, and barrier layer 60 is located between control gate 64 and surface 14, As shown.Control gate 64 is by the polycrystalline silicon material of typical case or metal gate electrode, as tungsten, tantalum, titanium and its nitride are made.

Unit 1250 includes five terminals: wordline (WL) terminal 70, source electrode line (SL) terminal 72, bit line (BL) terminal 74, Bury well (BW) terminal 76 and substrate terminal 78.Terminal 70 connects control gate 64.Terminal 72 connects the first district 16, and terminal 74 connects Second district 18.Or, terminal 72 connects the second district 18, and terminal 74 connects the first district 16.Terminal 76 connects buried layer 22.Terminal 78 connect substrate 12.

Figure 173 B for the internal storage location 1250 that is arranged in ranks it, an exemplary array 1280.Or, according to this The internal storage location assembly of invention, can occur in multiple unit 1250 mode of single file or single-row arrangement, but it is often the case that multirow All occur with multiple row.Figure 173 B discloses wordline 70A to 70n, source electrode line 72a to 72n, bit line 74a to 74p and substrate terminal 78.Arbitrary wordline in 70a to 70n is associated with single internal storage location 1250, and is coupled to be expert at each internal storage location On the door 64 of 1250.Similarly, the arbitrary source electrode line in 72a to 72n is associated with single internal storage location 1250, and is coupled to institute It is expert in the district 16 of each internal storage location 1250.Either bit line in 74a to 74p is associated with single-row internal storage location 1250, and It is coupled in the district 18 of each internal storage location of column 1250.Array 1280 times, well terminal 76 and lining are buried in all positions End terminal 78.Those of ordinary skill in the art should notify, and in terms of design alternative angle, one or more positions have one or more Substrate terminal 78.These those of ordinary skill in the art also should notify: when exemplary array 1280 is single company in Figure 173 B During continuous array, then a lot of other structures and layout can alternately be set up.Such as, wordline divisible or buffering, bit line divisible or Buffering, source electrode line is divisible or buffers, and array 1280 is divided into subnumber group and/or the control circuit, such as transliteration of two or more Code device, column decoder, segmentation device, sense amplifier and/or write amplifier, can be arranged in around exemplary array 1280 or Insert array 1280 subnumber group middle.Therefore, the one exemplary embodiment in the present invention, feature, design option etc. are in any feelings It is not construed as limiting under condition.

Figure 173 C is another example of the structure of arrays 1280b of the internal storage location assembly according to the present invention, wherein interior deposit receipt Unit 1250 arranges with multirow and multi-column version.Internal storage location 1250 connection makes in each row, and all control gates 64 are connected to Shared word line terminal 70 (such as 70,70b ... 70n).In each column, all the first and of column unit 1250 Two districts 16,18 be connected respectively to share source electrode and bitline terminal 72 (such as 72a, 72b ... 72h) and 74 (such as 74a, 74b、......74h)。

Figure 174 describes another write state " 1 " operation, is injected by interband tunnel hot hole, or ionization by collision hot hole Injection mode is carried out on unit 1250.By interband tunnel mechanism write state " 1 ", following voltage is applied in terminal: just Voltage acts in BL terminal 74, and neutral voltage acts in SL terminal 72, and negative voltage acts in WL terminal 70, and one is less than Being applied to BL terminal 74 positive voltage, act on BW terminal 76, neutral voltage acts in substrate terminal 78.Under these conditions, Hole is injected in floater area 24 from BL terminal 74, makes floater area 24 positively charged.Act on the positive voltage of BL terminal 74, produce Give birth to and can stop the depletion region being stored in any charge effect of storage location 62b.Therefore, no matter write state " 1 " operation can deposit Enter in storage location 62b and carry out in the case of electric charge.

In a specific unrestricted embodiment, the voltage of about+2.0 volts acts on terminal 74, about 0.0 volt it Voltage acts on terminal 72, and the voltage of about-1.2 volts acts on terminal 70, and the voltage of about+0.6 volt acts on terminal 76, about The voltage of 0.0 volt acts on 78.While it is true, these magnitudes of voltage also can change, and keep between applied electric charge Relativeness, see above-mentioned.Additionally, the voltage being applied in terminal 72 and 74 is interchangeable, but obtain same result all the time.Although So, depletion region can be formed near storage location 62a rather than 62b in turn.

Or, by ionization by collision mechanism write state " 1 ", it is applied with voltage as follows: positive voltage acts on BL terminal 74 On, neutral voltage acts in SL terminal 72, and positive voltage acts in WL terminal 70, and positive voltage acts in BW terminal 76, and Neutral voltage acts in substrate terminal 78.Under these conditions, hole is injected in floater area 24 from BL terminal 74, makes to float Body district 24 is positively charged.Act on the positive voltage of BL terminal 74 to create and can stop and be stored in any charge effect of storage location 62b Depletion region.

In a specific unrestricted embodiment, the voltage of about+2.0 volts acts on terminal 74, about 0.0 volt it Voltage acts on terminal 72, and the voltage of about+1.2 volts acts on terminal 70, and the voltage of about+0.6 volt acts on terminal 76, about The voltage of 0.0 volt acts on 78.While it is true, these magnitudes of voltage also can change, and keep between applied electric charge Relativeness, see above-mentioned.Additionally, the voltage being applied in terminal 72 and 74 is interchangeable, but obtain same result all the time.Although So, depletion region can be formed near storage location 62a rather than 62b in turn.

Or, silicon controlled rectifier (SCR) assembly of unit 1250 can enter state " 1 " by applying following bias (i.e. carrying out writing " 1 " operation): neutral voltage acts in BL terminal 74, and positive voltage acts in WL terminal 70, and one is more than The positive voltage being applied to terminal 70 positive voltage acts in substrate terminal 78, and SL terminal 72 and BW terminal 76 is then floated.Effect Positive voltage in WL terminal 70 can increase the voltage of buoyancy aid 24 by Capacitance Coupled and produce a feedback opening SCR assembly Journey.Once unit 1250 SCR assembly enter conduction mode (the most " opening "), SCR " locking " and be applied to WL terminal 70 it Voltage can be removed, and it " opens " state not to affect SCR assembly.In a specific unrestricted embodiment, about 0.0 volt Voltage act in terminal 74, the voltage of about 0.5 volt acts in terminal 70, and the voltage of about 0.8 volt acts on terminal On 78.While it is true, these magnitudes of voltage can change, and keep the relativeness between applied electric charge, see above-mentioned, such as It is applied to the voltage that the voltage in terminal 78 is consistently greater than applied in terminal 74.This write state " 1 " operates, and can no matter deposit Enter in storage location 62a or 62b and carry out in the case of electric charge.

Figure 175 describes, write state " 0 " operation that can carry out on unit 1250.In order to state " 0 " is write buoyancy aid District 24, is applied with negative voltage in SL terminal 72, and terminal 72 negative voltage is to be born less than being applied to be applied with one in WL terminal 70 Voltage, is applied with the voltage of 0.0 volt in BL terminal 74 and is applied with positive voltage in BW terminal 76, and in substrate terminal 78 It is applied with neutral voltage.Under these conditions, any p-n junction (nodes between 24 and 16) is positive bias, and emptying is from buoyancy aid 24 Any hole.In a specific unrestricted embodiment, the voltage of about-2.0 volts acts on terminal 72, about-1.2 volts The voltage of spy acts on terminal 70, and the voltage of about+0.6 volt acts on terminal 76, and the voltage of about 0.0 volt acts on terminal 72 With 78.While it is true, these magnitudes of voltage can change, and keep the relativeness between applied electric charge, see above-mentioned.This Outward, the voltage being applied in terminal 72 and 74 is interchangeable, but obtains same result all the time.It can be seen that write state " 0 " behaviour Make, can carry out in the case of electric charge no matter being stored in storage location 62a or 62b.

Or, it is set to non-blocking mode and just can carry out writing " 0 " by arranging silicon controlled rectifier assembly and operate.Can be by answering It is biased into row: positive voltage acts in BL terminal 74, and positive voltage acts in WL terminal 70, and a positive voltage, it is big with following In being applied to terminal 74 positive voltage, act on substrate terminal 78, and make SL terminal 72 and BW terminal 76 float.In these conditions Under, the voltage difference between anode and negative electrode, depend on the voltage of substrate terminal 78 and BL terminal 74, can become is the least, and can not SCR assembly is kept to be in conduction mode.Therefore, the SCR assembly of unit 1250 is closed.A specific unrestricted embodiment In, the voltage of about+0.8 volt acts in terminal 74, and the voltage of about+0.5 volt acts in terminal 70, about+0.8 volt it Voltage acts in terminal 78.While it is true, these magnitudes of voltage can change, and keep the relative pass between applied electric charge System, sees above-mentioned.It can be seen that write state " 0 " operation, can be no matter being stored in storage location 62a or 62b in the case of electric charge Carry out.

The read operation of unit 1250, is shown in the explanation of Figure 176.For sensing element 1250, apply positive electricity in BL terminal 74 Pressure, applies neutral voltage in SL terminal 72, applies a ratio in WL terminal 70 and be applied to the positive voltage that terminal 74 positive voltage is bigger, Positive voltage, substrate terminal 78 then ground connection is applied in BW terminal 76.The state in hole is had in unit 1250 is in floater area 24 Time " 1 ", then the threshold voltage (gate voltage when transistor is opened) recorded can be in floater area 24 without empty than unit 1250 The threshold voltage recorded under the state " 0 " in cave is low.Cell current can be by, such as, be connected to the sense amplifier of BL terminal 74b Circuit is sensed.The positive voltage acting on BL terminal 74 constitutes a depletion region around node 18, stops and is stored in bit of storage Put any charge effect of 62b.Therefore, volatile state read operation (in this instance, can be deposited no matter being stored in nonvolatile memory Enter the electric charge of storage location 62b) carry out in the case of electric charge.In a specific unrestricted embodiment, about+0.4 volt Voltage act in terminal 74, the voltage of about 0.0 volt acts on terminal 72, and the voltage of about+1.2 volts acts on terminal 70 On, the voltage of about+0.6 volt acts in terminal 76, and the voltage of about 0.0 volt acts in terminal 78.While it is true, these Magnitude of voltage can change, and keeps the relativeness between applied electric charge, sees foregoing.

Read operation also can be carried out in a case where: positive voltage acts in BL terminal 74, and neutral voltage acts on SL In terminal 72, a ratio is applied to the positive voltage that in terminal 74, positive voltage is less, acts on WL terminal 70, and positive voltage acts on BW In terminal 76, substrate terminal 78 then ground connection.When there being state " 1 " in hole during unit 1250 is in floater area 24, one by SL terminal 72, the parasitic bipolar transistor of buoyancy aid 24 and BL terminal 74 composition are opened, and contrast unit 1250 is in floater area 24 During without state " 0 " in hole, record a higher cell current.Act on positive voltage in BL terminal 74 node 18 weeks Enclose and define a depletion region, stop any charge effect being stored in storage location 62b.Therefore, volatile state read operation, can In the case of being stored in nonvolatile memory (in this instance, being stored in the electric charge of storage location 62b) electric charge regardless of (the most independently) Carry out.In a specific unrestricted embodiment, the voltage of about+3.0 volts acts in terminal 74, about 0.0 volt it Voltage acts on terminal 72, and the voltage of about+0.5 volt acts in terminal 70, and the voltage of about+0.6 volt acts on terminal 76 On, the voltage of about 0.0 volt acts in terminal 78.While it is true, these magnitudes of voltage can change, and keep being applied electricity Relativeness between pressure, is shown in foregoing.

Or, substrate terminal 78 applies a positive voltage, the electricity of applying one generally neutrality in BL terminal 74 Pressure, applies a positive voltage in WL terminal 70.Terminal 72 and 76 floatings.Unit 1250 discloses a P1-N2-P3-N4 silicon Controlled rectifier assembly, wherein substrate 78 runs as P1 district, and buried layer 22 runs as N2 district, and floater area 24 is transported as P3 district OK, district 18 or 18 then runs as N4 district.The operation of silicon controlled rectifier assembly, is shown in 12/ put on record on July 31st, 1998 More details described in 533, No. 661 applications, entitled " the floating body transistor semiconductor memory group of utilization controlled rectifier principle The operational approach of part ".12/533, No. 661 application full content is incorporated herein, as reference.In this instance, substrate is eventually End 78 runs as anode, and terminal 72 or terminal 74 are then run as negative electrode, and floater area 24 runs as p-base stage and opens SCR assembly.When there being state " 1 " in hole during unit 1250 is in floater area 24, one by substrate, bury well, buoyancy aid and BL knot Silicon controlled rectifier (SCR) assembly of some composition is opened, and contrast unit 1250 is in floater area 24 state " 0 " without hole Time, record a higher cell current.One positive voltage acts in WL terminal 70, thus selects in memory cell array Select a line, and for unselected trip, then in WL terminal 70, apply negative voltage.The negative voltage applied, decreases unselected Determine the voltage by the buoyancy aid 24 of Capacitance Coupled in row, and in each unselected row, close the SCR group of each unit 1250 Part.Therefore, read operation can be carried out in the case of deposited electric charge not taking into account in nonvolatile memory.Specific unlimited at one In the embodiment of system, the voltage of about+0.8 volt acts in terminal 78, and the voltage of about+0.5 volt acts on terminal 70 and (is used for Select row), the voltage of about 0.0 volt acts in terminal 72, and terminal 74 and 76 is then floated.While it is true, these magnitudes of voltage Can change.

Figure 177 describes preservation or standby operation.Perform this preservation or standby operation, strengthen the number of internal storage location 1250 According to keeping feature.Can perform to preserve operation by the following bias of application: apply the voltage of a generally neutrality in BL terminal 74, Apply a neutrality or negative voltage in WL terminal 70, substrate terminal 78 applies a positive voltage, and allows SL terminal 72 and BW Terminal 76 is floated.Under these conditions, just have if internal storage location 1250 is in storage/data mode " 1 " and floater area 24 Voltage, then the SCR assembly of internal storage location 1250 is then opened, thus the data of hold mode " 1 ".Deposit receipt in state " 0 " purgation Unit can keep non-blocking mode, because the voltage in buoyancy aid 24 is not the most positive voltage, therefore buoyancy aid 24 does not opens SCR assembly. Correspondingly, electric current does not flows through SCR assembly, and these unit hold mode " 0 " data.Visible, row's internal storage location 1250 can It is updated by periodically applying positive voltage in substrate terminal 78.It is commonly connected to substrate terminal 78 and carries in floater area 24 Those internal storage locations 1250 having positive voltage can carry out " 1 " data mode and update, and are commonly connected to substrate terminal 78, and floating There is no those internal storage locations 1250 of positive voltage in body district 24, non-blocking mode can be kept, because their SCR assembly will not be opened Opening, therefore those unit can keep internal storage state " 0 ".Words so, are commonly connected to all internal storage locations of substrate terminal 1250 can keep/update, accurately to preserve their data mode.As long as in parallel non-algorithm effective procedure, apply voltage In substrate terminal 78, this process will occur automatically.Further, it can be seen that preserve operation, can not take into account be stored in the most volatile Memorizer is carried out in the case of electric charge.In a specific unrestricted embodiment, the voltage of about 0.0 volt acts on end On end 74, the voltage of about-1.0 volts acts in terminal 70, and the voltage of about+0.8 volt acts in terminal 78.Although such as This, these magnitudes of voltage, it also occur that change, but maintain the relativeness between them.Or, the above-mentioned electricity being applied to terminal 74 Pressure may act in terminal 72, and terminal 74 is then floated.

Or, can perform to preserve operation by the following bias of application: the generally voltage of neutrality acts in BL terminal 74, Positive voltage acts in SL terminal 72, and positive voltage acts in BW terminal 76, and zero or negative voltage act in WL terminal 70.Lining End terminal 78 can be floated or ground connection.Under these conditions, the parasitic bipolar assembly being made up of district 16, floater area 24 and district 18 is beaten Open.If buoyancy aid 24 is in the interior state " 1 " with positive charge of floater area 24, then the positive voltage meeting being applied in SL terminal 72 Produce ionization by collision, thus generate electron-hole pair.And hole can be diffused in buoyancy aid 24, thus in supplementing floater area 24 it Positive charge is also maintained at " 1 " data mode.If buoyancy aid 24 is in state " 0 ", it is made up of double district 16, floater area 24 and district 18 Pole assembly will not be opened, and therefore those unit can hold mode " 0 ".Words so, are commonly connected to substrate terminal all Internal storage location 1250 can keep/update, accurately to preserve their data mode.This mechanism is by the voltage of storage in floater area 24 Or Charge controlled, and independent of the voltage acted in WL terminal 70.As long as in parallel non-algorithm effective procedure, apply voltage In SL terminal 72, this process will occur automatically.Can be seen that preservation operation, can be stored in nonvolatile memory not taking into account Carry out in the case of electric charge.In a specific unrestricted embodiment, the voltage of about 0.0 volt acts in terminal 74, The voltage of about-1.0 volts acts in terminal 70, and the voltage of about+0.8 volt acts in terminal 72, the electricity of about+0.6 volt Pressure acts in terminal 76.While it is true, these magnitudes of voltage are it also occur that change, but maintain the relativeness between them.Or Person, the above-mentioned voltage being applied to terminal 72 may act in terminal 74, terminal 72 then ground connection.

Or, can be by the preservation operation of bias execution below application: applying zero or negative voltage in WL terminal 70, at BL eventually Apply the voltage of generally neutrality in end 74 and SL terminals 72, and in BW terminal 76, apply positive voltage.Substrate terminal 78 can be floated Move or ground connection.Under these conditions, the parasitic bipolar assembly being made up of district 16 or 18, floater area 24 and buried layer 22 is opened. If buoyancy aid 24 is in the interior state " 1 " with positive charge of floater area 24, then being applied to the positive voltage in BW terminal 76 can produce Raw ionization by collision, thus generate electron-hole pair.And hole can be diffused in buoyancy aid 24, thus supplement in floater area 24 just Electric charge is also maintained at " 1 " data mode.If buoyancy aid 24 is in state " 0 ", by district 16 or 18, floater area 24 and buried layer 22 structure The dipole elements of one-tenth will not be opened, and therefore those unit can hold mode " 0 ".Words so, are commonly connected to substrate terminal All internal storage locations 1250 can keep/update, accurately to preserve their data mode.This mechanism is stored by floater area 24 Voltage or Charge controlled, and independent of the voltage acted in WL terminal 70.As long as executing in parallel non-algorithm effective procedure Powering up and be pressed onto in BW terminal 76, this process will occur automatically.Can be seen that preservation operation, the most volatile depositing can be stored in not taking into account Reservoir is carried out in the case of electric charge.In a specific unrestricted embodiment, the voltage of about 0.0 volt acts on terminal On 72 and 74, the voltage of about-1.0 volts acts in terminal 70, and the voltage of about+1.2 volts acts in terminal 76, and about 0.0 The voltage of volt acts in terminal 78.While it is true, these magnitudes of voltage are it also occur that change, the phase between them but can be maintained To relation.

When power-off being detected, such as, when the power supply of user's switching units 1250, or power supply interrupts suddenly or because any Other reason, unit 1250 power supply the most temporarily interrupts, or due to the user's any particular command during backup operation, exists Data in floater area 24 are injected by thermoelectron and are transferred in barrier layer 60.This operation is referred to as " covering ", Figure 178 A- 178B is described.Perform masking process and the evidence in floater area 24 can be stored in storage location 62a or 62b.To storage location 62a When execution is covered, a positive high voltage acts in SL terminal 72, and ratio is applied to the neutrality in terminal 72 or positive voltage is less Neutrality or positive voltage act in BL terminal 74.Positive voltage acts in terminal 70, and positive voltage acts in terminal 76.This Situation purgation high pressure is then the voltage more than or equal to+3 volts.In one example, one+3 to+6 volts it are applied with In the range of voltage, although apply higher voltage be also possible.When buoyancy aid 24 has a positive charge/voltage, source electrode leaks Polar region 16 and 18 and the bipolar node of NPN of buoyancy aid 24 composition, is in opening, and electronics flows through internal memory transistor.At end Apply high pressure activation/promotion electronics on end 72 and flow through buoyancy aid 24, when reaching enough, jump into the stop being positioned near SL terminal 72 again In storage location in layer 62a, in Figure 178 A, arrow points to shown in storage location 62a.Correspondingly, volatile when unit 1250 When memorizer is in state " 1 " (buoyancy aid 24 is positively charged), the storage location 62a in barrier layer 60 is electronegative by the method for covering Lotus, as shown in Figure 178 A.

When the volatile memory of unit 1250 is in state " 0 ", i.e. buoyancy aid 24 band is born or neutral charge/voltage, and NPN ties Point is closed, and electronics may not flow into buoyancy aid 24, sees that Figure 178 B explains.Correspondingly, when according to above-mentioned applying voltage to When terminal is in order to perform mask program, it is applied to the positive high voltage in terminal 72 and will not produce the acceleration of electronics, so that thermoelectron It is injected in barrier layer 60, because electronics is not in flowing.Correspondingly, when the volatile ram of unit 1250 is in state " 0 " (i.e. buoyancy aid 24 band neutrality or negative charge), barrier layer 60 is injected without electric charge, and keeps its electric charge until covering end, such as Figure 178 B Shown in.Described in the operation that resets, the storage location 62 in barrier layer 60 initializes during the operation that resets or resets To with positive charge.Therefore, when the volatile ram of unit 1250 is in state " 0 ", storage location 62a can cover operation At the end of positively charged.

Note: covering after operation terminates, the state of charge of storage location 62a terminal is mutual with the state of charge of buoyancy aid 24 Mend.Therefore, if the buoyancy aid 24 of internal storage location 1250 is positively charged in volatile memory, barrier layer 60 is by covering operation After can be electronegative, and bear or during neutral charge when the buoyancy aid of internal storage location 1250 carry in volatile memory, storage location 62a Can be positively charged at the end of covering operation.It is positioned at the electric charge/state of the neighbouring storage location 62a of SL terminal 72 then with non-algorithm Relation depend on the state of buoyancy aid, and covering of multiple unit occurs with parallel way, therefore covers speed of operation and is exceedingly fast.

At a specific example covering operation according to the present embodiment unrestrictedly, the voltage of about+6.0 volts acts on end On end 72, the voltage of about 0.0 volt acts in terminal 74, and the voltage of about+1.2 volts acts in terminal 70, about+0.6 volt The voltage of spy acts in terminal 76.While it is true, these magnitudes of voltage are it also occur that change, and keep between applied voltage it Relativeness, is shown in above-mentioned.

Storage location 62b near BL terminal 74 covers operation, can pass through reverse effect electricity in terminal 72 and 74 Pressure performs in a similar fashion.

In covering another embodiment of operation, following bias condition is suitable for.In order to perform to cover behaviour at storage location 62a Making, a positive high voltage acts in SL terminal 72, and a positive voltage acts on WL terminal 70, and a ratio is applied in SL terminal 72 The less neutrality of positive voltage or positive voltage act in BL terminal 76, BL terminal 74 is then floated.Under this bias condition, When buoyancy aid 24 positively charged/voltage time, by district 16, buoyancy aid 24 with bury the bipolar node of NPN that wellblock 22 constitutes and be in opening, And electronics flows through internal memory transistor.Terminal 72 applies high pressure activation/promotion electronics and flows through buoyancy aid 24, jump again when reaching enough Enter to be positioned at the storage location of the neighbouring barrier layer 62a of SL terminal 72.Correspondingly, it is in when the volatile memory of unit 1250 During state " 1 " (buoyancy aid 24 is positively charged), the storage location 62a in barrier layer 60 is electronegative by the method for covering.

When the volatile ram of unit 1250 is in state " 0 ", i.e. buoyancy aid 24 band is born or neutral charge/voltage, NPN node It is closed, and electronics may not flow into buoyancy aid 24.Correspondingly, when voltage acts on above-mentioned terminal, electronics will not flow, And the thermoelectron in barrier layer 60 will not be occurred subsequently to inject.When the volatile ram of unit 1250 is in state " 0 ", stop Storage location 62a in layer 60 keeps its electric charge until covering end.Described in the operation that resets, in barrier layer 60 it Storage location 62 initializes or resets to positive charge during the operation that resets.Therefore, when the volatile ram of unit 1250 When being in state " 0 ", storage location 62a can be positively charged at the end of covering operation.

Storage location 62b near BL terminal 74 covers operation can pass through reverse effect voltage in terminal 72 and 74 Perform in a similar fashion.

When unit 1250 Power resumption, deposit unit 1250 state over barrier layer 60, can return in floater area 24. The introduction of Figure 179 A and 179B is shown in recovery operation (never volatile ram recovers to the data of volatile ram).Performing recovery Before operation, buoyancy aid 24 is set to neutrality or negative charge, i.e. " 0 " state and is written in buoyancy aid 24.

In Figure 179 A-179B embodiment, in order to perform to be stored in the recovery operation of not volatile data in storage location 62a, Terminal 72 is set to the voltage having generally neutrality, and positive voltage acts in terminal 74, and negative voltage acts in terminal 70, positive voltage Act in terminal 76, substrate terminal 78 then ground connection.The positive voltage acting on terminal 74 can produce a depletion region, and stop is deposited Enter the impact of electric charge in storage location 62b.When storage location 62a is electronegative, as shown in Figure 179 A, this negative charge strengthens The driving force of interband hot hole injection technology, hole is injected into buoyancy aid 24 from n-district 18 whereby, thus has recovered in volatibility Memory cell 1250 is the one state of preservation before performing to cover operation.When barrier layer 62a is the most electronegative, such as, work as barrier layer 62a is positively charged or neutral as shown in Figure 179 B, then between the torrid zone, hole is injected and will not be occurred, and as shown in Figure 179 B, creates One internal storage location 1250 with " 0 " state, being done before it performs to cover operation.Correspondingly, bit of storage is worked as Put 62a positively charged after performing to cover, then the volatile ram of buoyancy aid 24 can recover to negative charge (" 0 " state), But when barrier layer 62a is electronegative or during neutral charge, the volatile ram of buoyancy aid 24 can recover to positive charge (" 1 " shape State).

It is stored in the recovery operation of the not volatile data of storage location 62b, can be with the above-mentioned similar side of relevant storage location 62a Formula performs, and is applied to the voltage in terminal 72 and 74 by reverse and applies every other the same terms.

After completing recovery operation, the state on barrier layer 60 can reset to original state.The most volatile storage location 62a answers Bit manipulation, is shown in that Figure 180 describes.One negative high voltage acts in terminal 70, and a neutrality or positive voltage act in terminal 72, and one Individual positive voltage acts in terminal 76, and no-voltage acts in substrate terminal 78, and terminal 74 is then floated.Under these conditions, Electrons is tunnelled to n+ junction area 16 from storage location 62a.Therefore, storage location 62a is positively charged.

At the example of a specific operation that resets according to the present embodiment unrestrictedly, the voltage of about-18 volts acts on end On end 70, the voltage of about 0.0 volt acts in terminal 72, and the voltage of about+0.6 volt acts in terminal 76, about 0.0 volt Voltage act in terminal 78, terminal 74 is then floated.While it is true, these magnitudes of voltage also can change, and keep institute Apply the relativeness between electric charge, see above-mentioned.

The recovery operation of the most volatile storage location 62b can perform in above-mentioned relevant mode similar for storage location 62a, passes through Reverse is applied to the voltage in terminal 72 and 74 and applies every other the same terms.

By applying negative high voltage in terminal 70, terminal 72 and 74 applies neutrality, or positive voltage and in terminal 76 Applying positive voltage, storage location 62a and 62b can perform to reset simultaneously and operate, and terminal 78 ground connection.

At the example of a specific operation that resets according to the present embodiment unrestrictedly, the voltage of about-18 volts acts on end On end 70, the voltage of about 0.0 volt acts in terminal 72,74 and 78, and the voltage of about+0.6 volt acts in terminal 76.To the greatest extent So, these magnitudes of voltage also can change pipe, and keeps the relativeness between applied electric charge, sees above-mentioned.

In the embodiment of another internal storage location operation, block charge resets/reinitializes to a negative original state. For the storage location 62a that resets, apply following bias condition: apply positive high voltage in WL terminal 70, apply neutrality in terminal 72 Voltage, applies positive voltage in BW terminal 76, applies no-voltage in terminal 78, and terminal 74 is then floated.Under these conditions, electronics N+ junction area 16 can be tunnelled to from storage location 62a.Therefore, storage location 62a is electronegative.

At the example of a specific operation that resets according to the present embodiment unrestrictedly, the voltage of about+18 volts acts on end On end 70, the voltage of about 0.0 volt acts in terminal 72 and 78, and the voltage of about+0.6 volt acts in terminal 76, and eventually End 74 then floats.While it is true, these magnitudes of voltage also can change, and keep the relativeness between applied electric charge, see Above-mentioned.

The reset operation of the most volatile storage location 62b, can perform in above-mentioned relevant mode similar for storage location 62a, logical Cross reverse be applied to the voltage in terminal 72 and 74 and apply every other the same terms.

By applying negative high voltage in terminal 70, terminal 72 and 74 applies neutral or positive voltage and in BW terminal 76 Applying positive voltage, storage location 62a and 62b can perform the operation that resets simultaneously.

At the example of a specific operation that resets according to the present embodiment unrestrictedly, the voltage of about 18 volts acts on terminal On 70, the voltage of about 0.0 volt acts in terminal 72,74 and 78, and the voltage of about+0.6 volt acts in terminal 76.Although So, these magnitudes of voltage also can change, and keeps the relativeness between applied electric charge, sees above-mentioned.

In another carries out covering the embodiment of operation according to the present invention, apply following bias condition.In order in storage Deposit position 62a to perform to cover operation, be applied with a positive high voltage in SL terminal, be applied with a neutrality or positive electricity in BL terminal 74 Pressure, is applied with a negative voltage in WL terminal 70, is applied with a neutral voltage in BW terminal 76, applies one in substrate terminal 78 Individual neutral voltage.Under these bias conditions, when buoyancy aid 24 positively charged/voltage time, by district 16 and 18 and buoyancy aid 24 constitute The bipolar node of NPN be in opening, and electronics flows through internal memory transistor.Terminal 72 applies high pressure activation/promotion electricity Subflow, through buoyancy aid 24, produces electron-hole pair by ionization by collision.Act on the negative voltage of WL terminal 70 create one for The pulling force electric field of the hot hole injection of storage location 62a near SL terminal 72.Correspondingly, at the volatile memory of unit 1250 When state " 1 " (buoyancy aid 24 is positively charged), the storage location 62a in barrier layer 60 becomes positively charged lotus by covering operation.

When the volatile ram of unit 1250 is in state " 0 ", i.e. buoyancy aid 24 is with negative or neutral charge/voltage, NPN Node is closed, and electronics may not flow in buoyancy aid 24.Correspondingly, when applying voltage to above-mentioned terminal, electronics is not Can flow, and hot hole will not be occurred subsequently to be injected into the situation on barrier layer 60.When the volatile ram of unit 1250 is in shape During state " 0 ", the storage location 62a in barrier layer 60 can keep negative charge at the end of covering operation.

Correspondingly, when buoyancy aid 24 is positively charged, storage location 62a can cover after operation terminates positively charged in execution. On the contrary, when buoyancy aid 24 is electronegative, then storage location 62a can cover after operation terminates electronegative in execution.

Near BL terminal 74 storage location 62b cover operation, can hold in above-mentioned mode similar for relevant storage location 62a OK, it is applied to the voltage in terminal 72 and 74 by reverse and applies every other the same terms.

In another covers operation embodiment, apply following bias condition.In order to perform reset at storage location 62a Operation, is applied with a positive high voltage in SL terminal 72, is applied with a negative voltage in WL terminal 70, is applied with one in BW terminal 76 Individual no-voltage, BL terminal 74 then floats, substrate terminal 78 ground connection.Under these bias conditions, positively charged/electric when buoyancy aid 24 During pressure, by district 16, buoyancy aid 24 with bury the bipolar node of NPN that wellblock 22 constitutes and be in opening, and electronics flows through internal memory crystal Pipe.Terminal 72 applies high pressure activation/promotion electronics and flows through buoyancy aid 24, produce electron-hole pair by ionization by collision.Effect Negative voltage in WL terminal 70 creates a pulling force electricity for the hot hole injection of storage location 62a near SL terminal 72 ?.Correspondingly, when the volatile memory of unit 1250 is in state " 1 " (buoyancy aid 24 is positively charged), in barrier layer 60 it Storage location 62a becomes positively charged lotus by covering operation.

Correspondingly, when buoyancy aid 24 is positively charged, storage location 62a can perform to cover after operation terminates, positively charged. On the contrary, when buoyancy aid 24 is electronegative, then storage location 62a can cover after operation terminates electronegative in execution.

In another recovery operation embodiment, terminal 72 is set to the voltage having generally neutrality, a positive voltage effect In terminal 74, a ratio is applied to the positive voltage that terminal 74 positive voltage is less, acts in terminal 70, a positive voltage effect In terminal 76, no-voltage acts in terminal 78.It is applied to the positive voltage in terminal 74 and can produce a depletion region, stop to come Electric charge impact in being stored in storage location 62b.When storage location 62a is positively charged, this positive charge strengthens ionization by collision The driving force of technique, produces hot hole and is injected into buoyancy aid 24 from n-district 18, thus recovered volatile ram unit 1250 and existed The one state of the front preservation of operation is covered in execution.When barrier layer 62a is the most positively charged, then would not collide ionization, produce Give birth to an internal storage location 1250 with " 0 " state, being done before it performs to cover operation.Correspondingly, storage is worked as Deposit position 62a positively charged after performing to cover, then the volatile ram of buoyancy aid 24, can recover to positive charge (" 1 " shape State), but when barrier layer 62a is electronegative, the volatile ram of buoyancy aid 24, can recover to neutral charge (" 0 " state).

Figure 181 A icon method describes, according to another embodiment of the internal storage location 1250S of the present invention.Unit 1250S includes such as p-type conductivity type etc., the substrate 112 of the first conductivity type.Substrate 112 is usually to be made up of silicon, but Also can be made up of semi-conducting material known in the art, such as germanium, germanium silicon, GaAs etc..Substrate 112 has a surface 114.Tool It is present in substrate 112 just like the first district 116 of the second conductivity type such as N-shaped, and is exposed to surface 114.Have second The second district 118 planting conductivity type exists in substrate 112, and is exposed to surface 114, spaced apart with the first district 116. According to any known and injection technology of art Special use, the first and second districts 116 and 118 pass through injection technology It is formed at and constitutes above the material of substrate 112.

The buried insulator layer 122 such as buried oxide (BOX) exist in substrate 112, and are embedded in substrate 112, As shown.The floater area 124 of substrate 112 is surrounded by surface 114, the first and second districts 116,118, and buried insulator layer 122. One barrier layer 160 is between district 116 and 118, above surface 114.Barrier layer 160 material can be silicon nitride, nanocrystal silicon or High-k dielectric material or other dielectric material.Barrier layer 60 is run and is stored not volatibility internal storage data.Barrier layer 160 is used for storing Not volatile storage data.Barrier layer 160 allows each unit to have storage location 162a, 162b of two physical isolation, from And create the most volatile functional of multidigit.

One control gate 164 is positioned at above barrier layer 160, words so, and barrier layer 160 is located in control gate 164 and surface Between 114, as shown.Control gate 164 is generally by allusion quotation polycrystalline silicon material or metal gate electrode, such as tungsten, tantalum, titanium and its nitride system Become.

Unit 1250S includes four terminals: wordline (WL) terminal 170, bit line (BL) terminal 172 and 174 and substrate terminal 178.Terminal 170 connects control gate 164.Terminal 172 connects the first district 116, and terminal 174 connects the second district 118.Or, eventually End 172 connection the second district 118, and terminal 174 connects the first district 116.

Figure 181 B be according to a certain embodiment of the present invention it, the example of internal storage location assembly structure of arrays 1280S, wherein in Memory cell 1250S arranges with multirow and multi-columnar.Or, according to the internal storage location assembly of the present invention, can be with single file or single-row Multiple unit 1250S modes of arrangement occur, but it is often the case that multirow and multiple row all occur.Internal storage location 1250S connection side Formula is as follows: in each row, all control gates 164 be connected in a shared word line terminal 170 (such as 170a, Which row 170b ... 170n, depend on reference to).In each column, all first and second districts 116 of this column unit 1250S It is connected to a share bit lines terminal 172 (such as 172a, 172b ... ..172e) and 174 (such as 174a, 174b etc. with 118 Deng) in.

Owing to each unit 1250S has a buried insulator layer 122, based on this, together with district 116 and 118, bag Having enclosed bottom and the lateral boundaries of buoyancy aid 124, therefore insulating barrier 26 is not necessarily intended to surround each limit of buoyancy aid 24, and the enforcement of Figure 173 A Example is contrasted.Because unit 1250S need not insulating barrier 26, then then need less terminal, it is used for operating fitting into one Internal storage location 1250S in one of individual internal storage location assembly row unit 1250S.Owing to closing on unit 1250S not by insulating barrier 26 Isolation, proximity 116 and 118 is not isolated by insulating barrier 26.Correspondingly, single terminal 172 or 174, can be as terminal 174 For arbitrary adjacent unit 1250S to district 118 run, and, by reversing its polarity, it is possible to be another as terminal 172 One adjacent unit 1250S to district 116 run, wherein this contacts this to second unit to the district 118 of first module 1250S 1250S goes 116.Such as, in Figure 181 B, in the case of applying voltage according to the first polarity, terminal 174a can be as terminal The district 118 that 174 is unit 1250Sa runs.The polarity of voltage being applied in terminal 174a by reverse, terminal 174a can Run as the district 116 that terminal 172 is unit 1250Sb.By reducing the terminal quantity of regulation in internal storage location assembly, According to the permission of this description arrangement, may be produced that the most same capacity internal storage location according to the memory subassembly of the present embodiment of the present invention Volume less for assembly, it is desirable to a pair terminal 172,174 of each unit, be expert at adjacent unit terminal 172,174 Separate.

Figure 182-184 be the internal storage location 1250V according to the present invention it, another embodiment.In the present embodiment, unit 1250V has a fin structure 252, is assemblied on substrate 212, thus extends from substrate surface and form a three dimensional structure, Fin 252 extends generally upper surface perpendicular to and at substrate 212.Fin structure 252 can conduct electricity and be positioned at and bury well layer 222 On.District 222 is also formed on substrate 212 material by ion implantation technology.Bury well layer 222 will have the first conductivity type it Substrate floating region 224, isolates with bulk substrate 212.Fin structure 252 includes having the first and second of the second conductivity type District 216,218.Therefore, floater area 224 by fin 252 upper surface, the first and second districts 216 and 218, bury well floor 222 and insulation Layer 226 surrounds (insulating barrier 226 see in Figure 184).When the set of multiple unit 50 forms a memory subassembly, insulating barrier 226 Unit 1250V is kept apart with adjacent unit 1250V.Fin 252 is made up of silicon typical case, but also comprises germanium, germanium silicon, arsenic The semi-conducting material that gallium, CNT etc. are known in the art.

Assembly 1250V also includes, is positioned at substrate floating region 224 and opposes the door 264 on two sides, as shown in Figure 182.Or, door 264 Three limits of substrate floating region 224 can be impaled, as shown in Figure 183.Door 264 is kept apart with buoyancy aid 224 by barrier layer 260.Door 264 Between the first and second districts 16,18, neighbouring buoyancy aid 24.

Assembly 1250V includes multiple terminal: wordline (WL) terminal 70, source electrode line (SL) terminal 72, bit line (BL) terminal 74, Bury well (BW) terminal 76 and substrate terminal 78.Terminal 70 connects door 264.Terminal 72 connects the first district 216, and terminal 74 connects second District 218.Or, terminal 72 connects the second district 218, and terminal 74 connects the first district 216.Terminal 76 connects buried layer 222, and whole End 78 connection substrate 212.Figure 184 is the top view of internal storage location 1250V shown in Figure 182.

Until this point, unit 1250,1250S, 1250V describe and have been directed to binary cell, and wherein volatibility is (such as 24,124,224) and not volatibility (such as 62a, 62b, 162a, 162b, 262a and 262b) data do not store and are binary system, generation Table each memory storage position or storing state " 1 ", or storing state " 0 ".In another embodiment, either memory unit 1250,1250S, 1250V can carry out configuring using as multi-level unit, words so, and more than a data can be stored in one One of unit storage location.It is therefoie, for example, one or more volatile rams 24,124,224；Not volatile ram 62a, 162a, 262a and/or not volatile ram 62b, 162b, 262b can carry out configuration and carry out the storage work of long numeric data.

Figure 185 A describes the binary system internal storage state relative to threshold voltage, wherein internal storage location 1250,1250S, In 1250V less than or equal to default voltage it (in one example, default voltage is 0 volt, but default voltage can be higher Or low voltage) threshold voltage is read as state " 1 ", and internal storage location 1250,1250S or 1250V height overall are in default voltage Voltage be read as state " 0 ".

Figure 185 B describes the example of a multilevel memory voltage status, and wherein two bits can be stored in arbitrary bit of storage Put 24,124,224, in 62a, 62b, 162a, 162b, 262a, 262b.In this case, internal storage location 1250,12505, In 1250V, one is less than or equal to default voltage (such as 0 volt or some other default voltage) for the first time, and higher than ratio first Second time default voltage that secondary predicted voltage is low (e.g., from about-0.5 volt or some are less than other electricity of default voltage for the first time Pressure), it is read as state " 10 ", one is read as state " 11 " less than or equal to the voltage of second time default voltage；One More than default voltage for the first time, and less than or equal to the third time default voltage (e.g., from about 0.5 volt higher than first time default voltage Special or some higher than other voltages of default voltage for the first time), be read as state " 01 ", and more than third time default voltage it Voltage is read as state " 00 ".The more details of relevant multistage operations can be owned together by pending trial at the same time, and at 1996 11 No. 11/996,311 application put on record for 29th by the moon is found.11/996th, No. 311 application content is all included in herein, makees For reference.

In view of the present invention is described explanation according to its specific embodiment, then those skilled in the art should know Dawn, different change can be made and replace equivalent, in the case of without departing substantially from the connotation of the present invention and scope.Additionally, can Carry out many places amendment make a certain special circumstances, material, material composition, technique, processing step adaptation the objective of the present invention, spirit and Scope.These type of amendments all should be in the range of appended claims disclosure.

Figure 186 A is the schematic cross section of internal storage location 1350 according to the present invention respectively.Internal storage location 1350 include as The substrate 12 of the first conductivity type such as p-type conductivity type.Substrate 12 is made by silicon is special, but also can by such as germanium, The semi-conducting material composition that germanium silicon, GaAs, CNT etc. are known in the art.In some embodiments of the invention, substrate 12 It can be the bulk material of semiconductor chip.In terms of design alternative angle, in other embodiments, substrate 12 can be to be embedded into the second Conductivity type well, or as the second conductivity type semiconductor chip bulks such as N-shaped the first conductivity type well (figure do not have Embody).Describing for convenience, it is quasiconductor bulk material that substrate 12 generally charts, as shown in Figure 186 A.

Substrate 12 comprises the buried layer 22 of the second conductivity type such as N-shaped.Buried layer 22 can pass through ion implanting work Skill is formed in substrate 12 material.Or, buried layer 22 also can epitaxial growth portion on the substrate 12.

The floater area 24 of the first conductivity type such as p-type, is by bitline regions 16, source electrode line district 18 and insulating barrier up 62 surround, and side is surrounded by insulating barrier 26, and bottom is surrounded by buried layer 22.When injecting buried layer 22, buoyancy aid 24 can be embedding A part for former substrate 12 above layer 22.Or, buoyancy aid 24 can epitaxial growth.In terms of design alternative angle, according to buried layer 22 With the generation type of buoyancy aid 24, buoyancy aid 24 can have in the doping in some embodiments as substrate 12, or other embodiments The different doping of requirement.

Insulating barrier 26 (as such as shallow trench isolation (STI)) material is the material of silicon dioxide etc, although it can be used His insulant.When forming a memory subassembly during multiple unit 1350 are integrated into an array 1380, insulating barrier 26 meeting Unit 1350 is isolated with adjacent unit 1350.Buried region 22 is can be located at internal, it is allowed to buried region 22 is continuous bottom insulating barrier 26, As shown in Figure 186 A.Or, can be located at bottom, buried region 22 bottom insulating barrier 26, such as another reality of internal storage location 1350 in Figure 186 B Execute shown in example cross section.This requires more shallow insulating barrier 28, is kept apart by floater area 24, but allows buried layer 22 at figure In cross section vertical orientations shown in 186A continuously.For simplicity, the most continuous buried region 22 it Internal storage location 1350 can be shown since then.

There is the bitline regions 16 of the second conductivity type such as n-type, be present in floater area 24 and be exposed to surface 14. According to any known and injection technology of art Special use, bitline regions 16 is formed at composition lining by injection technology Above the material at the end 12.Or, form bitline regions 16 by solid state diffusion process.

There is the source electrode line district 18 of the second conductivity type such as n-type, be present in floater area 24 and be exposed to surface 14.According to any known and injection technology of art Special use, source electrode line district 18 is formed at by injection technology Constitute above the material of substrate 12.Or, form source electrode line district 18 by solid state diffusion process.

Internal storage location 1350 be asymmetric it, be the region more than bitline regions 16, the region in source electrode line district 18.With bit line Coupling between district 16 and floating gate 60 is comparatively, bigger source electrode line district 18 produces between source electrode line district 18 and floating gate 60 Give birth to higher coupling.

Floating gate 60 is between bitline regions 16 and source electrode line district 18, and is positioned at above floater area 24.Floating gate 60 passes through Floater area 24 is kept apart by insulating barrier 62.Insulating barrier 62 material can be silicon dioxide and/or other dielectric materials, including high K Dielectric material etc., but be not limited only to, peroxidating tantalum, titanium oxide, zirconium oxide, hafnium oxide and/or aluminium oxide.Floating gate 60 can be by, Such as polycrystalline silicon material or metal gate electrode, as tungsten, tantalum, titanium and its nitride are made.

Unit 1350 is a single floating polysilicon moving grid internal storage location.Therefore, unit 1350 can be with the complementary metal of typical case Oxide semiconductor (CMOS) technique is complementary.Floating gate 60 polycrystalline silicon material can deposit together with the door of logic transistor and become Shape.Can contrast with the flash memory in grating assembly that such as changes, wherein second polysilicon gate (such as control gate) changes at poly floating Above grid (see Fig. 4 .6 of page such as 197, " not volatibility semiconductor memory ", W.D.Brown and J.E.Brewer " Brown "), Hereby it is all hereby incorporated by reference.This double (or multiple) polysilicon layer of repeatedly grid internal storage location Typical requirements processes, Wherein first polysilicon (such as floating gate) can deposit after second polysilicon (such as control gate) layer is formed and become Shape.

Unit 1350 includes multiple terminal: is connected electrically to bit line (BL) terminal 74 of bitline regions 16, is connected electrically to source Source electrode line (SL) terminal 72 in polar curve district 18, is connected electrically to burying well (BW) terminal 76 and being connected electrically to lining of buried layer 22 The substrate terminal 78 at the end 12.Floating gate 60 is without any electrical connection.Therefore, floating gate 60 floats and as not volatibility memory field Use.

Figure 186 C is the equivalent circuit representation of internal storage location 1350.Internal storage location 1350 includes that metal-oxide is partly led Body (MOS) transistor 20, is made up of bitline regions 16, floating gate 60, source electrode line district 18 and floater area 24, and dipole elements 30a and 30b is then by burying wellblock 22, floater area 24 and bitline regions 16 or source electrode line district 18 is constituted.

Memory subassembly 1350 also includes dipole elements 30c, is made up of bitline regions 16, buoyancy aid 24 and source electrode line district 18.For The definition of drawing, dipole elements 30c individually shows in Figure 186 D.

Figure 186 E describes the internal storage location 1350 of a ranks arrangement, and (four exemplary memory unit 1350 are expressed as 1350a, 1350b, 1350c and 1350d) exemplary memory array 1380.In the appearance of exemplary array 1380 much but not Must be in all figures, when described operation have one (or multiple, " selected it " internal storage location in certain embodiments) When 1350, the representative representative that internal storage location 1350a is a selected memory unit 1350.In these figures, have The internal storage location 1350b of representativeness is one and shares, with selected representative internal storage location 1350a, the unselected internal storage location gone together The representative of 1350, representative internal storage location 1350c is one and selected representative internal storage location 1350a to be shared and goes together it The representative of unselected internal storage location 1350, and representative internal storage location 1350d, be a deposit receipt interior with selected representativeness Unit 1350a does not share the representative of the unselected internal storage location 1350 of ranks.

Figure 186 E has source electrode line 72a to 72n, bit line 74a to 74p, buries well terminal 76a to 76n and substrate terminal 78. Every source line in 72a to 72n is relevant with the single file of internal storage location 1350, and be coupled to each internal storage location of this row 1350 it In source electrode line district 18.Each bit line in 74a to 74p is single-row relevant with internal memory 1350, and is coupled to each interior deposit receipt of these row On the bitline regions 16 of unit 1350.

In array 1380, all there is substrate 12 all positions.Those of ordinary skill in the art should notify, one or more ends End 78 is present in one or more position, from the point of view of design alternative angle.These technicians also should notify when exemplary array 1380 in Figure 186 E, occurs with single continuous array, then a lot of other tissues and layout are exactly possibility.Such as, wordline Divisible or buffering, bit line divisible or buffering, source electrode line divisible or buffering, array 1380 is divided into the subnumber of two or more Group and/or control circuit, such as word decoder, column decoder, segmentation device, sense amplifier, write amplifier can be arranged in Around exemplary array 1380, or it is middle to insert array 1380 subnumber group.Therefore, the one exemplary embodiment in the present invention, spy Levy, design option etc. is construed as limiting in no instance.

Figure 187 is flow process Figure 100 of a memory subassembly operation.In event 102, when memory subassembly is energized first, Memory subassembly is in original state, and wherein the Nonvolatile memory part of this assembly is set to a predetermined state.In event 104 In, memory subassembly 1350 runs under volatibility operator scheme.But, power-off or have a power failure suddenly, or other event terminations any Or when disturbing the power supply of memory subassembly 1350 of the present invention, the content of volatile memory is deposited in the not volatibility in event 106 In depositing, this process is referred to as " covering " (event 106) process, and the loss of data in volatile ram.Performing backup behaviour Also can cover during work, when volatibility operated for 104 stage and/or user manually indicates any time of backup regular Carry out.When backup operation, the content of volatile ram copies in Nonvolatile memory, and volatile ram is energized all the time, Make the content of volatile ram in volatile ram.Or, owing to volatile ram operation is stored up than Nonvolatile memory Deposit volatile ram content and consume more electricity, then this device can in any period of its at least predefined phase on the shelf It is arranged for carrying out masking process, thus transfers to, in Nonvolatile memory, save electricity by the content in volatile ram. Giving one example, this predefined phase can be about 30 minutes, but certainly, the present invention is not limited only to this stage, due to this device Can than perform the masking process stipulated time longer it, arbitrary predefined phase internal program designs, and thinks over the most volatile The reliability of property internal memory.

When covering operation, after the content in volatile ram being moved on to not in volatile ram, memory subassembly 1350 is i.e. Shutdown, power supply will not re-supply to volatile ram.At this moment, the number of storage during memory subassembly still retains not volatile ram According to.The Power resumption when event 108, the content in nonvolatile memory, by transferring to volatile by nonvolatile memory content Property internal memory in and recovered, this process be referred to as " recovery " process, after recovery, when event 110 replacement memory subassembly, Memory subassembly 1350 resets to original state 102 and again with volatile mode operation, in event 104.

In one embodiment, volatile ram (such as floating gate 60) is not initialised to positive charge, in event 102 In.When unit 1350 is energized, unit 1350 stores memory information (being i.e. saved in the data in internal memory), as memory subassembly Electric charge in 1350 buoyancy aids 24.Electric charge regulation in buoyancy aid 24 flows through the electric current of memory subassembly 1350 (from BL terminal 74 to SL eventually End 72).The electric current flowing through memory subassembly 1350 may be used to determine the state of unit 1350.Because not volatile memory elements (example Such as floating gate 60), it is initialized to carry a positive charge, so any cell current difference is the result of buoyancy aid 24 charge difference.

Under easy disabling mode, internal storage location 1350 can be performed multi-mode operation: preserve, read, write logical value-1 and write Logical value-0 operates.

Figure 188 describes the preservation operation of memory array 1380, and this array is made up of multiple internal storage locations 1350.By Apply forward feedback bias in BW terminal 76, in BL terminal 74 and SL terminal 72, apply zero-bias, perform preservation operation.Even Connect BW terminal and be applied to the forward feedback bias in buried layer district, the state of its connected internal storage location 1350 will be kept.

From the point of view of the equivalent circuit representation of the internal storage location 1350 shown in Figure 186 C, internal storage location 1350 includes n-p-n Dipole elements 30a and 30b, respectively by burying wellblock 22 (collector region), buoyancy aid 24 (base region) and bitline regions 16 or source electrode line district 18 (emitter region) forms.

Figure 189 A is that floater area 24 is positively charged and positive bias voltage acts on when burying wellblock 22 interior in n-p-n dipole elements The energy band schematic diagram of 30a.The energy band diagram of n-p-n dipole elements 30b is similar to shown in Figure 189 A, wherein source electrode line district 18 (connecting SL terminal 72) replaces bitline regions 16 (being connected to BL terminal 74).Dotted line represents in n-p-n transistor 30a different regions it Fermi level.According to well known in the art it, fermi level be positioned at represent valance band top the solid line 17 (end of band gap Portion) and the band gap that represents bottom conduction band between the solid line 19 at (band gap top) in.When buoyancy aid 24 is positively charged, one The state of individual counterlogic value-1, bipolar transistor 30a and 30b can be opened, and the positive charge in floater area reduces base The electron stream energy barrier of polar region.Once injecting floater area 24, act in positive bias and bury wellblock 22 times, electrons is swept into burying Wellblock 22 (being connected to BW terminal 76).Due to positive bias, by ionization by collision mechanism, electronics accelerates and produces an extra heat Carrier (hot hole and thermoelectron to).Thus generation thermoelectron flow into BW terminal 76, the hot hole of generation simultaneously also with and his like Enter floater area 24.This process has recovered the electric charge on floater area 24, and remains stored in the electric charge in floater area 24, thus N-p-n bipolar transistor 30a and 30b is kept to be in opening by BW terminal 76 when burying and applying positive bias on wellblock 22.

When buoyancy aid 24 band neutral charge (voltage of buoyancy aid 24 is identical with the voltage on ground connection bitline regions 16), a correspondence is patrolled Collect the state of value-0, do not have electric current can flow through n-p-n transistor 30a and 30b.Dipole elements 30a and 30b remain off, Will not be collided ionization.Subsequently, logical value-0 state purgation internal storage location is maintained at logical value-0 state.

Figure 189 B is floater area 24 band neutral charge and bias voltage acts on when burying wellblock 22 interior in n-p-n dipole elements The energy band schematic diagram of 130a.In this condition, by the band gap energy level of solid line 17A and 19A encirclement in n-p-n dipole elements The zones of different of 30a is difference.Because the voltage of floater area 24 and bitline regions 16 be identical it, fermi level be constant it, Thus between bitline regions 16 and floater area 24, create an energy barrier.Solid line 23 represents, in order to reference to mesh it, bitline regions Energy barrier between 16 and floater area 24.It is floating that energy barrier avoids electron stream to flow to from bitline regions 16 (being connected to BL terminal 74) Body district 24.Therefore, n-p-n dipole elements 30 remains closed.

In preservation operation described in Figure 188, the most not selected internal storage location.On the contrary, unit is buried well terminal 76a Embark on journey to 76n selected, may be selected to be independent rows, multirow or constitute all row of array 1380.

In one embodiment, the bias condition of the preservation operation of internal storage location 1350 is: the voltage of 0 volt acts on BL In terminal 74, the voltage of 0 volt acts in SL terminal 72, and the positive voltage of such as+1.2 volts of sizes acts on BW terminal 76 On, the voltage of 0 volt acts in substrate terminal 78.In other embodiments, different voltages may act on internal storage location 1350 Different terminals on, from design alternative angle consider, therefore, described exemplary voltage is not intended that restriction.

The read operation of internal storage location 1350 and memory cell array 1380 can describe in Figure 190 A and 190B simultaneously.Appoint What reading figure known in the art can be used along with internal storage location 1350.Example includes, such as, " uses monocrystal on SOT Pipe gain unit internal memory design " disclosed in readings scheme, author T.Ohsawa et al., 152-153 page, technical digest, 1991 The IEEE ISSCC that February in year holds) (" Ohsawa-1 ") and " 18.5ns a 128Mb with elemental floating body SOI DRAM ", Ohsawa et al., 458-459 page, page 609, IEEE ISSCC (" Ohsawa-2 ") in 1994, Both are fully incorporated herein middle as reference hereby.

The amount of charge of storage in buoyancy aid, can be read by the cell current of monitoring internal storage location 1350.Work as internal storage location 1350 are in logical value-1 state when having hole in floater area 24, then internal storage location should have higher cell current (such as The electric current of SL terminal 72 is flowed to from BL terminal 74), contrast unit 1350 is in logical value-0 state, without hole in floater area 24 Time situation.One reading circuit being typically connected in BL terminal 74, can be used to measure the data mode of internal storage location.

Read operation can be high (see Figure 190 A) by active word-line, or high (see Figure 190 B) scheme of active source electrode line performs. In an active word-line senior middle school, positive bias acts in selected BL terminal 74, and no-voltage acts in selected SL terminal 72, Zero or positive voltage act in selected BW terminal 76, no-voltage acts in substrate terminal 78.

In an exemplary embodiment, the voltage of about 0.0 volt acts in selected SL terminal 72a, about+0.4 volt The voltage of spy acts on selected bitline terminal 74a, and the voltage of about+1.2 volts acts on selected well terminal 76a of burying, about The voltage of 0.0 volt acts in substrate terminal 78.All unselected bitline terminal 74b to 74p are applied with the electricity of 0.0 volt Pressure or float, unselected SL terminal 72b to 72p is applied with voltage or the floating of+0.4 volt, and unselected BW terminal 76b The voltage of ground connection or applying+1.2 volts the state of unselected cells 1350, the voltage effect of about 0.0 volt can be maintained to 76p In substrate terminal 78.Figure 190 A give in selected representative internal storage location 1350a and memory array 1,380 three unselected The bias condition of representative internal storage location 1350b, 1350c and 1350d, each possesses the bias condition of uniqueness.This area Affiliated those of ordinary skill should notify the other embodiments of the present invention, can use other group being biased from design alternative angle Close.These technicians simultaneously it should also be appreciated that in other embodiments first and second kinds of conductivity type can be interchangeable, And relative bias can be changed.

In an active source electrode line senior middle school, a positive voltage acts in selected SL terminal 72, and no-voltage acts on choosing In fixed BL terminal 74, zero or positive voltage act on selected BW terminal 76, no-voltage acts in substrate terminal 78.

In an exemplary embodiment, the voltage of about+0.4 volt acts in selected SL terminal 72a, about 0.0 volt The voltage of spy acts on selected bitline terminal 74a, and the voltage of about+1.2 volts acts on selected well terminal 76a of burying, about The voltage of 0.0 volt acts in substrate terminal 78.All unselected bitline terminal 74b to 74p be applied with+0.4 volt it Voltage or floating, unselected SL terminal 72b to 72p is applied with voltage or the floating of 0.0 volt, and unselected BW terminal 76b to 76p can ground connection or the voltage of applying+1.2 volts, maintain the state of unselected cells 1350, the voltage of about 0.0 volt Act in substrate terminal 78.Figure 190 B gives in selected representative internal storage location 1350a and memory array 1380, and three are not The bias condition of selected representative internal storage location 1350b, 1350c and 1350d, each possesses the bias condition of uniqueness.This Those of ordinary skill belonging to field should be notified, and the other embodiments of the present invention can use its that be biased from design alternative angle Its combination.These technicians simultaneously it should also be appreciated that in other embodiments first and second kinds of conductivity type can carry out Exchange, and relative bias can be changed.

Write logical value-0 operation of one independent memory unit 1350, is shown in the introduction of Figure 191 A and 191B.At Figure 191 A In, back bias voltage acts in SL terminal 72, and no-voltage acts in BL terminal 74, zero or positive voltage act on selected BW terminal On 76, no-voltage acts in substrate terminal 78.Under these conditions, the buoyancy aid 24 of selected unit 1350 and source electrode line district 18 it Between any p-n junction be positive bias, the emptying any hole from buoyancy aid 24.Because SL terminal 72 is by multiple internal storage location 1350 institutes Sharing, so logical value-0 can be written in internal storage location 1350, wherein internal storage location 1350a and 1350b shares same simultaneously Individual SL terminal 72a.

In a specific unrestricted embodiment, the voltage of about-0.5 volt acts in source electrode line terminal 72, about The voltage of 0.0 volt acts on bitline terminal 74, and the voltage of about 0.0 volt or+1.2 volts acts in BW terminal 76, about The voltage of 0.0 volt acts in substrate terminal 78.From the point of view of design alternative angle, these magnitudes of voltage, can be because of only for demonstration use Change for embodiment changes.Therefore, the one exemplary embodiment in the present invention, feature, bias value etc. are under any circumstance It is not construed as limiting.

In Figure 191 B, back bias voltage acts in BL terminal 74, and no-voltage acts in SL terminal 72, zero or positive voltage work For selected BW terminal 76, no-voltage acts in substrate terminal 78.Under these conditions, the buoyancy aid of selected unit 1350 Any p-n junction between 24 and bitline regions 16 is positive bias, the emptying any hole from buoyancy aid 24.Because BL terminal 74 is at internal memory Array 1380 is shared by multiple internal storage locations 1350, so logical value-0 can be written in internal storage location 1350, wherein interior Memory cell 1350a and 1350c shares same BL terminal 74a simultaneously.

In a specific unrestricted embodiment, the voltage of about-0.5 volt acts on bitline terminal 74, and about 0.0 The voltage of volt acts in source electrode line terminal 72, and the voltage of about 0.0 volt or+1.2 volts acts in BW terminal 76, about The voltage of 0.0 volt acts in substrate terminal 78.From the point of view of design alternative angle, these magnitudes of voltage, can be because of only for demonstration use Change for embodiment changes.Therefore, the one exemplary embodiment in the present invention, feature, bias value etc. are under any circumstance It is not construed as limiting.

All there is a defect in the operation of above-mentioned write logical value-0: shares same SL terminal 72 (the first type-row write Enter logical value-0), or all internal storage locations 1350 of same BL terminal 74 (the second type-row write logical value-0) together with Step write, thus cause logical value-0 being write in independent memory unit 1350.In order to any binary data is write In the internal storage location 1350 of difference, all internal storage locations to be written perform write logical value-0 operation first, is then Must be written into one or more write logical values-1 operation that logical value-1 is upper.

Figure 192 A and 192B uses active word-line high scheme and active source electrode line high scheme respectively, to write logical value-1 behaviour It is described explanation.In active word-line high scheme, apply following bias condition: positive voltage acts on selected BL eventually End 74 on, no-voltage acts in selected SL terminal 72, zero or positive voltage act in selected BW terminal 76, no-voltage make For substrate terminal 78.One ratio is applied to the positive voltage that in selected BL terminal 74, positive voltage is lower, act on unselected it In SL terminal 72 (the SL terminal 72b to 72n in such as Figure 192 A), and no-voltage acts on (example in unselected BL terminal 74 BL terminal 74b to 74p as in Figure 192 A).Or, unselected SL and BL terminal can be floated.

Owing to floating gate 60 is positively charged, electrons flows to BL eventually by selected internal storage location 1350a from SL terminal 72a End 74a.Bias condition configuration mode in selected terminal is as follows: the MOS assembly 20 of selected unit 1350a is in saturation (i.e. acting on the voltage of BL terminal 74 more than the pressure reduction between floating gate 60 voltage and MOS assembly 20 threshold voltage).Therefore, electricity Son can accelerate in the pinch off region of MOS assembly 20, thus produces hot carrier near bitline regions 16.Then the hole generated Can flow in buoyancy aid 24, make unit 1350a be in logical value-1 state.

In a specific unrestricted embodiment, the voltage of about+1.2 volts acts on bitline terminal 74, and about 0.0 The voltage of volt acts in source electrode line terminal 72, and the voltage of about 0.0 volt or+1.2 volts acts in BW terminal 76, about The voltage of 0.0 volt acts in substrate terminal 78；And the voltage of about 0.0 volt acts on unselected bit line terminal 74, about+ The voltage of 0.4 volt acts in unselected source electrode line terminal 72.From the point of view of design alternative angle, these magnitudes of voltage are only for showing Fan Yong, can be because the change of embodiment changes.Therefore, described one exemplary embodiment, feature, bias value etc. are in any feelings It is not construed as limiting under condition.

For share the internal storage location of colleague with selected internal storage location (such as unit 1350b), BL and SL terminal Ground connection, does not has electric current to flow through.These unit can be in holding pattern, and with the positive voltage acted in BW terminal 76.

For share the internal storage location of same column with selected internal storage location (such as unit 1350c), act on unselected Determine the positive bias in SL terminal and can cut off the MOS assembly 20 of these unit, thus cause not having electric current to flow through.Due to BW terminal 76 And the less difference between SL terminal 72, a less holding electric current can flow through these unit.While it is true, due to write behaviour Make that the charge life (in terms of millisecond magnitude) in (in terms of nanosecond order) relatively buoyancy aid 24 completes faster, therefore it is answered hardly Electric charge in this interruption buoyancy aid.

For do not share the internal storage location of colleague or same column with selected internal storage location (such as unit 1350d), SL Terminal band positive bias, and BL terminal ground connection.While it is true, the positive bias acted in SL terminal can be of a sufficiently low, thus avoid touching Hit the generation of ionization.These unit can be in holding pattern, and state logic value-1 purgation internal storage location can retain charge in In buoyancy aid 24, state logic value-0 purgation internal storage location then keeps neutral state.

Write logical value-1 operation of active source electrode line high scheme purgation is described by Figure 192 B, wherein applies following Bias condition a: positive voltage acts in selected SL terminal 72, and no-voltage acts in selected BL terminal 74, zero or just Voltage acts in selected BW terminal 76, and no-voltage acts in substrate terminal 78.One ratio is applied to selected SL terminal The positive voltage that on 72, positive voltage is lower, acts in unselected BL terminal 74 that (BL terminal 74b in such as Figure 192 B is extremely 74p), and no-voltage acts on (the SL terminal 72b to 72n in such as Figure 192 B) in unselected SL terminal 72.Or, unselected Fixed SL and BL terminal can be floated.

The electric capacity that positive charge on floating gate 60 couples with from source electrode line district 18, can open the MOS group of selected unit 1350a Part 20.Therefore, electrons flows to SL terminal 72a by selected internal storage location 1350a from BL terminal 74a.In selected terminal it Bias condition configuration mode is as follows: the MOS assembly 20 of selected unit 1350a be in saturation (i.e. act on SL terminal 72 it Voltage is more than the pressure reduction between floating gate 60 voltage and MOS assembly 20 threshold voltage).Therefore, electrons is at the folder of MOS assembly 20 Accelerate in disconnected district, thus near source electrode line district 18, produce hot carrier.Then the hole generated can flow in buoyancy aid 24, makes Unit 1350a is in logical value-1 state.

In a specific unrestricted embodiment, the voltage of about+1.2 volts acts in source electrode line terminal 72, about The voltage of 0.0 volt acts on selected bitline terminal 74, and the voltage of about 0.0 volt or+1.2 volts acts on BW terminal 76 On, the voltage of about 0.0 volt acts in substrate terminal 78；And the voltage of about 0.0 volt acts on unselected source electrode line eventually The voltage holding 72, about+0.4 volt acts on unselected bitline terminal 74.From the point of view of design alternative angle, these magnitudes of voltage Only for demonstration use, can be because the change of embodiment changes.Therefore, described one exemplary embodiment, feature, bias value etc. exist It is not construed as limiting.

For share the internal storage location of colleague with selected internal storage location (such as unit 1350b), act on unselected Determine the positive bias in BL terminal and can cut off the MOS assembly 20 of these unit, thus cause not having electric current to flow through.Due to BW terminal 76 And the less difference between SL terminal 72, a less holding electric current can flow through these unit.While it is true, due to write behaviour Make that the charge life (in terms of millisecond magnitude) in (in terms of nanosecond order) relatively buoyancy aid 24 completes faster, therefore it is answered hardly Electric charge in this interruption buoyancy aid.

For share the internal storage location of same column with selected internal storage location (such as unit 1350c), BL and SL terminal Ground connection, does not has electric current to flow through.These unit can be in holding pattern, and with the positive voltage acted in BW terminal 76.

For do not share the internal storage location of colleague or same column with selected internal storage location (such as unit 1350d), BL Terminal band positive bias, and SL terminal ground connection.While it is true, the positive bias acted in BL terminal can be of a sufficiently low, thus avoid touching Hit the generation of ionization.These unit can be in holding pattern, and state logic value-1 purgation internal storage location can retain charge in In buoyancy aid 24, state logic value-0 purgation internal storage location then keeps neutral state.

When power-off being detected, such as, when the power supply of user's switching units 1350, or power supply interrupts suddenly or because any Other reason, unit 1350 power supply the most temporarily interrupts, or due to the user's any particular command during backup operation, exists Data in floater area 24 are transferred in floating gate 60.This operation is referred to as " covering ", is described in Figure 193 A-193B.

Figure 193 A-193C describes the embodiment of a unit 1350 operation, performs volatile to the most volatile process covered, Injected by thermoelectron and operate.In order to perform to cover operation, apply following bias condition: a positive voltage acts on SL In terminal 72, no-voltage acts in BL terminal 74, zero or positive voltage act in BW terminal 76, no-voltage acts on substrate eventually On end 78.

In a specific unrestricted embodiment, the voltage of about+6.0 volts acts in source electrode line terminal 72, about The voltage of 0.0 volt acts on bitline terminal 74, and the voltage of about 0.0 volt or+1.2 volts acts in BW terminal 76, about The voltage of 0.0 volt acts in substrate terminal 78.From the point of view of design alternative angle, these magnitudes of voltage, can be because of only for demonstration use Change for embodiment changes.Therefore, described one exemplary embodiment, feature, bias value etc. are in no instance It is construed as limiting.

Figure 193 B is the cross-sectional view of unit 1350 in masking process when buoyancy aid 24 is positively charged.When buoyancy aid 24 positively charged Lotus/voltage, MOS assembly 20 and dipole elements 30c be in opening, and electronics flows to source electrode line district 18 (figure from bitline regions 16 The direction of arrow shown in 193B).Being in terminal 72 applying positive voltage in source electrode line district 18 encourages/promotes electronics to flow through buoyancy aid 24, to jump in the stop oxide layer between buoyancy aid 24 and floating gate 60 when reaching enough again, such electronics just can enter floating Grid 60 (see in Figure 193 B shown in arrow indication floating gate 60).Correspondingly, when the volatile memory of unit 1350 be in logical value- During 1 state (buoyancy aid 24 is positively charged), floating gate 60 is electronegative by the method for covering, as shown in Figure 193 B.

Figure 193 C is the cross-sectional view of unit 1350 in masking process when buoyancy aid 24 is neutral.When buoyancy aid 24 is neutral Time, MOS assembly 20 and dipole elements 30c are closed, and do not have electrons to flow through unit 1350.Correspondingly, unit is worked as When the volatile memory of 1350 is in logical value-0 state (buoyancy aid 24 is for time neutral), floating gate 60 is at the end of covering operation Keep positive charge, as shown in Figure 193 C.

One ratio is applied to the positive voltage that in SL terminal 72, positive voltage is lower and may also act in BL terminal 74, it is ensured that only The internal storage location 1350 carrying positive buoyancy aid 24 conducts electric current in covering operation.

Note: covering after operation terminates, the state of charge of floating gate 60 is complementary with the state of charge of buoyancy aid 24.Therefore, If the buoyancy aid 24 of internal storage location 1350 is positively charged in volatile memory, floating gate 60 is negative by carrying after covering operation Electric charge, and when the buoyancy aid 24 of internal storage location 1350 carries negative or neutral charge in volatile memory, floating gate layer 60 can hide At the end of covering operation positively charged.Electric charge/the state of floating gate 60 then depends on the state of buoyancy aid with the relation of non-algorithm, and many Covering of individual unit occurs with parallel way, therefore covers speed of operation and is exceedingly fast.

When unit 1350 Power resumption, unit 1350 state existed on floating gate 60 can return in floater area 24. Recovery operation (never volatile ram recovers to the data of volatile ram) is shown in that Figure 194 A～194C introduces.Performing recovery behaviour Before work, buoyancy aid 24 is set to neutral state, buoyancy aid state when i.e. memory subassembly 1350 removes power supply.In order to perform recovery operation, Apply following bias condition: a positive voltage acts in BL terminal 74, and no-voltage acts in SL terminal 72, zero or positive electricity Pressure acts in BW terminal 76, and no-voltage acts in substrate terminal 78.

In a specific unrestricted embodiment, the voltage of about+3.0 volts acts on bitline terminal 74, and about 0.0 The voltage of volt acts in source electrode line terminal 72, and the voltage of about 0.0 volt or+1.2 volts acts in BW terminal 76, about The voltage of 0.0 volt acts in substrate terminal 78.From the point of view of design alternative angle, these magnitudes of voltage, can be because of only for demonstration use Change for embodiment changes.Therefore, described one exemplary embodiment, feature, bias value etc. are in no instance It is construed as limiting.

Figure 194 B is the cross-sectional view of unit 1350 in recovery process when buoyancy aid 24 electronegative property.On floating gate 60 it Between the positive voltage on negative charge and BL terminal 74 bitline regions 16 and floater area 24 near floating gate 60, generation one is powerful Electric field, and this makes it possible to band and the most significantly bends near door and bit line node overlapping area, causes electronics from valance band It is tunnelled to conduction band, hole is stayed in valance band.Tunneling through the electronics of band drain leakage can be become, and hole is injected into To floater area 24 hole charge that becomes generation logical value-1 state.In this area, this process is referred to as interband tunnel effect Should, or gate-induced drain leakage (GIDL) mechanism, such as " low-power and high speed embedded memory are being used gate-induced drain leakage (GIDL) unit of 1T-DRAM without the electric capacity design of electric current ", Yoshida et al., 913-918 page, International Electro assembly meeting in 1992 years View (" Yoshida ") (particularly Fig. 2 and 6 and Fig. 9 of page 4 of page 3) there is explaination, is hereby fully incorporated herein middle conduct Reference.

Figure 194 C is the cross-sectional view of unit 1350 in recovery process when buoyancy aid 24 is positively charged.Floating gate 60 and bit line Positive charge in district 16 will not produce powerful electric field, orders about hole and is injected in buoyancy aid 24.Therefore, during buoyancy aid 24 can be maintained at Sexual state.

It can be seen that when floating gate 60 perform cover after positively charged, the volatile ram of buoyancy aid 24 can return to band Neutral charge (logical value-0 state), but when floating gate 60 is electronegative, the volatile ram of buoyancy aid 24 just can return to band Electric charge (logical value-1 state), thus before covering operation, return to the initial condition of buoyancy aid 24.Note: this process is with non-calculation Mode occurs, because floating gate 60 state determines the state of buoyancy aid 24 recovery without carrying out reading, understand or measure.On the contrary Ground, recovery process occurs automatically, potential difference drive.Correspondingly, this process is the order of magnitude, and ratio requires the speed of algorithm intervention more Hurry up.

After recovering internal storage location 1350, floating gate 60 resets to default conditions, such as positive status so that each floating gate 60 have a known state before performing another and covering operation.Reset by using interband tunneled holes to be injected into floating gate 60 Principle operate, see Figure 195.

Reset and use the principle similar with recovery operation.Electronegative floating gate 60 can produce one generate hot hole it Electric field.Most of hot holes of generation are injected in buoyancy aid 24, and smaller portions are injected in floating gate 60.Hole is injected and is only sent out Raw in the unit 1350 of electronegative floating gate 60.Therefore, before reset operation terminates, all floating gates 60 are initialized to Positively charged.

In a specific unrestricted embodiment, the voltage of about+3.0 volts acts on bitline terminal 74, and about 0.0 The voltage of volt acts in source electrode line terminal 72, and the voltage of about 0.0 volt or+1.2 volts acts in BW terminal 76, about The voltage of 0.0 volt acts in substrate terminal 78.From the point of view of design alternative angle, these magnitudes of voltage, can be because of only for demonstration use Change for embodiment changes.Therefore, described one exemplary embodiment, feature, bias value etc. are in no instance It is construed as limiting.Bias condition is with the bias condition of recovery operation.While it is true, owing to injecting the number of cavities ratio in floating gate 60 The number of cavities being injected in buoyancy aid 24 to be lacked, and the operation that resets is slower than recovery operation.Negative voltage may also act on source electrode line terminal 72 or bury in well terminal 76, to ensure not having hole accumulation in the internal storage location 1350 of positively charged floating gate 60.

Internal storage location 1350 can manufacture in many ways.Figure 196 and 197 gives the system obtaining internal storage location 1350 Make example process.Figure arranges in three relevant view group modes, and often first figure of group is top view, and often second figure of group is this The vertical cross-section diagram of group first figure top view of I-I ', and often organize the water that the 3rd figure is this group II-II ' first figure top view Plane section figure.Therefore, Figure 196 A, 196D, 196G, 196J, 196M, 196P and 197A, 197D, 197G, 197J, 197M and 197P For the internal storage location 1350 manufacture process a series of top view of different phase purgation, Figure 196 B, 196E, 196H, 196K, 196N and 196Q and 197B, 197E, 197H, 197K, 197N and 197Q for being marked with the respective vertical cross-section diagram of I-I ', and Figure 196 C, 196F, 196I, 196L, 196O and 196R and 197C, 197F, 197I, 197L, 197O and 197R cut for the respective level being marked with II-II ' Face figure.During in Figure 196 and 197, the consistent reference number of Figure 186 of appearance to 195 represents drawing in the early time, foregoing descriptions is similar, consistent Or analogous structure.Here " vertically " represent moving towards up and down in top view, and " level " represents that the left and right in top view is moved towards.? In one of internal storage location 1350 physical embodiments, two sectional views are all vertical with the surface of semiconductor subassembly.

Figure 196 A to 196C gives the initial step of process.During exemplary 130 nanometer (nm), thickness is about The thin silicon oxide layer 82 of 100A can be grown on substrate 12 surface, the precipitation of the most about 200A polysilicon 84.In turn, it is possible to Followed by it is about the precipitation of 1200A silicon nitride layer 86.Can use other procedure geometric structure, such as 250nm, 180nm, 90nm, 65nm etc..Similarly, the protective layer 82,84 and 86 of other quantity thickness and combination can use according to design alternative.One Individual opened areas becomes the pattern of irrigation canals and ditches 80 can use photoetching process molding.Then silicon oxide 82, polysilicon 84, silicon nitride layer 86 Pattern can be formed by photoetching process, be etched further according to silicon etching method, produce irrigation canals and ditches 80.

Shown in Figure 196 D to 196F, after have a silicon oxidizing process, can in irrigation canals and ditches 80 growing silicon oxide thin film, become insulation Layer 26.During an exemplary 130nm, the growth of silicon oxide of about 4000A.Perform chemical mechanical planarization process afterwards, right The silicon oxide film of generation is ground, and such silicon oxide layer is to put down it relative to silicon face.In other embodiments, insulating barrier Different height is arranged for silicon face at 26 tops.Be removed after silicon nitride layer 86 and polysilicon layer 84, after have wet Etching process removes silicon oxide layer 82 (with one of formation partial oxidation silicon thin film in front irrigation canals and ditches 80 region).Other processes, several What structure such as 250nm, 180nm, 90nm, 65nm etc. can use.Similarly, other insulating layer materials, height and thickness with And operation stage substitutes operation and can use according to design alternative.

Shown in Figure 196 G to 196I, perform ion implanting step and form burying of the second conductivity (such as N-shaped conductivity) Zhi Ceng district 22.Ion implantation energy optimizes as follows: deep bottom the ratio insulating barrier 26 of formation bottom buried layer district 22.Buried layer 22 The last floater area 24 of the first conductivity type (such as p-type) is separated with substrate 12 isolation.

As shown in Figure 196 J to 196L, silicon oxide or high dielectric material door insulating barrier 62 are formed at silicon face (such as one About 100A during individual exemplary 130nm), followed by precipitate (such as an exemplary 130nm mistake for polysilicon or metal gate 60 About 500A in journey).

Figure 196 M to 196O, performs lithography step and makes layer 62 and 60 shape, and opened areas becomes source electrode line district 18.Next For polysilicon and the etching of silicon oxide layer.Then perform ion implanting step and form source electrode line district 18 or the second conductivity (example Such as N-shaped conductivity).Other processes, geometry such as 250nm, 180nm, 90nm, 65nm etc. can use.Similarly, other Door and the door insulant of different-thickness use according to design alternative.

Figure 196 P to 196R, performs another lithography step and makes layer 62 and 60 shape, and opened areas becomes bitline regions 16.Connect down Carry out the etching for polysilicon and silicon oxide layer.Then bitline regions 16 or the second conductivity of ion implanting step formation are performed (such as N-shaped conductivity).Other processes, geometry such as 250nm, 180nm, 90nm, 65nm etc. can use.Similarly, Door and the door insulant of other different-thickness use according to design alternative.

Another manufacture process of the relevant unit of Figure 197 A to 197R 1350.Process in Figure 197 A to 197R, only Relate to one to shape with etching program to determine the floating gate 60 of internal storage location 1350.Therefore, this process and Standard Complementary Metal-oxide semiconductor (MOS) (CMOS) process compatible.Higher capacitance coupling between source electrode line district 18 and floating gate 60, is to pass through The floating gate 60 shown in the unit 1350 final structure extension to region, source electrode line district 18 in Figure 197 P to 197R and realize it. As follows into the floating gate 60 width configuration mode in source electrode line district 18 it is noted that extend: being subsequently injected into technique can be at door 60 times Produce a continuous channel region.Above-mentioned Roizin gives a CMOS-manufacturing floating gate nonvolatile memory unit and holds concurrently Hold the example of process.

The initial step of alternative Process, similar to the order in Figure 196 A to 196C.Figure 197 A to 197C give process Initial step.During exemplary 130 nanometer (nm), the thin silicon oxide layer 82 of thickness about 100A can be grown in substrate On 12 surfaces, the precipitation of the most about 200A polysilicon layer 84.In turn, it is possible to be followed by about 1200A silicon nitride layer 86 heavy Form sediment.Other procedure geometric structure, such as 250nm, 180nm, 90nm, 65nm etc. can be used.Similarly, other quantity thickness and The protective layer 82,84 and 86 of combination can use according to design alternative.The pattern that one opened areas becomes irrigation canals and ditches 80 can be transported Use photoetching process molding.Then silicon oxide 82, polysilicon 84, silicon nitride layer 86 can form pattern by photoetching process, further according to Silicon etching method is etched, and produces irrigation canals and ditches 80.

Shown in Figure 197 D to 197F, after have a silicon oxidizing process, can in irrigation canals and ditches 80 growing silicon oxide thin film, become insulation Layer 26.During an exemplary 130nm, the growth of silicon oxide of about 4000A.Perform chemical mechanical planarization process afterwards to product The silicon oxide film of life is ground, and such silicon oxide layer is to put down it relative to silicon face.In other embodiments, insulating barrier 26 Different height is arranged for silicon face at top.Be removed after silicon nitride layer 86 and polysilicon layer 84, after have wet corrosion Quarter, process removed silicon oxide layer 82 (with one of formation partial oxidation silicon thin film in front irrigation canals and ditches 80 region).Other processes, geometry Structure such as 250nm, 180nm, 90nm, 65nm etc. can use.Similarly, other insulating layer materials, height and thickness and Operation stage substitutes operation and can use according to design alternative.

Shown in Figure 197 G to 197I, perform ion implanting step, form burying of the second conductivity (such as N-shaped conductivity) Zhi Ceng district 22.Ion implantation energy optimizes as follows: deep bottom the ratio insulating barrier 26 of formation bottom buried layer district 22.Buried layer 22 The last floater area 24 of the first conductivity type (such as p-type) is separated with substrate 12 isolation.

Shown in Figure 197 J to 197L, silicon oxide or high dielectric material door insulating barrier 62 are formed at silicon face (such as at one About 100A during exemplary 130nm), followed by precipitate (such as an exemplary 130nm process for polysilicon or metal gate 60 Middle about 500A).Other processes, geometry such as 250nm, 180nm, 90nm, 65nm etc. can use.Similarly, other are not Door and the door insulant of stack pile use according to design alternative.

Figure 197 M to 197O, performs lithography step and makes layer 62 and 60 shape, and opened areas becomes bitline regions 16 and source electrode line District 18.Next it is the etching of polysilicon and silicon oxide layer.Contrary with the previous operation shown in Figure 196 A to 196R, work as bit line When the region in district 16 and source electrode line district 18 determines simultaneously, only require a photoetching and etch sequence.

Figure 197 P to 197R gives the example injection process subsequently of the second conductivity type (such as N-shaped conductivity). In region around bitline regions 16, owing to floating grid region 60 is relatively long, ion implanting will not be deep into floating gate 60 purgation Region (see Figure 197 Q).In region around source electrode line district 18, due to floating grid region 60 relative narrower, ion implanting can be goed deep into To floating gate 60 purgation region, cause floating gate 60 purgation continuous source polar curve district 18 (see Figure 197 R).Therefore, to source electrode line district 18 Floating gate 60 zones of extensibility on define metal-oxide semiconductor (MOS) (MOS) capacitor.

Figure 198 is the sectional view of another embodiment of internal storage location 1350.Shown in unit 1350 and Figure 186 A or 186B Unit similar, define an interstitial area 17 at bitline regions 16 areas adjacent.Therefore, nothing between floating gate 60 and bitline regions 16 Overlap.The operation of unit 1350, similar to the operation having been described above in Figure 187 to 195.Volatile ram operates in the same manner Carry out, and the electric charge in buoyancy aid 24 regulates the characteristic of unit 1350 in volatile operating process.While it is true, cover the effect of operation Rate, can increase because of the existence in gap 17." source side of flash eprom application is injected and is optimized ", D.K.Y.Liu etc. People, page 315～318, technical digest, International Electro assembly meeting (" Liu ") in 1980, such as, describe thermoelectron and be injected into In volatibility internal storage location, the efficiency of floating gate does not improves problem.

Described in Figure 193 A to 193C, following bias condition is used to execution and covers operation: a positive voltage acts on SL eventually On end 72, no-voltage acts in BL terminal 74, zero or positive voltage act in BW terminal 76, and no-voltage acts on substrate eventually On end 78.

When buoyancy aid 24 positively charged/voltage time, MOS assembly 20 and dipole elements 30c be in opening, and electronics is from bit line District 16 flows to source electrode line district 18 (direction of arrow shown in Figure 199 A).Due to the existence of region, bitline regions 16 internal clearance 17, source electrode Applied pressure reduction between line district 18 and bitline regions 16, and the big transverse electric field meeting of one of generation.This transverse electric field can encourage/promote Electronics flows through buoyancy aid 24, jumps in the stop oxide layer between buoyancy aid 24 and floating gate 60 when reaching enough again.And floating gate Therefore potential difference (in part because source electrode line district 18 and the coupling on surface 14) between 60 and one of generation big longitudinal electric field can be Produce.So electronics just can enter floating gate 60 (see in Figure 199 A shown in arrow indication floating gate 60).Correspondingly, unit is worked as When the volatile memory of 1350 is in logical value-1 state (buoyancy aid 24 is positively charged), floating gate 60 is electronegative by the method for covering Lotus, as shown in Figure 199 A.

Figure 199 B is the cross-sectional view of unit 1350 in masking process when buoyancy aid 24 is neutral.When buoyancy aid 24 is neutral Time, MOS assembly 20 and dipole elements 30c are closed, and do not have electrons to flow through unit 1350.Correspondingly, unit is worked as When the volatile memory of 1350 is in logical value-0 state (buoyancy aid 24 is for time neutral), floating gate 60 terminates covering operation Time, keep positive charge, as shown in Figure 199 B.

Covering after operation terminates, the state of charge of floating gate 60 is complementary with the state of charge of buoyancy aid 24.Therefore, if interior When the buoyancy aid 24 of memory cell 1350 is positively charged in volatile memory, floating gate 60 is electronegative by meeting after covering operation, And when the buoyancy aid 24 of internal storage location 1350 carries negative or neutral charge in volatile memory, floating gate layer 60 can cover operation At the end of positively charged.Electric charge/the state of floating gate 60 then depends on the state of buoyancy aid with the relation of non-algorithm, and multiple unit Cover with parallel way occur, therefore cover speed of operation and be exceedingly fast.

Figure 200 A-200C describes the recovery operation when unit 1350 recovers power supply.Existence can be floated by recovery operation Unit 1350 state on grid 60, returns in floater area 24.Before performing recovery operation, buoyancy aid 24 is set to neutral state, i.e. Memory subassembly 1350 removes buoyancy aid state during power supply.In order to perform recovery operation, apply following bias condition: a positive electricity Pressure acts in SL terminal 72, zero or positive voltage act in BW terminal 76, no-voltage acts in substrate terminal 78, and BL is eventually End 74 then floats.

In a specific unrestricted embodiment, the voltage of about 3.0 volts acts in source electrode line terminal 72, about The voltage of 0.0 volt or+1.2 volts acts in BW terminal 76, and the voltage of about 0.0 volt acts in substrate terminal 78, and Bitline terminal 74 then floats.From the point of view of design alternative angle, these magnitudes of voltage are only demonstration use, can be because the change of embodiment is sent out Changing.Such as, a positive voltage may act on any electric current when avoiding recovery operation on bitline terminal 74 and flows through unit The channel region of 1350.Therefore, described one exemplary embodiment, feature, bias value etc. are construed as limiting in no instance.

Figure 200 B is the cross-sectional view of unit 1350 in recovery process when floating gate 60 electronegative property.On floating gate 60 Negative charge and SL terminal 72 on positive voltage, between source electrode line district 18 and the floater area 24 near floating gate 60 produce one Powerful electric field, and this makes it possible to band and the most significantly bends near door and source electrode line node overlapping area, cause electronics from Valance band is tunnelled to conduction band, is stayed in hole in valance band.Tunneling through the electronics of band drain leakage can be become, and hole It is injected into floater area 24 and becomes the hole charge of generation logical value-1 state.In this area, this process is referred to as interband tunnel Channel effect, or gate-induced drain leakage (GIDL) mechanism, such as at above-mentioned Yoshida (particularly Fig. 2 and 6 of page 3 and page 4 Fig. 9) in have explaination.BL terminal 74 is floated or positive voltage effect avoids electric current to flow through the channel region of unit 1350 on it, no Words then, then can cause the ionization by collision of all unit 1350.

Figure 200 C is the cross-sectional view of unit 1350 in recovery process when floating gate 60 is positively charged.Floating gate 60 and position Positive charge in line district 16 will not produce powerful electric field, orders about hole and is injected in buoyancy aid 24.Therefore, buoyancy aid 24 can be maintained at Neutral state.

After recovering internal storage location 1350, floating gate 60 resets to default conditions, such as positive status so that each floating gate 60 have a known state before performing another and covering operation.Reset by using interband tunneled holes to be injected into floating gate 60 Principle operate, see Figure 20 1.

In a specific unrestricted embodiment, the voltage of about 3.0 volts acts in source electrode line terminal 72, about The voltage of 0.0 volt or+1.2 volts acts in BW terminal 76, and the voltage of about 0.0 volt acts in substrate terminal 78, and Bitline terminal 74 then floats.From the point of view of design alternative angle, these magnitudes of voltage are only demonstration use, can be because the change of embodiment is sent out Changing.Therefore, described one exemplary embodiment, feature, bias value etc. are construed as limiting in no instance.Bias condition Bias condition with recovery operation.While it is true, owing to injecting the number of cavities in floating gate 60, ratio is injected in buoyancy aid 24 it Number of cavities to be lacked, and the operation that resets is slower than recovery operation.Negative voltage may also act on and buries in well terminal 76, to ensure not having hole It is accumulated in the internal storage location 1350 of positively charged floating gate 60, and positive voltage may also act on and stops electricity on bitline terminal 74 Stream flows through the channel region of unit 1350.

Figure 20 2 is the cross-sectional view of the internal storage location 1450 according to another embodiment of the present invention.Internal storage location 1450 includes Substrate 112 such as the first conductivity type such as p-type conductivity types.Substrate 112 is made by silicon is special, but also can be by such as The semi-conducting material composition that germanium, germanium silicon, GaAs, CNT etc. are known in the art.In some embodiments of the invention, substrate 112 can be the bulk material of semiconductor chip.In terms of design alternative angle, in other embodiments, substrate 112 can be to be embedded into Two kinds of conductivity type wells, or such as the first conductivity type well (figure of the second conductivity type semiconductor chip bulks such as N-shaped There is not embodiment).Describing for convenience, it is quasiconductor bulk material that substrate 112 generally charts, as shown in diagram 202.

Substrate 112 comprises the buried layer 122 of the second conductivity type such as N-shaped.Buried layer 122 can pass through ion implanting Technique is formed in substrate 112 material.Or, buried layer 122 also can epitaxial growth on substrate 112 top.

The floater area 124 of the first conductivity type such as p-type, is by bitline regions 116, source electrode line district 118 and absolutely up Edge layer 162 and 166 is surrounded, and side is surrounded by insulating barrier 126, and bottom is surrounded by buried layer 122.When injecting buried layer 122, floating Body 124 can be a part for former substrate 112 above buried layer 122.Or, buoyancy aid 124 can epitaxial growth.From design alternative angle Seeing, according to buried layer 122 and the generation type of buoyancy aid 124, buoyancy aid 124 can have in some embodiments, as substrate 112 it The different doping of requirement in doping or other embodiments.

Insulating barrier 126 (as such as shallow trench isolation (STI)) material is the material of silicon dioxide etc, although also can use Other insulant.When forming a memory subassembly during multiple unit 1450 are integrated into an array 1480, insulating barrier 126 Unit 1450 can be isolated with adjacent unit 1450.Buried region 122 is can be located at internal, it is allowed to buried region 122 bottom insulating barrier 126 Continuously, as shown in Figure 20 2A.Or, can be located at bottom, buried region 122 bottom insulating barrier 126, as shown in Figure 20 2B.This requirement More shallow insulating barrier 128, keeps apart floater area 124, but allows buried layer 122 at the cross section Vertical Square shown in Figure 20 2B On position continuously.For simplicity, the internal storage location 1450 of the most continuous buried region 122 can be opened up since then Show.

There is the bitline regions 116 of the second conductivity type such as n-type, be present in floater area 124 and be exposed to surface 114.According to any known and injection technology of art Special use, bitline regions 116 is formed at by injection technology Constitute above the material of substrate 112.Or, form bitline regions 116 by solid state diffusion process.

There is the source electrode line district 118 of the second conductivity type such as n-type, be present in floater area 124 and be exposed to surface 114.According to any known and injection technology of art Special use, source electrode line district 118 is formed by injection technology On the material constituting substrate 112.Or, form source electrode line district 118 by solid state diffusion process.

Internal storage location 1450 be asymmetric it, be the region more than bitline regions 116, the region in source electrode line district 118.Contrast When region, source electrode line district 118 and bitline regions 116 are about the same, bigger source electrode line district 118 is in source electrode line district 118 and floating Higher coupling is created between moving grid 160.

Floating gate 160 is between source electrode line district 118 and clearance for insulation district 168, and is positioned at above floater area 124.Float Floater area 124 is kept apart by grid 160 by insulating barrier 162.Insulating barrier 162 material can be silicon dioxide and/or other dielectrics Material, including high-k dielectric material etc., but is not limited only to, peroxidating tantalum, titanium oxide, zirconium oxide, hafnium oxide and/or aluminium oxide.Floating Moving grid 160 can be by, and such as polycrystalline silicon material or metal gate electrode, as tungsten, tantalum, titanium and its nitride are made.

One selection grid 164 is between bitline regions 116 and clearance for insulation district 168, and is positioned at above floater area 124.Choosing Select grid 164 to be kept apart by floater area 124 by insulating barrier 162.Insulating barrier 162 material can be silicon dioxide and/or other Jie Electric material, including high-k dielectric material etc., but is not limited only to, peroxidating tantalum, titanium oxide, zirconium oxide, hafnium oxide and/or aluminium oxide. Selecting the grid 164 can be by, such as polycrystalline silicon material or metal gate electrode, as tungsten, tantalum, titanium and its nitride are made.

Unit 1450 is another example of single polysilicon floating gate internal storage location because except logic transistor grid it Outside shaping, select grid 164 and floating gate 160 all can shape in the single polysilicon deposition process of assembling stage.Gap 168 it Formation needs extra process step because gap size than lithography tool can process little more than.

Unit 1450 includes multiple terminal: is connected electrically to select grid 164 zigzag (WL) terminal 170, is connected electrically to Bit line (BL) terminal 174 of bitline regions 116, is connected electrically to source electrode line (SL) terminal 172 in source electrode line district 118, electrical connection Buried layer 122 bury well (BW) terminal 176, and be connected electrically to the substrate terminal 178 of substrate 112.Floating gate 160 is without electrically Connect.Therefore, floating gate 160 floats and uses as nonvolatile memory district.

Figure 20 3 is the equivalent circuit representation of internal storage location 1450.Internal storage location 1450 includes and MOS transistor 120b Metal-oxide semiconductor (MOS) (MOS) the transistor 120a of series connection, by bitline regions 116, floating gate 160, source electrode line district 118 and buoyancy aid District 124 is constituted, and selects grid 164 and floating gate 160 then to control the channel region of respective grid lower unit 1450.Internal storage location 1450 In also include dipole elements 130a and 130b, respectively by burying wellblock 122, floater area 124 and bitline regions 116 or source electrode line district 118 Constitute.

Figure 20 4 describes the internal storage location 1450 of a ranks arrangement, and (four exemplary memory unit 1450 are expressed as 1450a, 1450b, 1450c and 1450d) exemplary memory array 1480.Occur a lot in exemplary array 1480, but not Must be in all figures, when described operation have one (or multiple, selected internal storage location in certain embodiments) When 1450, representative internal storage location 1450a is the representative of a selected memory unit 1450.In these figures, have The internal storage location 1450b of representativeness is one and selected representative internal storage location 1450a, shares the unselected internal storage location of colleague The representative of 1450, representative internal storage location 1450c is one and selected representative internal storage location 1450a, shares same column The representative of unselected internal storage location 1450, and representative internal storage location 1450d, be one with selected representative internal memory Unit 1450a do not share ranks it, the representative of unselected internal storage location 1450.

Figure 20 4 has wordline 172a to 172n, source electrode line 172a to 172n, bit line 174a to 174p, buries well terminal 176a To 176n and substrate terminal 178.Each wordline in 172a to 172n and the every source line in 172a to 172n with in single file Memory cell 1450 is relevant, and is respectively coupled in selection grid 164 and the source electrode line district 118 of each internal storage location of this row 1450. Each bit line in 174a to 174p is relevant with single-row internal memory 1450, and is coupled to the bitline regions of each internal storage location of these row 1450 On 116.

In array 1480, all there is substrate 112 all positions.Consider from design alternative angle, ordinary skill people Member should notify, and one or more substrate terminal 178 are present in one or more position.These technicians also should notify, when showing Plasticity array 1480 occurs with single continuous array in Figure 20 4, then a lot of other tissues and layout are exactly possibility.Example As divisible in, wordline or buffering, bit line is divisible or buffering, and source electrode line is divisible or buffering, array 1480 be divided into two with Upper subnumber group and/or control circuit, such as word decoder, column decoder, segmentation device, sense amplifier, write amplifier Can be arranged in around exemplary array 1480 or insert array 1480 subnumber group middle.Therefore, the exemplary reality in the present invention Execute example, feature, design option etc. to be construed as limiting in no instance.

The operation of memory subassembly 1450 is with the mode of operation of the memory subassembly 1350 shown in Figure 187.In event 102, When memory subassembly is energized first, memory subassembly is in original state, and wherein the Nonvolatile memory part of this assembly is set to One predetermined state.In event 104, memory subassembly 1450 runs under volatibility operator scheme, wherein the shape of unit 1450 State is stored in buoyancy aid 124.When power-off or have a power failure suddenly, or other event terminations any or interference, memory subassembly of the present invention 1450 power supply time, the content of volatile memory " is covered " to event 106 purgation not volatibility memory part.Performing backup behaviour Also can cover during work, when volatibility operated for 104 stage and/or user manually indicates any time of backup regular Carry out.At this moment, memory subassembly keeps there are the data in not volatile ram.When event recovers power supply 108 times, not volatibility Content in internal memory, is recovered, followed by by the mode that the content in not volatile ram is transferred to volatile ram Reset for event 110 purgation memory subassembly.

In one embodiment, volatile ram (such as floating gate 160) is not initialised to positive charge, in event In 102.When unit 1450 is energized, unit 1450 stores memory information (being i.e. saved in the data in internal memory), as internal memory Electric charge in assembly 1450 buoyancy aid 124.Electric charge regulation in buoyancy aid 124 flows through the electric current of memory subassembly 1450 (from BL terminal 174 To SL terminal 172).The electric current flowing through memory subassembly 1450 may be used to determine the state of unit 1450.Because not volatile storage Element (such as floating gate 160) is initialized to carry a positive charge, thus any cell current difference be buoyancy aid 124 charge difference it Result.

Under easy disabling mode, internal storage location 1450 can be performed multi-mode operation: preserve, read, write logical value-1 and write Logical value-0 operates.

Figure 20 5 describes the holding operation of memory array 1480, and this array is made up of multiple internal storage locations 1450.By Apply forward feedback bias in BW terminal 176, execute in WL terminal 170, SL terminal 172, BL terminal 174 and substrate terminal 178 Add zero-bias, perform holding operation.Connect BW terminal and be applied to buried layer district forward feedback bias it will be kept to be connected Connect the state of internal storage location 1450.

From the point of view of the equivalent circuit representation of the internal storage location 1450 shown in Figure 20 3, internal storage location 1450 includes that n-p-n is double Pole assembly 130a and 130b, respectively by burying wellblock 122 (collector region), buoyancy aid 124 (base region) and bitline regions 116 or source electrode line district 118 (emitter region) forms.

The holding operating principle of unit 1450 is with the operating principle of unit 1350.When buoyancy aid 124 is positively charged, one right Answering the state of logical value-1, bipolar transistor 130a and 130b can be opened, and the positive charge in floater area reduces base stage The electron stream energy barrier in district.Once injecting floater area 124, act in positive bias and bury wellblock 122 times, electrons is swept into burying Wellblock 122 (being connected to BW terminal 176).Due to positive bias, by ionization by collision mechanism, electronics accelerate and produce one extra it Heat carrier (hot hole and thermoelectron to).Thus the thermoelectron of generation flows into BW terminal 176, and the hot hole of generation simultaneously is the most therewith Flow into floater area 124.This process has recovered the electric charge on floater area 124, and remains stored in the electric charge in floater area 124, Thus burying on wellblock 122 by BW terminal 176, apply to keep at n-p-n bipolar transistor 130a and 130b during positive bias In opening.

When buoyancy aid 124 band neutral charge (voltage of buoyancy aid 124 and the voltage on ground connection bitline regions 116 or source electrode line district 118 Identical), the state of a counterlogic value-0, do not have electric current can flow through n-p-n transistor 130a and 130b.Dipole elements 130a Remaining off with 130b, will not collide ionization.Subsequently, logical value-0 state purgation internal storage location is maintained at logic Value-0 state.

In holding operation described in 205, the most not selected internal storage location.On the contrary, unit is buried well terminal 176a Embark on journey to 176n selected, can be independent rows, multirow or all row selection constituting array 1480.

In one embodiment, the bias condition of the holding operation of internal storage location 1450 is: the voltage of 0 volt acts on WL In terminal 170, SL terminal 172, BL terminal 174 and substrate terminal 178, as the positive voltages of+1.2 volts act on BW terminal 176 On.In other embodiments, different voltages may act on the different terminals of internal storage location 1450, examines from design alternative angle Considering, therefore, described exemplary voltage is not intended that restriction.

Figure 20 6 describes the read operation of execution on selected internal storage location 1450a.Read operation can by apply with Lower bias condition performs: a positive voltage acts in selected WL terminal 170a, and a positive voltage acts on selected BL eventually On end 174a, no-voltage acts in SL terminal 172, and a positive voltage acts in BW terminal 176, and no-voltage acts on lining In end terminal 178.

In an exemplary embodiment, the voltage of about+1.2 volts acts in selected WL terminal 170a, about 0.0 volt The voltage of spy acts in selected SL terminal 172a, and the voltage of about+0.4 volt acts on selected bitline terminal 174a, The voltage of about+1.2 volts acts on and selected buries well terminal 176, and the voltage of about 0.0 volt acts in substrate terminal 178.Institute Having the voltage that unselected zigzag terminal 170b to 170n is applied with 0.0 volt, bitline terminal 174b to 174p is applied with 0.0 volt The voltage of spy, unselected SL terminal 172b to 172p is applied with voltage or the floating of 0.0 volt, and unselected BW terminal 176b to 176p the voltage of ground connection or applying+1.2 volts can maintain the state of unselected cells 1450, the electricity of about 0.0 volt Pressure acts in substrate terminal 178.Figure 20 6 gives in selected representative internal storage location 1450a and memory array 1,480 three The bias condition of unselected representative internal storage location 1450b, 1450c and 1450d, each possesses the bias condition of uniqueness. One of ordinary skill in the art should notify, and the other embodiments of the present invention can use from design alternative angle and be biased it Other combination.These technicians simultaneously it should also be appreciated that in other embodiments first and second kinds of conductivity type can enter Row exchanges, and relative bias can be changed.

When the floater area 124 of elected cell 1450a is positively charged (unit 1450a is in logical value-1 state), that The threshold voltage of MOS transistor 120a and 120b of selected unit 1450a can relatively low (contrasting floater area 124 be the feelings of neutrality Under condition), and a larger current can flow to select the source electrode line district 118 of unit 1450a from bitline regions 116.Due to floating gate 160 is positively charged when volatile operation, then unit electricity measured between logical value-0 and logical value-1 state lower unit It is poor to flow, and is because the potential difference of buoyancy aid 124 and causes it.

For share the internal storage location of colleague with selected internal storage location (such as unit 1450b), BL and SL terminal Ground connection, does not has electric current to flow through.These unit can be in holding pattern, and with the positive voltage acted in BW terminal 176.

For share the internal storage location of same column with selected internal storage location (such as unit 1450c), act on unselected Determine the no-voltage in WL terminal and can cut off the MOS transistor 120a of these unit, thus cause not having electric current to flow through.Due to BW eventually Less difference between end 176 and BL terminals 174, a less holding electric current can flow through these unit.While it is true, due to Charge life (in terms of millisecond magnitude) in write operation (in terms of nanosecond order) relatively buoyancy aid 124 complete faster, therefore it The electric charge in buoyancy aid should be interrupted hardly.

For do not share the internal storage location of colleague or same column with selected internal storage location (such as unit 1450d), WL, BL and SL terminal ground connection.These unit can be in holding pattern, and state logic value-1 purgation internal storage location, electric charge can be kept In buoyancy aid 124, state logic value-0 purgation internal storage location then keeps neutral state.

Write logical value-0 operation of one independent memory unit 1450, is shown in the introduction of Figure 20 7A to 207C.At Figure 20 7A In, back bias voltage acts on (i.e. 172a in Figure 20 7A) in SL terminal 172, and no-voltage acts on WL terminal 170 and BL terminal 174 On, zero or positive voltage act in selected BW terminal 176, no-voltage acts in substrate terminal 178.Under these conditions, Any p-n junction between buoyancy aid 124 and the source electrode line district 118 of selected unit 1450 is positive bias, any from buoyancy aid 124 of emptying Hole.Because SL terminal 172 is shared by multiple internal storage locations 1450, logical value-0 can be written into internal storage location 1450 In, wherein internal storage location 1450a and 1450b shares same SL terminal 172a simultaneously.

In a specific unrestricted embodiment, the voltage of about-1.2 volts acts in source electrode line terminal 172, about The voltage of 0.0 volt acts on word line terminal 170 and bitline terminal 174, and the voltage of about 0.0 volt or+1.2 volts acts on In BW terminal 176, the voltage of about 0.0 volt acts in substrate terminal 178.From the point of view of design alternative angle, these magnitudes of voltage Only for demonstration use, can be because the change of embodiment changes.Therefore, the one exemplary embodiment in the present invention, feature, bias value Deng being construed as limiting in no instance.

In Figure 20 7B, back bias voltage acts on (i.e. 174a in Figure 20 7B) in BL terminal 174, and zero-bias acts on WL eventually End 170 and SL terminals 172 on, zero or positive voltage act in selected BW terminal 176, no-voltage acts on substrate terminal 178 On.Under these conditions, any p-n junction between buoyancy aid 124 and the bitline regions 116 of selected unit 1450 is positive bias, and emptying is certainly Any hole of buoyancy aid 124.Because BL terminal 174 is shared by multiple internal storage locations 1450, so logical value-0 can be write Entering in internal storage location 1450, wherein internal storage location 1450a and 1450c shares same BL terminal 174a simultaneously.

In a specific unrestricted embodiment, the voltage of about-1.2 volts acts on bitline terminal 174, about The voltage of 0.0 volt acts in word line terminal 170 and source electrode line terminal 172, about 0.0 volt or the voltage effect of+1.2 volts In BW terminal 176, the voltage of about 0.0 volt acts in substrate terminal 178.From the point of view of design alternative angle, these voltages Value is only demonstration use, can be because the change of embodiment changes.Therefore, the one exemplary embodiment in the present invention, feature, bias Values etc. are construed as limiting in no instance.

All there is one defect in the operation of above-mentioned write logical value-0: and shared same SL terminal 172 (the first type-OK Write logical value-0) or all internal storage locations 1450 meeting of same BL terminal 174 (the second type-row write logical value-0) It is synchronously written, thus causes logical value-0 being write in independent memory unit 1450.In order to by any binary data write In the internal storage location 1450 of difference, all internal storage locations to be written perform write logical value-0 operation first, then One or more write logical values-1 operation upper for must be written into logical value-1.

The third allows write logical value-0 operation of independent bits write to see that Figure 20 7C illustrates and passes through to execute in WL terminal 170 Add positive voltage, apply negative voltage in BL terminal 174, apply no-voltage in SL terminal 172, apply zero or positive electricity in BW terminal 176 Pressure and substrate terminal 178 apply the mode of no-voltage and realize.Under these conditions, buoyancy aid 124 voltage is by selected WL terminal 170 Capacitance Coupled applying positive voltage are increased.Owing to the voltage of buoyancy aid 124 increases and is applied in BL terminal 174 it Negative voltage, any p-n junction between buoyancy aid 124 and bitline regions 116 is positive bias, the emptying any hole from buoyancy aid 124.

For reducing in memory array 1480, the unnecessary logical value-0 of writing being brought other internal storage locations 1450 bothers, The voltage acted on can optimize as follows: when buoyancy aid 124 voltmeter of state logic value-1 is shown as V_FB1, then act on selected WL It is V that the voltage of terminal 170 is configurable to increase the voltage of buoyancy aid 124_FB1/ 2, and-V_FB1/ 2 act in BL terminal 174. It addition, ground connection or more weak positive voltage, it is possible to act on and do not share the unselected of same BL terminal 174 with selected memory unit 1450 In the BL terminal 174 of internal storage location 1450, and negative voltage, it is possible to act on and do not share same WL with selected memory unit 1450 eventually In the WL terminal 170 of the unselected internal storage location 1450 of end 170.

Shown in Figure 20 7C, following bias condition act in exemplary memory array 1480 selected representative within Memory cell 1450a, performs only just have logical value-0 of independently writing to operate in representative internal storage location 1450a: about 0.0 volt The voltage of spy acts in SL terminal 172a, and the voltage of about-0.2 volt acts in BL terminal 174a, the electricity of about+1.2 volts Pressure acts on word line terminal 170a, and the voltage of about+1.2 volts acts on and buries in well terminal 176a, and the voltage of about 0.0 volt is made For substrate terminal 278a.When resetting array 1580, the voltage of about 0.0 volt acts on unselected WL terminal (including WL terminal 170b and 170n), the voltage (or the strongest positive voltage) of about 0.0 volt acts on unselected BL terminal (including BL terminal 174b and 174p) on 174, the voltage of about 0.0 volt acts on and (includes that SL is eventually in unselected SL terminal 172 End 172b and 172n), the voltage of about+1.2 volts act in unselected BW terminal 176 (include BW terminal 176b and 176n).One of ordinary skill in the art should notify, the magnitude of voltage in Figure 20 7C only for explaination mesh it, and different implement Example considers to have the magnitude of voltage of difference from design alternative angle.

. one write logical value-1 operation, can by be all hereby incorporated by reference it " one has reinforcement buoyancy aid The novel 1T DRAM cell of effect ", Lin and Chang, 23-27 page, nineteen ninety-five IEEE memory techniques, design and test the world and grind Beg in meeting (hereinafter referred " Lin "), or by the interband tunneling of the most above-mentioned Yoshida, (alternatively referred to as gate-induced drain is let out Leakage or GIDL) described ionization by collision carries out on internal storage location 1450.In conjunction with Figure 20 8A to using a certain of GIDL method to write Enter logical value-1 example of operation to be described, and combine Figure 20 8B, to use ionization by collision method a certain write logical value- 1 example of operation is described.

In Figure 20 8A, describe one during interband tunnel write logical value-1 operation, comprise selected representative in The bias condition example of the array 1480 of memory cell 1450a.The back bias voltage being applied in WL terminal 170a and be applied to BL terminal The positive bias that 174a is upper so that hole is injected in the buoyancy aid 124 of selected representative internal storage location 1450a.SL terminal 172a and Substrate terminal 178 is ground connection during write logical value-1 operation, and a positive bias acts on and maintains not in BW terminal 176a The holding operation of selected unit.

Negative voltage in WL terminal has coupled downwards the voltage of the floater area 124 in representative internal storage location 1450a.In choosing In fixed representative internal storage location 1450a, (it is thus it " grid cause " portion of GIDL in conjunction with the positive voltage in BL terminal 174a at door 160 Point) near bitline regions 116 and floater area 124 between create a highfield.And this makes it possible to band in door and drain junction The most significantly bend near overlapping area, cause electronics to be tunnelled to conduction band from valance band, hole is stayed in valance band.Wear Tunnel is through the electronics of band becoming drain leakage (being thus it " drain current " part of GIDL), and hole is injected into buoyancy aid District 124 also becomes the hole charge of generation logical value-1 state.This process is the most famous in this area, at above-mentioned Yoshida (particularly Fig. 2 and 6 and Fig. 9 of page 4 of page 3) there is explaination.

In a specific unrestricted embodiment, the voltage of about-1.2 volts acts on word line terminal 170a, about+ The voltage of 1.2 volts acts on bitline terminal 174a, and the voltage of about 0.0 volt acts in source electrode line terminal 172a, and about 0.0 Volt or the voltage of+1.2 volts act in BW terminal 176, and the voltage of about 0.0 volt acts in substrate terminal 178, and position Line terminal 74 is then floated.From the point of view of design alternative angle, these magnitudes of voltage are only demonstration use, can be because the change of embodiment occurs Change.Therefore, described one exemplary embodiment, feature, bias value etc. are construed as limiting in no instance.

Figure 20 8B describes write logical value-1 operation using ionization by collision method.In this case, to be written it The door 160 of internal storage location 1450 and bit line 116 bias under positive voltage so that buoyancy aid 124 is charged to patrol by ionization by collision flowing Collect value-1 state, regardless of the data being originally stored in unit.

In one exemplary embodiment shown in Figure 20 8B, selected zigzag terminal 170a biases when+1.2 volts, and unselected Determine zigzag terminal 170b to 170n then to bias when 0.0 volt；Selected bitline terminal 174a also biases when+1.2 volts, And unselected bitline terminal 174b to 174p biases when 0.0 volt, selected source electrode line 172a biases when 0.0 volt, Burying well terminal 176 to bias when 0.0 or+1.2 volts (maintaining the state of unselected cells), substrate terminal 178 is then 0.0 Bias during volt.These bias values only for demonstration mesh it, can according to embodiment change and change, the most in no instance It is construed as limiting.

The following bias condition performing to cover operation is described by Figure 20 9: a positive voltage acts on selected SL In terminal 172, a positive voltage acts in selected WL terminal 170, and no-voltage acts in selected BL terminal 174, and zero Or positive voltage acts in BW terminal 176, and no-voltage acts in substrate terminal 178.

In a specific unrestricted embodiment, the voltage of about 6.0 volts acts in source electrode line terminal 172, about+ The voltage of 1.2 volts acts in WL terminal 170, and the voltage of about 0.0 volt acts on bitline terminal 174, about 0.0 volt or The voltage of+1.2 volts acts in BW terminal 176, and the voltage of about 0.0 volt acts in substrate terminal 178.From design alternative From the point of view of angle, these magnitudes of voltage are only demonstration use, can be because the change of embodiment change.Therefore, the demonstration in the present invention Property embodiment, feature, bias value etc. are construed as limiting in no instance.

The sectional view of internal storage location when buoyancy aid 124 is positively charged when Figure 21 0A is for covering operation.When buoyancy aid 124 positively charged During lotus/voltage, MOS assembly 120a opens.MOS assembly 120a purgation surface voltage, equal to act in BL terminal 174 voltage and Act on the voltage in WL terminal 170 and the small voltage in pressure reduction between MOS assembly 120a upper threshold voltage.And it is applied to source Positive voltage (through SL terminal 172) on polar curve 118 can be capacitively coupled on floating gate 160.Therefore, MOS assembly 120b purgation Surface voltage can increase, and according to the positive charge in floating gate 160, can be close to the voltage being applied in source electrode line district 118. Then, a powerful transverse electric field can produce around interstitial area 168.This transverse electric field can encourage/promote electronics from bit line District 116 flows to source electrode line district 118 (MOS assembly 120a and 120b opens simultaneously), jumps into buoyancy aid 124 again and float when reaching enough Stop oxide layer between grid 160.And potential difference between floating gate 160 (in part because source electrode line district 118 and surface 114 Coupling), and therefore the big longitudinal electric field of one of generation can produce.So electronics just can enter floating gate 160 (see in Figure 21 0A Shown in arrow indication floating gate 160).Correspondingly, (the buoyancy aid when the volatile memory of unit 1450 is in logical value-1 state 124 is positively charged), floating gate 160 is electronegative by the method for covering, as shown in Figure 21 0A.

Figure 21 0B is when buoyancy aid 124 is for neutrality, the cross-sectional view of unit 1450 in masking process.In buoyancy aid 124 is During property, the threshold voltage of MOS assembly 120a higher (compare buoyancy aid 124 positively charged time threshold voltage), and MOS assembly 120a It is closed.Therefore, electrons is not had to flow through unit 1450.Correspondingly, it is in logical value-0 when the volatile memory of unit 1450 During state (when buoyancy aid 124 is neutral), floating gate 160 keeps positive charge at the end of covering operation, as shown in Figure 21 0B.

Covering after operation terminates, the state of charge of floating gate 160 is complementary with the state of charge of buoyancy aid 124.Therefore, if When the buoyancy aid 124 of internal storage location 1450 is positively charged in volatile memory, floating gate 160 is electronegative by meeting after covering operation Lotus, and when the buoyancy aid 124 of internal storage location 1450 carries negative or neutral charge in volatile memory, floating gate layer 160 can hide At the end of covering operation positively charged.Electric charge/the state of floating gate 160 then depends on the state of buoyancy aid with the relation of non-algorithm, and Covering of multiple unit occurs with parallel way, therefore covers speed of operation and is exceedingly fast.

Figure 21 1 describes the recovery operation when unit 1450 recovers power supply.Recovery operation can will exist on floating gate 160 Unit 1450 state, return in floater area 124.Before performing recovery operation, buoyancy aid 124 is set to neutral state, i.e. internal memory Assembly 1450 removes buoyancy aid state during power supply.In order to perform recovery operation, apply following bias condition: a positive voltage is made For SL terminal 172, no-voltage acts in WL terminal 170 and BL terminal 174, zero or positive voltage act on BW terminal 176 On, no-voltage acts in substrate terminal 178.

In a specific unrestricted embodiment, the voltage of about+1.2 volts acts in source electrode line terminal 172, about The voltage of 0.0 volt acts on word line terminal 170 and bitline terminal 174, and the voltage of about 0.0 volt or+1.2 volts acts on In BW terminal 176, the voltage of about 0.0 volt acts in substrate terminal 178.From the point of view of design alternative angle, these magnitudes of voltage Only for demonstration use, can be because the change of embodiment changes.Such as, positive voltage may act on bitline terminal 174 or One negative voltage acts on no current when ensureing recovery operation in wordline 170 and flows through the channel region of unit 1450.Therefore, described One exemplary embodiment, feature, bias value etc. be construed as limiting in no instance.

Figure 21 2A is the cross-sectional view of unit 1450 in recovery process when floating gate 160 electronegative property.Floating gate 160 Between the positive voltage on upper negative charge and SL terminal 172 source electrode line district 118 and floater area 124 near floating gate 160, produce A raw powerful electric field, and this makes it possible to band and the most significantly bends near door and source electrode line node overlapping area, causes Electronics is tunnelled to conduction band from valance band, is stayed in hole in valance band.It is tunneling through the electronics of band drain leakage can be become, And hole is injected into floater area 124 and becomes the hole charge of generation logical value-1 state.In this area, this process is claimed For band-to-band tunnelling, or gate-induced drain leakage (GIDL) mechanism, such as at above-mentioned Yoshida (particularly Fig. 2 and 6 of page 3 Fig. 9 with page 4) in have explaination.BL terminal 174 ground connection or positive voltage effect avoid electric current to flow through the ditch of unit 1450 on it Road district.

Figure 21 2B is when floating gate 160 is positively charged in recovery process, the cross-sectional view of unit 1450.Floating gate 160 Powerful electric field will not be produced with the positive charge in source electrode line district 118, order about hole and be injected in buoyancy aid 124.Therefore, buoyancy aid 124 can be maintained at neutral state.

It can be seen that when floating gate 160 perform cover after positively charged, the volatile ram of buoyancy aid 124 can return to Band neutral charge (logical value-0 state), but when floating gate 160 is electronegative, the volatile ram of buoyancy aid 124 can return to Positively charged (logical value-1 state), thus before covering operation, return to the initial condition of buoyancy aid 124.Note: this process with Non-calculation mode occurs, because floating gate 160 state determines the shape of buoyancy aid 124 recovery without carrying out reading, understand or measure State.On the contrary, recovery process occurs automatically, potential difference drive.Correspondingly, this process is the order of magnitude, and ratio requires that algorithm is got involved Speed faster.

After recovering internal storage location 1450, floating gate 160 resets to default conditions, such as introduce it in Figure 21 3A and 213B Positive status so that each floating gate 160 has a known state before performing another and covering operation.Reset by using interband Tunneled holes is injected into the principle of floating gate 160 and operates, as shown in Figure 21 3A, or by 160 beginnings of self-relocation grid Electron tunneling, as shown in Figure 21 3B.

Reset in Figure 21 3A uses the principle similar with recovery operation.Electronegative floating gate 160 can produce one Generate the electric field of hot hole.Most of hot holes of generation are injected in buoyancy aid 124, and smaller portions are injected into floating gate 160 In.One higher voltage may act on and increases the speed that the operation that resets is desired in SL terminal 172.Hole is injected and is only occurred In the unit 1450 of electronegative floating gate 160.Therefore, before reset operation terminates, all floating gates 160 are initialized to Positively charged.

In a specific unrestricted embodiment (see Figure 21 3A), the voltage of about+3.0 volts acts on source electrode line eventually End 172 on, the voltage of about 0.0 volt acts on word line terminal 170 and bitline terminal 174, about 0.0 volt or+1.2 volts it Voltage acts in BW terminal 176, and the voltage of about 0.0 volt acts in substrate terminal 178.From the point of view of design alternative angle, These magnitudes of voltage are only demonstration use, can be because the change of embodiment change.Therefore, described one exemplary embodiment, feature, Bias values etc. are construed as limiting in no instance.Bias condition is with the bias condition of recovery operation.While it is true, due to note Entering the number of cavities in floating gate 160 fewer than the number of cavities being injected in buoyancy aid 124, the operation that resets is slower than recovery operation. Negative voltage may also act on and buries in well terminal 176, to ensure the not having hole accumulation internal storage location at positively charged floating gate 160 In 1450, and positive voltage may also act on bitline terminal 174, to stop electric current to flow through the channel region of unit 1450.

Figure 21 3B is tunneling to select the mode of grid 164 to describe reset operation from floating gate 160 by electronics.One positive electricity Pressure acts in WL terminal 170, and no-voltage acts in BL terminal 174 and SL terminal 172, and no-voltage or positive voltage can act on In BW terminal 176, no-voltage acts in substrate terminal 178.It is applied to select the positive voltage on grid 164 (by WL terminal 170) highfield can be produced through selecting grid 164 and floating gate 160 so that electronics is tunneling to select grid 164 from floating gate 160.

In a specific unrestricted embodiment (see Figure 21 3B), the voltage of about+12.0 volts acts on WL terminal On 170, the voltage of about 0.0 volt acts in BL terminal 174, SL terminal 172 and substrate terminal 178, about 0.0 volt or+1.2 The voltage of volt acts in BW terminal 176.From the point of view of design alternative angle, these magnitudes of voltage are only demonstration use, can be because in fact The change executing example changes.Therefore, described one exemplary embodiment, feature, bias value etc. are constituted in no instance Limit.

Figure 21 4 is another embodiment of internal storage location 1450.Wherein, grid 164 and floating gate 160 is selected to have overlapping (part Or all), and this may produce, a short channel length of such as MOS assembly 120a, can increase in turn flow through unit 1450 it Electric current.Due to overlap, can in door forming process not by less geometry shape and etching in the case of obtain shorter Channel length, such as the processing step shown in Figure 197 M to 197O.

Figure 21 5A be another embodiment of internal storage location 1550 according to the present invention cross-sectional view, including a control gate 240.Internal storage location 1550 includes such as the substrate 212 of the first conductivity type such as p-type conductivity type.Substrate 212 is by silicon Special make, but also can be made up of semi-conducting materials such as such as germanium, germanium silicon, GaAs, CNTs.In the present invention, some are implemented In example, substrate 212 can be the bulk material of semiconductor chip.In terms of design alternative angle, in other embodiments, substrate 212 can For being embedded into the second conductivity type well or the first conductivity such as the second conductivity type semiconductor chip bulks such as N-shapeds Type well (figure does not has embodiment).Describing for convenience, it is quasiconductor bulk material that substrate 212 generally charts, as shown in Figure 21 5.

Substrate 212 comprises the buried layer 222 of the second conductivity type such as N-shaped.Buried layer 222 can pass through ion implanting Technique is formed in substrate 212 material.Or, buried layer 222 also can epitaxial growth on substrate 212 top.

The floater area 224 of the first conductivity type such as p-type, is by bitline regions 216, source electrode line district 218 and absolutely up Edge layer 262 and 266 is surrounded, and side is surrounded by insulating barrier 226, and bottom is surrounded by buried layer 222.When injecting buried layer 222, floating Body 224 can be a part for former substrate 212 above buried layer 222.Or, buoyancy aid 224 can epitaxial growth.Depend on buried layer 222 and the generation type of buoyancy aid 224, buoyancy aid 224 can have in some embodiments the doping as substrate 12 or other are implemented The different doping of requirement in example, in terms of design alternative angle.

Insulating barrier 226 (as such as shallow trench isolation (STI)) material is the material of silicon dioxide etc, although it can be used His insulant.When forming a memory subassembly during multiple unit 1550 are integrated into an array 1580, insulating barrier 226 meeting Unit 1550 is isolated with adjacent unit 1550.Buried region 222 is can be located at internal, it is allowed to buried region 222 is even bottom insulating barrier 226 Continuous, as shown in Figure 21 5A.Or, can be located at bottom, buried region 222 bottom insulating barrier 226, as shown in Figure 21 5B.This requires more Shallow insulating barrier 228, keeps apart floater area 224, but allows buried layer 222 in the cross section vertical orientations shown in Figure 21 5B Upper continuous.For simplicity, the internal storage location 1550 of the most continuous buried region 222 can be shown since then.

There is the bitline regions 216 of the second conductivity type such as n-type, be present in floater area 224 and be exposed to surface 214.According to any known and injection technology of art Special use, bitline regions 216 is formed at by injection technology Constitute above the material of substrate 212.Or, form bitline regions 216 by solid state diffusion process.

There is the source electrode line district 218 of the second conductivity type such as n-type, be present in floater area 224 and be exposed to surface 214.According to any known and injection technology of art Special use, source electrode line district 218 is formed by injection technology On the material constituting substrate 212.Or, form source electrode line district 218 by solid state diffusion process.

Different from internal storage location 1350 and 1450, internal storage location 1550 be not necessarily asymmetric it because floating gate 260 it Coupling can be obtained by control gate 240.

Floating gate 260 is between source electrode line district 218 and clearance for insulation district 268, and is positioned at above floater area 224.Float Floater area 224 is kept apart by grid 260 by insulating barrier 262.Insulating barrier 262 material can be silicon dioxide and/or other dielectrics Material, including high-k dielectric material etc., but is not limited only to, peroxidating tantalum, titanium oxide, zirconium oxide, hafnium oxide and/or aluminium oxide.Floating Moving grid 260 can be by, and such as polycrystalline silicon material or metal gate electrode, as tungsten, tantalum, titanium and its nitride are made.

One selection grid 264 is between bitline regions 216 and clearance for insulation district 268, and is positioned at above floater area 224.Choosing Select grid 264 to be kept apart by floater area 224 by insulating barrier 266.Insulating barrier 266 material can be silicon dioxide and/or other Jie Electric material, including high-k dielectric material etc., but is not limited only to, peroxidating tantalum, titanium oxide, zirconium oxide, hafnium oxide and/or aluminium oxide. Selecting the grid 264 can be by, such as polycrystalline silicon material or metal gate electrode, as tungsten, tantalum, titanium and its nitride are made.

Control gate 240 is positioned at above floating gate 260, and is kept apart by insulating barrier 242, words so, floating gate 260 Between surface 214 below insulating barrier 262 and floating gate 260, insulating barrier 242 and control gate 240 are then positioned at floating gate 260 Top, as shown.Control gate 240 will be capacitively coupled on floating gate 260.Control gate 240 is by polycrystalline silicon material or metal gate electricity Pole, as special in tungsten, tantalum, titanium and its nitride etc. makes.Relation between floating gate 260 and control gate 240, with not volatibility repeatedly Relation between grid floating gate/barrier layer internal storage location is similar to.Floating gate 260 is used to store not volatibility internal storage data, and Control gate 240 then selects for internal storage location.

Unit 1550 includes multiple terminal: is connected electrically to select grid 264 zigzag (WL) terminal 270, is connected electrically to Bit line (BL) terminal 274 of bitline regions 216, is connected electrically to source electrode line (SL) terminal 272 in source electrode line district 218, electrical connection To control gate (CG) terminal 280 of control gate 240, be electrically connected buried layer 222 buries well (BW) terminal 276, and electrically connects Receive the substrate terminal 278 of substrate 212.

Figure 21 6 is the equivalent circuit representation of internal storage location 1550.Internal storage location 1550 includes and MOS transistor 220b Metal-oxide semiconductor (MOS) (MOS) the transistor 220a of series connection, by bitline regions 216, selects grid 264, floating gate 260 and control gate 240, source electrode line district 218 and floater area 224 are constituted.Select grid 264 to control to select the channel region of grid lower unit 1550, and float Grid 260 and control gate 240 then control floating gate 260 channel region below.Internal storage location 1550 also includes dipole elements 230a And 230b, respectively by burying wellblock 222, floater area 224 and bitline regions 216 or source electrode line district 218 is constituted.Source to floating gate 260 Polar curve district 218 couples in (being extended to source electrode line district 218 via floating gate 260 show especially) Figure 21 6 embodiment, because unit 1550 may need, it is also possible to need not additionally be coupled in floating gate 260.In order to ensure that drawing is succinctly spent, floating gate 260 to The extension part in source electrode line district 218 is not drawn.

Figure 21 7 describes the internal storage location 1550 of a ranks arrangement, and (four exemplary memory unit 1550 are expressed as 1550a, 1550b, 1550c and 1550d) exemplary memory array 1580.Occur a lot in exemplary array 1580, but not Must be in all figures, when described operation have one (or multiple, selected internal storage location in certain embodiments) When 1550, the representative representative that internal storage location 1550a is a selected memory unit 1550.In these figures, have The internal storage location 1550b of representativeness is one and shares, with selected representative internal storage location 1550a, the unselected internal storage location gone together The representative of 1550, representative internal storage location 1550c be one with selected representative internal storage location 1550a share same column it The representative of unselected internal storage location 1550, and representative internal storage location 1550d be one with selected representative in deposit receipt Unit 1550a does not share the representative of the unselected internal storage location 1550 of ranks.

Figure 21 7 has wordline 270a to 270n, source electrode line 272a to 272n, bit line 274a to 274p, control gate terminal 280a to 280n, buries well terminal 276a to 276n and substrate terminal 278.Each word line terminal in 270a to 270n, 272a is extremely Every source line terminal in 272n and each control gate terminal in 280a to 280n, relevant with single file internal storage location 1550, And be respectively coupled on the selection grid 264 of each internal storage location of this row 1550, source electrode line district 218 and control gate 240.274a is extremely Each bit line in 274p is relevant with single-row internal memory 1550, and is coupled on the bitline regions 216 of each internal storage location of these row 1550.

In array 1580, all there is substrate 212 all positions.Consider from design alternative angle, ordinary skill people Member should notify, and one or more substrate terminal 278 are present in one or more position.These technicians also should notify, when showing Plasticity array 1580 occurs with single continuous array in Figure 21 7, then a lot of other tissues and layout are exactly possibility.Example As divisible in, wordline or buffering, bit line is divisible or buffering, and source electrode line is divisible or buffering, array 1580 be divided into two with Upper subnumber group and/or control circuit, such as word decoder, column decoder, segmentation device, sense amplifier, write amplifier Can be arranged in around exemplary array 1580 or insert array 1580 subnumber group middle.Therefore, described one exemplary embodiment, Feature, design option etc. are not construed as limiting.

The operation of memory subassembly 1550, with the mode of operation of the memory subassembly 1350 shown in Figure 187.In event 102, When memory subassembly is energized first, memory subassembly is in original state, and wherein the Nonvolatile memory part of this assembly is set to One predetermined state.In event 104, memory subassembly 1550 runs under volatibility operator scheme, wherein the shape of unit 1550 State is stored in buoyancy aid 224.When power-off or have a power failure suddenly, or other event terminations any or disturb memory subassembly 1550 of the present invention Power supply time, the content of volatile memory " is covered " to event 106 purgation not volatibility memory part.At this moment, memory subassembly is protected Hold the data existed in not volatile ram.When event recovers power supply 108 times, the not content in volatile ram, by inciting somebody to action The content in volatile ram is not transferred to the mode of volatile ram and is recovered, and is followed by event 110 purgation memory group Part resets.

In one embodiment, volatile ram (such as floating gate 260) is not initialised to positive charge, in event In 102.When unit 1550 is energized, unit 1550 stores memory information (being i.e. saved in the data in internal memory), as internal memory Electric charge in assembly 1550 buoyancy aid 224.Electric charge regulation in buoyancy aid 224 flows through the electric current of memory subassembly 1550 (from BL terminal 274 To SL terminal 272).The electric current flowing through memory subassembly 1550 may be used to determine the state of unit 1550.Because not volatile storage Element (such as floating gate 260) is initialized to carry a positive charge, thus any cell current difference be buoyancy aid 224 charge difference it Result.

Under easy disabling mode, internal storage location 1550 can be performed multi-mode operation: preserve, read, write logical value-1 and write Logical value-0 operates.

Figure 21 8 describes the holding operation of memory array 1580, and this array is made up of multiple internal storage locations 1550.By Apply forward feedback in BW terminal 276 to bias, at WL terminal 270, SL terminal 272, BL terminal 274, CG terminal 280 and substrate eventually Apply zero-bias on end 278, perform holding operation.Connect BW terminal and be applied to the forward feedback bias in buried layer district, will Keep the state of its connected internal storage location 1550.

From the point of view of the equivalent circuit representation of the internal storage location 1550 shown in Figure 21 6, internal storage location 1550 includes that n-p-n is double Pole assembly 230a and 230b, respectively by burying wellblock 222 (collector region), buoyancy aid 224 (base region) and bitline regions 216 or source electrode line district 218 (emitter region) forms.

The holding operating principle of unit 1550 is with the operating principle of unit 1350.When buoyancy aid 224 is positively charged, one right Answering the state of logical value-1, bipolar transistor 230a and 230b can be opened, and the positive charge in floater area reduces base stage The electron stream energy barrier in district.Once injecting floater area 224, act in positive bias and bury wellblock 222 times, electrons is swept into burying Wellblock 222 (being connected to BW terminal 276).Due to positive bias, by ionization by collision mechanism, electronics accelerate and produce one extra it Heat carrier (hot hole and thermoelectron to).Thus the thermoelectron of generation flows into BW terminal 276, and the hot hole of generation simultaneously is the most therewith Flow into floater area 224.This process has recovered the electric charge on floater area 224, and remains stored in the electric charge in floater area 224, Thus keeping n-p-n bipolar transistor 230a and 230b to be in by BW terminal 276 when burying and applying positive bias on wellblock 222 Opening.

When buoyancy aid 224 band neutral charge (voltage of buoyancy aid 224 and the voltage on ground connection bitline regions 216 or source electrode line district 218 Identical), the state of a counterlogic value-0, do not have electric current can flow through n-p-n transistor 230a and 230b.Dipole elements 230a Remaining off with 230b, will not collide ionization.Subsequently, logical value-0 state purgation internal storage location is maintained at logic Value-0 state.

In holding operation described in Figure 21 8, the most not selected internal storage location.On the contrary, unit is buried well terminal 276a to 276n embarks on journey selected, can be independent rows, multirow or all row selection constituting array 1580.

In one embodiment, the bias condition of the holding operation of internal storage location 1550 is: the voltage of 0 volt acts on WL In terminal 270, SL terminal 272, BL terminal 274, CG terminal 280 and substrate terminal 278, the positive voltage such as+1.2 volts acts on In BW terminal 276.In other embodiments, different voltages may act on the different terminals of internal storage location 1550, from design choosing Selecting angle to consider, therefore, described exemplary voltage is not intended that restriction.

Figure 21 9 describes the read operation of execution on selected internal storage location 1550a.Read operation can by apply with Lower bias condition performs: a positive voltage acts in selected WL terminal 270a, and a positive voltage acts on selected BL eventually On end 274a, no-voltage acts in CG terminal 280, and no-voltage acts in SL terminal 272, and a positive voltage acts on BW eventually On end 276, and no-voltage acts in substrate terminal 278.

In an exemplary embodiment, the voltage of about+1.2 volts acts in selected WL terminal 270a, about 0.0 volt The voltage of spy acts in selected SL terminal 272a, and the voltage of about+0.4 volt acts on selected bitline terminal 274a, The voltage of about 0.0 volt acts in selected CG terminal 280a, and the voltage of about+1.2 volts acts on and selected buries well terminal The voltage of 276, about 0.0 volt acts in substrate terminal 278.All unselected zigzag terminal 270b to 270n are applied with The voltage of 0.0 volt, bitline terminal 274b to 274p is applied with the voltage of 0.0 volt, unselected SL terminal 272b to 272p Being applied with the voltage of 0.0 volt, unselected CG terminal 280b to 280n is applied with the voltage of 0.0 volt, and unselected BW Terminal 276b to 276p the voltage of ground connection or applying+1.2 volts can maintain the state of unselected cells 1550, about 0.0 volt Voltage act in substrate terminal 278.Figure 21 9 gives in selected representative internal storage location 1550a and memory array 1580 The bias condition of three unselected representative internal storage location 1550b, 1550c and 1550d, each possesses the bias strip of uniqueness Part.One of ordinary skill in the art should notify, and the other embodiments of the present invention, from design alternative angle, can use applying partially Other combination of pressure.These technicians are simultaneously it should also be appreciated that first and second kinds of conductivity type in other embodiments Can be interchangeable, and relative bias can be changed.

When the floater area 224 of elected cell 1550a is positively charged (unit 1550a is in logical value-1 state), that The threshold voltage of MOS transistor 220a and 220b of selected unit 1550a can relatively low (contrasting floater area 224 be the feelings of neutrality Under condition), and a larger current, the source electrode line district 218 of selected unit 1550a can be flowed to from bitline regions 216.Due to floating gate 260 is positively charged when volatile operation, then unit electricity measured between logical value-0 and logical value-1 state lower unit It is poor to flow, and is the potential difference of buoyancy aid 224 and causes it.

For share the internal storage location of colleague with selected internal storage location (such as unit 1550b), BL and SL terminal Ground connection, does not has electric current to flow through.These unit can be in holding pattern, and with the positive voltage acted in BW terminal 276.

For share the internal storage location of same column with selected internal storage location (such as unit 1550c), act on unselected Determine the no-voltage in WL terminal and can cut off the MOS transistor 220a of these unit, thus cause not having electric current to flow through.Due to BW eventually Less difference between end 276 and BL terminals 274, a less holding electric current can flow through these unit.While it is true, due to Charge life (in terms of millisecond magnitude) in write operation (in terms of nanosecond order) relatively buoyancy aid 224 complete faster, therefore it Interrupt the electric charge in buoyancy aid hardly.

For do not share the internal storage location of colleague or same column with selected internal storage location (such as unit 1550d), WL, CG, BL and SL terminal ground connection.These unit can be in holding pattern, and state logic value-1 purgation internal storage location, can be by electric charge Being maintained in buoyancy aid 224, state logic value-0 purgation internal storage location then keeps neutral state.

Write logical value-0 operation of one independent memory unit 1550, is shown in that Figure 22 0A, 220B and 221 introduce.At figure In 220A, back bias voltage acts in SL terminal 272, and zero-bias acts in WL terminal 270, BL terminal 274 and CG terminal 280, Zero or positive voltage act in selected BW terminal 276, no-voltage acts in substrate terminal 278.Under these conditions, selected Any p-n junction between buoyancy aid 224 and the source electrode line district 218 of unit 1550 is positive bias, the emptying any sky from buoyancy aid 224 Cave.Because selected SL terminal 272 is shared by multiple internal storage locations 1550, so logical value-0 can be written into internal storage location In 1550, wherein internal storage location 1550a and 1550b shares same SL terminal 272a simultaneously.

In a specific unrestricted embodiment, the voltage of about-1.2 volts acts in source electrode line terminal 272a, The voltage of about 0.0 volt acts in word line terminal 270, bitline terminal 274 and CG terminal 280, about 0.0 volt or+1.2 volts Voltage act in BW terminal 276, the voltage of about 0.0 volt acts in substrate terminal 278.Come from design alternative angle Seeing, these magnitudes of voltage are only demonstration use, can be because the change of embodiment change.Therefore, the exemplary enforcement in the present invention Example, feature, bias value etc. are construed as limiting in no instance.

In Figure 22 0B, back bias voltage acts in BL terminal 274, and zero-bias acts on WL terminal 270, SL whole 272 and CG In terminal 280, zero or positive voltage act in selected BW terminal 276, no-voltage acts in substrate terminal 278.At these Under the conditions of, any p-n junction between buoyancy aid 224 and the bitline regions 216 of selected unit 1550 is positive bias, and emptying is from buoyancy aid 224 Any hole.Because selected BL terminal 274, shared by multiple internal storage locations 1550 in memory array 1580, so Logical value-0 can be written in internal storage location 1550, and wherein internal storage location 1550a and 1550c shares same BL terminal simultaneously 274a。

In a specific unrestricted embodiment, the voltage of about-1.2 volts acts on bitline terminal 274a, about The voltage of 0.0 volt acts in word line terminal 270, source electrode line terminal 272 and control gate terminal 280, about 0.0 volt or+1.2 The voltage of volt acts in BW terminal 276, and the voltage of about 0.0 volt acts in substrate terminal 278.From design alternative angle From the point of view of, these magnitudes of voltage are only demonstration use, can be because the change of embodiment change.Therefore, the exemplary reality in the present invention Execute example, feature, bias value etc. to be construed as limiting in no instance.

All there is one defect in the operation of above-mentioned write logical value-0: and shared same SL terminal 272 (the first type-OK Write logical value-0) or all internal storage locations 1550 meeting of same BL terminal 274 (the second type-row write logical value-0) It is synchronously written, thus causes logical value-0 being write in independent memory unit 1550.In order to by any binary data write In the internal storage location 1550 of difference, all internal storage locations to be written perform write logical value-0 operation first, then One or more write logical values-1 operation upper for must be written into logical value-1.

The third allows write logical value-0 operation of independent bits write to see that Figure 22 1 illustrates and passes through to execute in WL terminal 270 Add positive voltage, BL terminal 274 apply negative voltage, SL terminal 272 apply no-voltage, in CG terminal 280 apply no-voltage, BW terminal 276 apply zero or positive voltage and substrate terminal 278 apply the mode of no-voltage and perform on internal storage location 1550.? Under the conditions of these, buoyancy aid 224 voltage is increased by the Capacitance Coupled applying positive voltage in selected WL terminal 270.Due to floating The voltage of body 224 increases and is applied to the negative voltage in BL terminal 274, any p-n junction between buoyancy aid 224 and bitline regions 216 For positive bias, the emptying any hole from buoyancy aid 224.

Bother by reducing the unnecessary logical value-0 of writing in memory array 1580, other internal storage locations 1550 brought, institute The voltage of effect can optimize as follows: when buoyancy aid 224 voltmeter of state logic value-1 is shown as V_FB1, then act on selected WL eventually It is V that the voltage of end 270 is configurable to increase the voltage of buoyancy aid 224_FB1/ 2, and-V_FB1/ 2 act in BL terminal 274.Separately Outward, ground connection or more weak positive voltage may also act on not with selected memory unit 1550, share same BL terminal 274 unselected in In the BL terminal 274 of memory cell 1550, and negative voltage may also act on not with selected memory unit 1550, share same WL terminal In the WL terminal 270 of the unselected internal storage location 1550 of 270.

As shown in Figure 22 1, following bias condition acts in exemplary memory array 1580, selected representative it Internal storage location 1550a, performs only just have logical value-0 of independently writing to operate in representative internal storage location 1550a: about 0.0 The voltage of volt acts in SL terminal 272a, and the voltage of about-0.2 volt acts in BL terminal 274a, about+1.2 volts it Voltage acts on word line terminal 270a, and the voltage of about 0.0 volt acts in control gate terminal 280a, the electricity of about+1.2 volts Pressure acts on buries in well terminal 276a, and the voltage of about 0.0 volt acts in substrate terminal 278.Array 1580 is being carried out again During position, the voltage of about 0.0 volt acts on unselected WL terminal (including WL terminal 270b and 270n), the electricity of about 0.0 volt Pressure (or the strongest positive voltage) acts on and (includes BL terminal 274b and 274p) in unselected BL terminal 274, about 0.0 volt Voltage act on and (include SL terminal 272b and 272n) in unselected SL terminal 272, the voltage of about 0.0 volt acts on not In selected CG terminal 280 (including CG terminal 280a and 280n), the voltage of about+1.2 volts acts on unselected BW terminal (BW terminal 276b and 276n is included) on 276.One of ordinary skill in the art should notify, and the magnitude of voltage in Figure 22 1 is only Explaination mesh it, and different embodiment considers to have the magnitude of voltage of difference from design alternative angle.

One write logical value-1 operation can be by above-mentioned Lin or by the interband tunneling of the most above-mentioned Yoshida Ionization by collision described in (alternatively referred to as gate-induced drain leakage or GIDL) is carried out on internal storage location 1550.In conjunction with Figure 22 2A to fortune It is described by a certain write logical value-1 example of operation of GIDL method, and combines Figure 22 2B to using ionization by collision method A certain write logical value-1 example of operation be described.

In Figure 22 2A, describe one during interband tunnel write logical value-1 operation, comprise selected representative internal memory The bias condition example of the array 1580 of unit 1550a.The back bias voltage being applied in WL terminal 270a and be applied to BL terminal Positive bias upper for 274a makes hole be injected in the buoyancy aid 224 of selected representative internal storage location 1550a.SL terminal 272a, CG Terminal 280a and substrate terminal 278 ground connection during write logical value-1 operation, and a positive bias acts on BW terminal 276a On maintain the holding of unselected cells to operate.

Negative voltage in WL terminal 270a is downward, has coupled the electricity of floater area 224 in representative internal storage location 1550a Pressure.In selected representative internal storage location 1550a, (it is thus GIDL in conjunction with positive voltage BL terminal 274a at selection grid 264 It " grid cause " part) near bitline regions 216 and floater area 224 between create a highfield.And this makes it possible to band at door And the most significantly bend near drain junction overlapping area, cause electronics to be tunnelled to conduction band from valance band, hole is stayed In valance band.Tunneling through the electronics of band drain leakage (being thus it " drain current " part of GIDL) can be become, and hole It is injected into floater area 224 and becomes the hole charge of generation logical value-1 state.This process is the most famous in this area, Above-mentioned Yoshida (particularly Fig. 2 and 6 and Fig. 9 of page 4 of page 3) there is explaination.

In a specific unrestricted embodiment, the voltage of about-1.2 volts acts on word line terminal 270a, about+ The voltage of 1.2 volts acts on bitline terminal 274a, and the voltage of about 0.0 volt acts on source electrode line terminal 272a and control gate In terminal 280a, the voltage of about 0.0 volt or+1.2 volts acts in BW terminal 276, and the voltage of about 0.0 volt acts on lining In end terminal 278.From the point of view of design alternative angle, these magnitudes of voltage are only demonstration use, can be because the change of embodiment become Change.Described one exemplary embodiment, feature, bias value etc. are construed as limiting in no instance.

Figure 22 2B describes write logical value-1 operation using ionization by collision method.In this case, to be written it The selection grid 264 of internal storage location 1550 and bit line 216 bias under positive voltage so that buoyancy aid 224 is charged by ionization by collision flowing To logical value-1 state, regardless of the data being originally stored in unit.

In the one exemplary embodiment shown in Figure 22 2B, selected zigzag terminal 270a biases when+1.2 volts, and not Selected zigzag terminal 270b to 270n then biases when 0.0 volt；Selected bitline terminal 274a is also inclined when+1.2 volts Pressure, and unselected bitline terminal 274b to 274p biases when 0.0 volt, selected source electrode line 272a is inclined when 0.0 volt Pressure, and unselected source electrode line terminal 272b to 272n biases when 0.0 volt, all control gate terminals 280 are when 0.0 volt Bias, buries well terminal 276 and biases (maintaining the state of unselected cells) when 0.0 or+1.2 volts, and substrate terminal 278 is then Bias when 0.0 volt.These bias values only for demonstration mesh it, can according to embodiment change and change, therefore in any situation Under all without being construed as limiting.

The embodiment performing to cover operation on unit 1550 is described by Figure 22 3A: a positive voltage acts on SL In terminal 272a, a positive voltage acts in WL terminal 270a, and no-voltage acts in BL terminal 274a, and positive voltage acts on In CG terminal 280a, zero or positive voltage act in BW terminal 276a, and no-voltage acts in substrate terminal 278.

In a specific unrestricted embodiment, the voltage of about+6.0 volts acts in source electrode line terminal 272, about The voltage of+1.2 volts acts in WL terminal 270, and the voltage of about 0.0 volt acts on bitline terminal 274, about+6.0 volts Voltage act in control gate terminal 280, the voltage of about 0.0 volt or+1.2 volts acts in BW terminal 276, about 0.0 The voltage of volt acts in substrate terminal 278.From the point of view of design alternative angle, these magnitudes of voltage only for demonstration use, can because The change of embodiment changes.Therefore, the one exemplary embodiment in the present invention, feature, bias value etc. are the most all It is not construed as limiting.

When buoyancy aid 224 positively charged/voltage time, MOS assembly 220a opens.MOS assembly 220a purgation surface voltage is equal to Act in BL terminal 274 pressure reduction between voltage and the voltage acted in WL terminal 270 and MOS assembly 220a upper threshold voltage In small voltage.And the positive voltage being applied on control gate 240 (through CG terminal 280) can be capacitively coupled to floating gate 260 On.Therefore, MOS assembly 220b purgation surface voltage can increase, and according to the positive charge in floating gate 260, can be close to executing It is added in the voltage in source electrode line district 218.Then, a powerful transverse electric field can produce around interstitial area 268.This is the most electric Field can encourage/promote electronics to flow to source electrode line district 218 (MOS assembly 220a and 220b opens simultaneously) from bitline regions 216, reaches foot The stop oxide layer between buoyancy aid 224 and floating gate 260 is skipped again during amount.And potential difference between floating gate 260 (part be because of For control gate 240 and source electrode line district 218 and the coupling on surface 214) and therefore the big longitudinal electric field of one of generation can produce.So Electronics just can enter floating gate 260.Correspondingly, (the buoyancy aid when the volatile memory of unit 1550 is in logical value-1 state 224 is positively charged), floating gate 260 is electronegative by the method for covering.

When buoyancy aid 224 is neutral, the threshold voltage of MOS assembly 220a higher (compare buoyancy aid 224 positively charged time threshold Threshold voltage), and MOS assembly 220a is closed.Therefore, electrons is not had to flow through unit 1550.Correspondingly, easily when unit 1550 Losing (buoyancy aid 224 is for time neutral) when memorizer is in logical value-0 state, floating gate 260 just keeps at the end of covering operation Electric charge.

Covering after operation terminates, the state of charge of floating gate 260 is complementary with the state of charge of buoyancy aid 224.Therefore, if When the buoyancy aid 224 of internal storage location 1550 is positively charged in volatile memory, floating gate 260 is electronegative by meeting after covering operation Lotus, and when the buoyancy aid 224 of internal storage location 1550 carries negative or neutral charge in volatile memory, floating gate layer 260 can hide At the end of covering operation positively charged.Electric charge/the state of floating gate 260 then depends on the state of buoyancy aid with the relation of non-algorithm, and Covering of multiple unit occurs with parallel way, therefore covers speed of operation and is exceedingly fast.

Another embodiment performing to cover operation on unit 1550 is described by Figure 22 3B: a positive voltage effect In CG terminal 280, a positive voltage acts in WL terminal 270, and no-voltage acts in BL terminal 274, zero or positive voltage Acting in BW terminal 276, no-voltage acts in substrate terminal 278, and SL terminal 272 is then floated.

In a specific unrestricted embodiment, the voltage of about+12.0 volts acts in control gate terminal 280, The voltage of about+1.2 volts acts on word line terminal 270, and the voltage of about 0.0 volt acts on bitline terminal 274, and about 0.0 Volt or the voltage of+1.2 volts act in BW terminal 276, and the voltage of about 0.0 volt acts in substrate terminal 278, and source Polar curve terminal 272 is then floated.From the point of view of design alternative angle, these magnitudes of voltage are only demonstration use, can be because of the change of embodiment Change.Therefore, the one exemplary embodiment in the present invention, feature, bias value etc. are construed as limiting in no instance.

When buoyancy aid 224 positively charged/voltage time, MOS assembly 220a opens, conduction be applied in BL terminal 274 zero electricity Pressure.When the bias being applied on control gate 240 is sufficiently large, such as " one be applicable to below 40nm and above technology no 64 unit nand flash memories of symmetrical source/drain structures are K-T.Park et al., 19-20 page, technical papers digest, nineteen ninety-five VLSI technical seminar, (is fully incorporated herein middle as reference, be hereinafter called for short " Park ") in nineteen ninety-five and is described it Disperse electric field can produce a reversal zone in interstitial area 268.Therefore, it is applied to the no-voltage in BL terminal 274 also can be passed The channel region of the MOS assembly 220b below floating gate 260.Owing to control gate 240 is coupled to the effect of floating gate 260, floating A powerful longitudinal electric field is defined in moving grid 260 and channel region below.This powerful longitudinal electric field can order about electricity Son is tunneling to floating gate 260 from channel region.Correspondingly, when the volatile memory of unit 1550 is in logical value-1 state ( Buoyancy aid 224 is positively charged), floating gate 260 is electronegative by the method for covering.

When buoyancy aid 224 is neutral, the threshold voltage of MOS assembly 220a higher (compare buoyancy aid 224 positively charged time threshold Threshold voltage), and MOS assembly 220a is closed.Therefore, floating gate 260 channel region below can flow.And it is applied to control gate Positive voltage on 240 can increase floating gate 260 raceway groove pressure below on the contrary, and then electric field construction is not enough to order about electron tunneling To floating gate 260.Correspondingly, when the volatile memory of unit 1550 is in logical value-0 state, (buoyancy aid 224 is neutrality Time), floating gate 260 keeps positive charge at the end of covering operation.

Figure 22 4 describes the recovery operation when unit 1550 recovers power supply.Recovery operation can will exist on floating gate 260 Unit 1550 recovering state in floater area 224.Before performing recovery operation, buoyancy aid 224 is set to neutral state, i.e. memory group Part 1550 removes buoyancy aid state during power supply.In order to perform recovery operation, apply following bias condition: a positive voltage effect In SL terminal 272, no-voltage acts in WL terminal 270, CG terminal 280 and BL terminal 274, zero or positive voltage act on BW In terminal 276, no-voltage acts in substrate terminal 278.

In a specific unrestricted embodiment, the voltage of about+1.2 volts acts in source electrode line terminal 272, about The voltage of 0.0 volt acts on word line terminal 270, control gate terminal 280 and bitline terminal 274, about 0.0 volt or+1.2 volts The voltage of spy acts in BW terminal 276, and the voltage of about 0.0 volt acts in substrate terminal 278.Come from design alternative angle Seeing, these magnitudes of voltage are only demonstration use, can be because the change of embodiment change.Such as, a positive voltage may act on position In line terminal 274 or a negative voltage acts on no current when ensureing recovery operation in wordline 270 and flows through the ditch of unit 1550 Road district.Therefore, described one exemplary embodiment, feature, bias value etc. are not construed as limiting.

When floating gate 260 is electronegative, the negative charge on floating gate 260 and the positive voltage in SL terminal 272, floating Produce a powerful electric field between source electrode line district 218 and floater area 224 near grid 260, and this makes it possible to band at Men Heyuan The most significantly bend near polar curve node overlapping area, cause electronics to be tunnelled to conduction band from valance band, curtain is stayed in hole In curtain band.Tunneling through the electronics of band drain leakage can be become, and hole is injected into floater area 224 and becomes generation logic The hole charge of value-1 state.In this area, this process is referred to as band-to-band tunnelling or gate-induced drain leakage (GIDL) machine Reason, such as, have explaination in above-mentioned Yoshida (particularly Fig. 2 and 6 and Fig. 9 of page 4 of page 3).BL terminal 274 ground connection or Positive voltage effect avoids electric current to flow through the channel region of unit 1550 on it.

When floating gate 260 is positively charged, the positive charge on floating gate 260 and source electrode line district 218 will not produce powerful it Electric field, orders about hole and is injected in buoyancy aid 224.Therefore, buoyancy aid 224 can be maintained at neutral state.

It can be seen that when floating gate 260 perform cover after positively charged, the volatile ram of buoyancy aid 224 can return to Band neutral charge (logical value-0 state), but when floating gate 260 is electronegative, the volatile ram of buoyancy aid 224 can return to Positively charged (logical value-1 state), thus before covering operation, return to the initial condition of buoyancy aid 224.Note: this process with Non-calculation mode occurs, because floating gate 260 state determines the shape of buoyancy aid 224 recovery without carrying out reading, understand or measure State.On the contrary, recovery process occurs automatically, potential difference drive.Correspondingly, this process is the order of magnitude, and ratio requires that algorithm is got involved Speed faster.

After recovering internal storage location 1550, floating gate 260 resets to default conditions, such as introduce it in Figure 22 5A and 225B Positive status so that each floating gate 260 has a known state before performing another and covering operation.Reset by using interband Tunneled holes is injected into the principle of floating gate 260 and operates, as shown in Figure 22 5A, or by 260 beginnings of self-relocation grid Electron tunneling, as shown in Figure 22 5B.

Reset in Figure 22 5A uses the principle similar with recovery operation.Electronegative floating gate 260 can produce one Generate the electric field of hot hole.Most of hot holes of generation are injected in buoyancy aid 224, and smaller portions are injected into floating gate 260 In.One higher voltage may act on and increases the speed that the operation that resets is desired in SL terminal 272.Hole is injected and is only occurred In the unit 1550 of electronegative floating gate 260.Therefore, before reset operation terminates, all floating gates 260 are initialized to Positively charged.

In a specific unrestricted embodiment, the voltage of about+3.0 volts acts in source electrode line terminal 272, about The voltage of 0.0 volt acts on word line terminal 270, control gate terminal 280 and bitline terminal 274, about 0.0 volt or+1.2 volts The voltage of spy acts in BW terminal 276, and the voltage of about 0.0 volt acts in substrate terminal 278.Come from design alternative angle Seeing, these magnitudes of voltage are only demonstration use, can be because the change of embodiment change.Therefore, described one exemplary embodiment, spy Levy, bias value etc. is construed as limiting in no instance.Bias condition is with the bias condition of recovery operation.Bias condition is with extensive The bias condition of multiple operation.While it is true, owing to injecting the sky that the number of cavities ratio in floating gate 260 is injected in buoyancy aid 224 Cave quantity to be lacked, and the operation that resets is slower than recovery operation.Negative voltage may also act on and buries in well terminal 276, to ensure not having hole It is accumulated in the internal storage location 1550 of positively charged floating gate 260, and positive voltage may also act on bitline terminal 274, with resistance Only electric current flows through the channel region of unit 1550.

Figure 22 5B is tunneling to select the mode of grid 264 to describe reset operation from floating gate 260 by electronics.One positive electricity Pressure acts in WL terminal 270, and a negative voltage acts in CG terminal 280, and no-voltage acts in BL terminal 274, and SL terminal 272 is then floated, and no-voltage or positive voltage may act in BW terminal 276, and no-voltage acts in substrate terminal 278. It is applied to the positive voltage (by WL terminal 270) on selection grid 264 and the negative voltage being applied on control gate 240 is (whole by CG End 280), highfield can be produced through selecting grid 264 and floating gate 260 so that electronics is tunneling to select grid from floating gate 260 264。

In a specific unrestricted embodiment, the voltage of about+1.2 volts acts in WL terminal 270, about- The voltage of 12.0 volts acts in CG terminal 280, and the voltage of about 0.0 volt acts in BL terminal 274, and SL terminal 272 is floated Dynamic, the voltage of about 0.0 volt or+1.2 volts acts in BW terminal 276, and the voltage of about 0.0 volt acts on substrate terminal On 278.From the point of view of design alternative angle, these magnitudes of voltage are only demonstration use, can be because the change of embodiment change.Example As, BL terminal 274 is likely to float.Therefore, described one exemplary embodiment, feature, bias value etc. are in no instance It is construed as limiting.

Figure 22 6 operates another embodiment of 200 about memory subassembly 1550.The control gate 240 of unit 1550 can be used to hinder There is the electric charge in floating gate 260 in gear.Therefore, volatibility operation 104 can be in the situation without initial reset floating gate 260 state Lower execution.During power failure, the operation 110 that resets performs first, then for covering operation, buoyancy aid 224 state is transferred to floating gate 260.Once recovering power supply in event 108, the content in volatile ram does not returns in volatile ram, and memory subassembly Volatile ram operation 104 can be immediately entered.Which reduce the startup time of memory subassembly 1550, i.e. power up and by mobile multiple Bit manipulation 110 carries out the time between the operation of memory subassembly 1550 volatile memory to power failure operation.

For the electric charge deposited in stopping floating gate 260, under easy disabling mode operates, on control gate 240, it is applied with one Positive bias (by CG terminal 280), such as, use ionization by collision principle to carry out volatile read operation and write logical value-1 operation Time.

Figure 22 7 describes the bias condition example performing read operation on selected internal storage location 1550a.Read operation Can perform by applying following bias condition: a positive voltage acts in selected WL terminal 270a, a positive voltage effect In selected BL terminal 274a, a positive voltage acts in CG terminal 280a, and no-voltage acts in SL terminal 272, and one Individual positive voltage acts in BW terminal 276, and no-voltage acts in substrate terminal 278.

In an exemplary embodiment, the voltage of about+1.2 volts acts in selected WL terminal 270a, about 0.0 volt The voltage of spy acts in selected SL terminal 272a, and the voltage of about+0.4 volt acts on selected bitline terminal 274a, The voltage of about+5.0 volts acts in selected CG terminal 280a, and the voltage of about+1.2 volts acts on and selected buries well terminal On 276, the voltage of about 0.0 volt acts in substrate terminal 278.All unselected zigzag terminal 270b to 270n are applied with The voltage of 0.0 volt, bitline terminal 274b to 274p is applied with the voltage of 0.0 volt, unselected SL terminal 272b to 272p Being applied with the voltage of 0.0 volt, unselected CG terminal 280b to 280n is applied with the voltage of 0.0 volt, and unselected BW Terminal 276b to 276n the voltage of ground connection or applying+1.2 volts can maintain the state of unselected cells 1550, about 0.0 volt Voltage act in substrate terminal 278.One of ordinary skill in the art should notify, and the other embodiments of the present invention is from setting Meter selected angle can use other combination being biased.These technicians are simultaneously it should also be appreciated that in other embodiments First and second kinds of conductivity type can be interchangeable, and relative bias can be changed.

The positive voltage being applied in the CG terminal 280 selected can produce a reversal zone below floating gate 260, the most floating The electric charge deposited in moving grid 260.Therefore, MOS assembly 220b is in opening, and internal storage location 1550 electrical conductivity depends on MOS assembly 220a.The threshold voltage of MOS assembly 220a is adjusted by the electric charge deposited in buoyancy aid 224 on the contrary.Positively charged it Buoyancy aid 224 can produce a relatively low MOS assembly 220a threshold voltage, situation when being neutral relative to buoyancy aid.

Figure 22 8 describes another write logical value-1 operation using ionization by collision method.In this case, one just Voltage is applied on control gate 240 (by CG terminal 280) so that buoyancy aid 224 is charged to logic by impact ionization current flowing Value-1 state, regardless of the electric charge deposited in floating gate 260.

In one exemplary embodiment shown in Figure 22 8, selected zigzag terminal 270a biases when+1.2 volts, and unselected Zigzag terminal 270b to 270n then biases when 0.0 volt；Selected bitline terminal 274a also biases when+1.2 volts, and Unselected bitline terminal 274b to 274p biases when 0.0 volt, and selected source electrode line 272a and unselected source electrode line are eventually End 272b to 272n biases when 0.0 volt, and control gate terminal 280a biases when+5.0 volts, and unselected control gate is eventually End 280b to 280n biases when 0.0 volt, buries well terminal 276 and biases when 0.0 or+1.2 volts and (maintain unselected cells State), substrate terminal 278 then when 0.0 volt bias.These bias values only for demonstration mesh it, can according to embodiment become Change and change, thus without being construed as limiting.

Other easy disabling mode operation of execution on internal storage location 1550, is relative with the electric charge deposited in floating gate 260 Independence.Such as, the operation of write logical value-0 is heavily dependent on buoyancy aid 224 and bitline regions 216 (or source electrode line district 218) Between pressure reduction.In these operate, control gate can ground connection, or a positive bias also can be respectively applied to Figure 22 7 He similarly In reading described in 228 and write logical value-1 operation

In another embodiment of internal storage location 1550, instead volatile ram material can be used.Foregoing description uses Floating polysilicon gate is as nonvolatile memory material.The charge-trapping material that such as nanocrystal silicon or silicon nitride are made, it is possible to As not volatile ram material.No matter being to use floating gate 260 or barrier layer 160, function is just as it, because they It is all holding data in the case of short of electricity, and aforesaid operations mode also can perform.Between floating gate 260 and barrier layer 260 it Differring primarily in that floating gate 260 is a conductor, barrier layer 260 is then an insulating barrier.

Above-mentioned internal storage location 1350,1450 and 1550 also can assemble on epitaxial silicon (SOI) substrate on insulator.Figure 22 9A Describing unit 1350S, 1450S and 1550S to 229C, wherein the bottom of buoyancy aid is respectively by insulator region 22S, 122S and 222S Surround.

Figure 22 9A is the cross-sectional view of internal storage location 1350S.Internal storage location 1350S includes the first conductivity type, example Silicon on insulator (SOI) substrate 12 such as p-type.Substrate 12 is made by silicon is special, but also can be by such as germanium, germanium silicon, arsenic Change the semi-conducting material such as gallium, CNT composition.Substrate 12 then has buried insulator layer 22S, such as buried oxide (BOX)

The floater area 24 of the first conductivity type such as p-type, draws an analogy, and is by bitline regions 16, source electrode line district up 18 and insulating barrier 62 surround, bottom is surrounded by buried layer 22S.

There is the bitline regions 16 of the second conductivity type such as n-type, draw an analogy, be present in floater area 24 and expose On surface 14.According to any known and injection technology of art Special use, bitline regions 16 is by injection technology shape Become on the material constituting substrate 12.Or, form bitline regions 16 by solid state diffusion process.

There is the source electrode line district 18 of the second conductivity type such as n-type, draw an analogy, exist in floater area 24 also It is exposed to surface 14.According to any known and injection technology of art Special use, source electrode line district 18 is by injecting Technique is formed at above the material constituting substrate 12.Or, form source electrode line district 18 by solid state diffusion process.

One completely depleted SOI substrate, as shown in Figure 22 9A, shape in multiple unit 1350S are integrated into an array When becoming a memory subassembly so that unit 1350S need not be kept apart by insulating barrier with neighbouring unit 1350S.Bitline regions 16 and source electrode line district 18 share together with neighbouring unit 1350S.In a SOI surface not exclusively exhausted (the most Show), such as shallow trench isolation (STI), can be used to keep apart unit 1350S with adjacent unit 1350S.

The operation of internal storage location 1350S is similar with the operation of internal storage location 1350.While it is true, due in unit 1350S Lack and bury wellblock, and can not carry out keeping operation (applying positive bias in well terminal burying of unit 1350).One is used for updating The regular update operation of unit 1350S can be carried out, as being fully incorporated herein work by applying positive bias in source electrode line district 18 Described in reference it " automatically updating of elemental floating body ", author T.Ohsawa et al., holds it in 1997 by 1-4 page IEEE International Electro assembly meeting) (hereinafter referred to as " Ohsawa-2 ").

Figure 22 9B and 229C describes unit 1450S and 1550S of assembling on epitaxial silicon substrate on insulator, wherein, Buried insulator 122S/222S, such as buried oxide (BOX), surrounds from bottom by buoyancy aid substrate 124/224.Relevant unit The great majority of 1450/1550 describe and are also applied for unit 1450S/1550S.Similarly, owing to unit 1450S/1550S lacking Bury wellblock, and can not carry out keeping operation (applying positive bias in well terminal burying of unit 1450/1550).One is used for updating The regular update operation of unit 1450S/1550S can be carried out by applying positive bias in source electrode line district 118/228

Internal storage location 1350,1450 and 1550 also may make up the fin structure shown in Figure 23 0A to 230C.Similarly, interior Memory cell 1350S, 1450S and 1550S the most optionally constitute fin structure.

Figure 23 0A is the cross-sectional view of internal storage location 1350V.Unit 1350V has a fin structure 52, is assemblied in substrate On 12, thus from substrate surface extend and form a three dimensional structure, fin 52 extend generally perpendicular to and at substrate 12 it Upper surface.Fin structure 252 can conduct electricity and be positioned at and bury on well layer 222.Fin structure 52 can conduct electricity, and sets up and is burying on well layer 22, Himself is then positioned at above substrate 12.Or, burying well 22 can be the interior diffusate of substrate 12, and remaining fin 52 is above, or Burying well 22 can be to be connected to above all other fin 52 structure (mode with as above-mentioned internal storage location 1350) substrates 12 Conductive layer.Fin 52 is made up of silicon typical case, but also comprises known in the art partly the leading such as germanium, germanium silicon, GaAs, CNT Body material.

Bury well layer 22 to be formed on the material of substrate 12 by ion implantation technology.Or, burying well layer 22 can extension life Long side on the substrate 22.There is burying well layer 22 and having the first of the second conductivity type (such as N-shaped conductivity type) The floater area 24 of conductivity type (such as p-type conductivity type), with have the bulk substrate 12 of the first conductivity type every Leave.Fin structure 52 includes bitline regions 16 and the source electrode with the second conductivity type (such as N-shaped conductivity type) Line district 18.Be similar to internal storage location 1350, unit 1350V be also asymmetric it, such as have to floating gate 60 from source electrode line district 18 There is higher Capacitance Coupled.Internal storage location 1350V also includes the floating gate 60 of the 24 liang of opposite side in floating substrate district, by insulating barrier 62 Isolate with buoyancy aid 24.Floating gate 60 is between bitline regions 16 and source electrode line district 18, near buoyancy aid 24.

Therefore, floater area 24 by the upper surface of fin 52, the front of bitline regions 16 and bottom, bury wellblock 22 and insulating barrier 26 Top (see the top view of Figure 23 0B relevant unit 1350V) surrounds.When multiple unit 1350V set forms a memory array Time, unit 1350V can be kept apart by insulating barrier 26 with neighbouring unit 1350V.

Shown in Figure 23 0C, one replaces it fin structure 1350V and can set up.In this embodiment, floating gate 60 He Insulating barrier 62 can impale three limits in floating substrate district 24.In on three limits, the existence of floating gate 60 allows floater area 24, electric charge is more preferably Control.

Internal storage location 1350V can be used to replace one and between unit and array control signal terminal, has identical company The internal storage location 1350 that the array 1380 of connecing property is similar in array.In such a scenario, keep, read and write operation with Similar in cross-member embodiment described in internal storage location 1350 in array 1380 in the early time.Together with other embodiments, first Plant and the second conductivity type, can change according to design alternative.Together with other embodiments, other of a lot of assemblies become Change and combination is possible, and described example must not limit the present invention.Additionally, internal storage location 1350V also can be at insulator Assemble on upper epitaxial silicon (SOI) substrate.

Figure 23 0D and 230E introduces unit 1450V and 1550V constituting fin 152/252.Relevant unit 1450/1550 it Great majority describe and are also applied for unit 1450V/1550V.The reference number previously related in drawing and having in previous embodiment Identical, similar or similar effect.Selection grid, floating gate and control gate on unit 1450V/1550V also can impale floating lining All limits of base area 124/224.Additionally, internal storage location 1450V/1550V also can the upper assembling of epitaxial silicon (SOI) on insulator.

Complete a novel semi-conductor internal memory with volatile and the most volatile function.A lot of embodiments of the present invention have Describe.One of ordinary skill in the art should notify, these embodiments be for demonstration mesh it, explain the principle of the present invention. A lot of other embodiments are it should be mentioned that these technicians also should be in conjunction with institute's drawing when reading this specification.Such as:

The first and the second conductivity type are convertible, the polarity of voltage reversible of applying, but all should be maintained at this In bright scope.

When the exemplary voltage value of a lot of difference is for different operating and embodiment, in terms of design alternative angle, understand because of It is varied from for embodiment is different, but preferably must be held in the scope of the invention.

Under any process geometries or technology node, the present invention can use any technique to manufacture, but must belong to In the scope of the invention.Furthermore, it is necessary to understand is: drawing draw mesh be not configured to conveniently understand and clearly read, and arbitrarily Layer composition, thickness, doped level, material etc. can use within the scope of the present invention.

Although one exemplary embodiment give especially with simple as mesh single memory array, explain different herein The operation of internal storage location, but the memory subassembly of employing internal storage location is from the point of view of design alternative angle, in structure and organizational aspects A difference is had etc. a lot of detail aspects, but the most within the scope of the present invention.These embodiments are possible, but are not limited to, Including the most multiple memory array, it is with or without the different control line segmentations of multi-level decoding, in memory array or same array Middle synchronization performs multiple operations, uses much different voltage or current-sensing circuit to perform read operation, uses various decoding side Case, uses the internal storage location of more than one type, uses the interface of any type to contact with other circuit, and/or uses ability The analog circuit of a lot of differences that territory is known, produces voltage or electric current thus carries out various operation in memory array.This Analog circuit is likely not to have and is limited to, such as, and digital-to-analog converter (DACs), AD converter (ADCs), fortune Calculate amplifier (Op Amps), comparator, voltage reference circuit, current mirror, emulation buffer etc..

Therefore, the present invention in no instance should be restricted, in appended claims opinion except.

Claims

1. a semiconductor memory cell, is made up of following assemblies:

It is configured to be charged to the floater area of an instruction state of memory cells level；

The firstth district of making electrical contact with is carried out with above-mentioned floater area；

The secondth that make electrical contact with and spaced apart with the firstth above-mentioned district district is carried out with above-mentioned floater area；

Grid between the firstth above-mentioned district and the secondth district；And

It is configured to inject electric charge to above-mentioned floater area or from floater area, extract electric charge out, to keep the anti-of state of memory cells Feedback bias region.

Semiconductor memory cell the most according to claim 1, the first the most above-mentioned zone has from a P-type conduction class The first conduction type selected in type, and a n-type conduction type；

Wherein, above-mentioned floater area has second conduction type selected from P-type conduction type, and n-type conduction type, This second conduction type is different with the first above-mentioned conduction type；

Wherein, there is the first above-mentioned conduction type in the secondth above-mentioned district；And

Wherein, above-mentioned back bias comprises a substrate with above-mentioned first conduction type.

Semiconductor memory cell the most according to claim 1, this element comprises one further and passes with from a P-type The substrate of the first conduction type selected in conductivity type, and a N-shaped conduction type；

Wherein, there is second conduction type selected from P-type conduction type and N-shaped conduction type in the firstth above-mentioned district, this Second conduction type is different with the first above-mentioned conduction type；

Wherein, above-mentioned floater area has the first conduction type；

Wherein, there is the second above-mentioned conduction type in the secondth above-mentioned district；And

Above-mentioned back bias comprises a buried layer with above-mentioned second conduction type, and this buried layer is placed in above-mentioned buoyancy aid Between district and above-mentioned substrate.

Semiconductor memory cell the most according to claim 1, this element also comprises following assemblies:

It is connected electrically to a root line terminals in one of the first and secondth above-mentioned district；

It is connected electrically to a bit line terminal in one of the first and secondth above-mentioned district；

It is connected electrically to a wordline terminal in one of the first and secondth above-mentioned district；

It is connected to a wordline terminal of above-mentioned grid；And

It is connected to a back bias terminal in above-mentioned back bias district.

Semiconductor memory cell the most according to claim 2, this element also comprises following assemblies:

It is connected to a wordline terminal of above-mentioned grid；And

Being connected to a base-plate terminal of above-mentioned substrate, this base-plate terminal is configured to serve as a back bias terminal.

Semiconductor memory cell the most according to claim 3, this element also comprises following assemblies:

It is connected to a wordline terminal of above-mentioned grid；And

One that is connected to above-mentioned buried layer is buried well terminal, and this buries well terminal and is configured to serve as a back bias terminal.

Semiconductor memory cell the most according to claim 4, wherein, applies back bias at above-mentioned back bias terminal The electric charge leaked out from above-mentioned floater area for counteracting.

Semiconductor memory cell the most according to claim 7, wherein, above-mentioned back bias is as a constant positively biased Pressure.

Semiconductor memory cell the most according to claim 7, wherein, above-mentioned back bias is as a periodicity positive electricity Pressure pulse.

Semiconductor memory cell the most according to claim 1, wherein, can be stored in the maximum electricity of above-mentioned floater area Gesture, can be improved by above-mentioned back bias district is applied back bias, thus obtain relatively large memory window.

11. semiconductor memory cells according to claim 4, wherein, apply feedback partially at above-mentioned back bias terminal Pressure keeps operation for performing one at above-mentioned unit.

12. semiconductor memory cells according to claim 1, the most above-mentioned unit is a multilevel-cell, above-mentioned Floater area is configured to store multidigit and indicate multiple state；Further, wherein said units is used for monitoring its cell current, To determine the state of this unit.

13. 1 kinds of semicondctor storage arrays, this semicondctor storage array includes:

According to claim 1, multiple semiconductor memory cells of matrix it are arranged in by row and column.

14. 1 kinds of semicondctor storage arrays, this semicondctor storage array includes:

Multiple semiconductor memory cells of matrix it are arranged in by row and column, here, above-mentioned each semiconductor memory cell bag Include following assembly:

15. semicondctor storage arrays according to claim 14, wherein, each firstth above-mentioned district has from one First conduction type selected in P-type conduction type and n-type conduction type；

Wherein, each above-mentioned floater area has from a P-type conduction type and n-type conduction type selected one the Two conduction types；This second above-mentioned conduction type is different with the first above-mentioned conduction type；

Wherein, there is the first above-mentioned conduction type in each secondth above-mentioned district；And

Wherein, each above-mentioned back bias district comprises a substrate with the first above-mentioned conduction type.

16. semicondctor storage arrays according to claim 14, wherein, each above-mentioned unit also comprises from one The substrate of second conduction type selected in P-type conduction type and n-type conduction type；

Wherein, each the firstth above-mentioned district, there is selected from P-type conduction type and n-type conduction type one second Conduction type, this second above-mentioned conduction type and the first conduction type are different；

Wherein, each above-mentioned floater area has the first above-mentioned conduction type；

Wherein, there is the second above-mentioned conduction type in each secondth above-mentioned district；And

Wherein, each above-mentioned back bias district, comprise a buried layer with the second above-mentioned conduction type, this is above-mentioned Buried layer between above-mentioned floater area and above-mentioned substrate.

17. semicondctor storage arrays according to claim 14, wherein, each row or column of said units, all connect In row or column, be electrically connected a source line terminals is carried out to each first or second district of each said units, thus, Each above-mentioned row or column, all passes through the addressable above-mentioned source line terminals of one of them, carries out separate connection；

Wherein, other each row or column of said units, it is all connected to exist with each first or second district of each said units Carry out on a bit line terminal being electrically connected in other row or column corresponding, thus, each other above-mentioned row or column, the most logical The addressable above-mentioned bit line terminal crossing one of them carries out separate connection；

Wherein, each row or column of said units, it is all connected to and each grid of each said units, enterprising in corresponding row or column One wordline terminal of row electrical connection, thus, each above-mentioned row or column, all pass through the addressable of one of them Above-mentioned wordline terminal carries out separate connection；

Wherein, at least a row or column of said units

It is connected to corresponding to carry out in few a row or column to be electrically connected with each back bias district of each said units On one back bias terminal.

18. semicondctor storage arrays according to claim 17, the most above-mentioned back bias terminal is generally above-mentioned Array all unit on.

19. semicondctor storage arrays according to claim 17, the most above-mentioned back bias terminal is divided into that These multiple sections separated, so that the bias that part chosen on above-mentioned semiconductor memory array applies can be carried out solely by it Vertical control.

20. semicondctor storage arrays according to claim 17, wherein, are applied on above-mentioned back bias terminal Back bias, on above-mentioned unit perform keep operation, and can by select one or more above-mentioned source lines, bit line and Wordline terminal accesses chosen unit.

21. semicondctor storage arrays according to claim 17, it comprises further and is configured to execute back bias It is added to the voltage generator circuit on above-mentioned back bias terminal.

22. semicondctor storage arrays according to claim 17, it comprises further and is configured to produce above-mentioned storage One of the initial accumulated unit electric current of unit is with reference to generator circuit, and what this Memory Sharing one was selected is written of source Line.

23. semicondctor storage arrays according to claim 17, it comprises further and is configured to produce above-mentioned storage One of the initial accumulated unit electric current of unit is with reference to generator circuit, and what this Memory Sharing one was selected is written of source Line.

24. semicondctor storage arrays according to claim 17, its assembly also comprises and is configured to represent above-mentioned depositing The storage electric charge of one original state of storage unit, the source that the is written of line that this Memory Sharing one is selected.

25. semicondctor storage arrays according to claim 14, wherein, each above-mentioned cell location is multilamellar list Unit, on it, each above-mentioned floater area is configured to the multidigit multiple states of instruction of storage, in described floater area not Same change represents different storage states.