JPS5961178A - Semiconductor device for power - Google Patents
Semiconductor device for powerInfo
- Publication number
- JPS5961178A JPS5961178A JP17165682A JP17165682A JPS5961178A JP S5961178 A JPS5961178 A JP S5961178A JP 17165682 A JP17165682 A JP 17165682A JP 17165682 A JP17165682 A JP 17165682A JP S5961178 A JPS5961178 A JP S5961178A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- pattern
- base
- patterns
- polygons
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 239000006185 dispersion Substances 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000000638 solvent extraction Methods 0.000 abstract 1
- 239000000969 carrier Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 241000218645 Cedrus Species 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 201000004569 Blindness Diseases 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
(技 術 分 甲f 〕
この発明は、バイポーラパワートランジスタ構造を備え
た電力用半導体装置の高速スイッチング特性向上に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Section Af) This invention relates to improving the high-speed switching characteristics of a power semiconductor device having a bipolar power transistor structure.
電力用゛1′*悴装置m、 vcおいては、バイポーラ
パワートランジスタは、一般にMOS FETノぐワー
トランジスタと比較すれば、周知の通り高速スイッチン
グ特性が劣るにもかかわらず製造技術的に先行しており
、量産性が優れ低価格である。よって、バイポーラパワ
ートランジスタ構造の電力用半導体装置は、スイッチン
グ式電源等に依然として賞用されている。しかし、上記
スイッチング式電源等は、現在も益々小型化、軽量化の
必要から、半導体装置のスイッチング速度を数百KHz
もの超高速化させることが要求されている。ところが、
従来より周知の通り、高速スイッチング性と高耐圧性と
は相反の関係にあり、したがって、高速化を図れば耐圧
を犠牲にせさ゛るを得ない事情があった。In power devices, bipolar power transistors are generally superior in manufacturing technology compared to MOS FET power transistors, even though they have inferior high-speed switching characteristics, as is well known. It is suitable for mass production and is inexpensive. Therefore, power semiconductor devices having a bipolar power transistor structure are still being used in switching power supplies and the like. However, due to the current need for smaller and lighter switching power supplies, etc., the switching speed of semiconductor devices has been reduced to several hundred KHz.
There is a need to make things extremely fast. However,
As is well known in the past, high-speed switching performance and high voltage resistance are in a contradictory relationship, and therefore, in order to increase the speed, it is unavoidable to sacrifice voltage resistance.
が、現在では、その相反もエミッタパターンの設計によ
りかなり改善されるに至っている。すなわチ、エミッタ
パターンを櫛形状に設定することにより、ベース領域中
のエミッタ直下部分の横方向抵抗の影響で、エミッタ直
下部分とその他の部分で、パワートランジスタ動作中に
電位差が生じて、特にスイッチングOFF時に、エミッ
タ中央Wlt &c電Mr、が集中してしまい、エミッ
タ有効m1偵か減少し、結局スイッチング降F時間を速
められなかった点が改@をれ又きた。また櫛形エミッタ
とするエミツク周囲長とエミッタ面積の比 E/A、が
人となり、いわゆる安全動作領域も増し、二次1伶伏q
盲慴も良好となり耐圧向上が図れる点でも好都合である
。However, this conflict has now been considerably improved through the design of emitter patterns. In other words, by setting the emitter pattern in a comb shape, due to the influence of the lateral resistance of the part directly below the emitter in the base region, a potential difference is generated between the part directly below the emitter and other parts during power transistor operation, and When the switching is OFF, the emitter central Wlt & c electric currents concentrate, the emitter effective m1 decreases, and the switching down F time cannot be sped up after all. In addition, when using a comb-shaped emitter, the ratio of the emitter perimeter to the emitter area (E/A) increases, the so-called safe operating area increases, and the secondary
It is also advantageous in that blindness is also good and pressure resistance can be improved.
しかし先ホした通り、超晶速化を図る一1ニーAは、補
形エミッタでは、エミッタよりベースへのキャリアの注
入が困難きなり、限界が生している。その原因としては
、if!II杉エミッタの歯部の幅寸法か十分に選定で
きないことなとが考えられているが、有効な解決手段が
採られていない。However, as mentioned above, in order to increase the supercrystalline speed, it is difficult to inject carriers into the base rather than the emitter with a complementary emitter, and there is a limit to this. The reason is if! It is thought that the width dimension of the teeth of the II cedar emitter cannot be selected sufficiently, but no effective solution has been taken.
この発明は、上記の問題に鑑み提唱されたもので、パワ
ートランジスタ構造におけるエミッタパターン及びベー
スパターンヲ櫛形とぜず、エミッタパターンを多角形に
区画形成して、ベースパターンもエミッタパターンとほ
ぼ相似形の多角影VC設足し、エミッタパターン」二に
規則的に格子点状4C設けることを特徴としている。し
たがって、この発明は、スイッチング動作の高速化は勿
繻、耐圧特性を含めた安全動作領域の点でも従来の櫛形
エミッタのものよりも一段と優れており、製造上の股甜
変更も容易となる長所がある。This invention was proposed in view of the above problem, and the emitter pattern and the base pattern in the power transistor structure are not comb-shaped, but the emitter pattern is divided into polygons, and the base pattern is also almost similar to the emitter pattern. A polygonal shadow VC is provided, and lattice points 4C are regularly provided in the emitter pattern. Therefore, the present invention is superior to conventional comb-shaped emitters not only in terms of faster switching operation but also in terms of safe operation range including withstand voltage characteristics, and has the advantage that it is easy to change the manufacturing route. There is.
第1図は、この発明の一実施例を示すバイポーラパワー
トランジスタのエミッタパターン及びベースパターンを
概念的に示L7こ平面視概略構成図である。尚この実施
例の説明に当っては、元来、スイッチング時にベース領
域中に蓄積した多数キャリアをより速く外部へ流出させ
ることが出来る型のもの、すなわちベース領域をP型と
して注入される多数キャリアを電子に設定したnprI
型トラノンスタを前提として行うが、この発明は、j京
理的に他のpnp型に適用してもよく、以下の説明から
明らかとなる。FIG. 1 is a schematic plan view showing conceptually an emitter pattern and a base pattern of a bipolar power transistor according to an embodiment of the present invention. In the explanation of this embodiment, we will use a type that allows the majority carriers accumulated in the base region to flow out more quickly during switching, that is, a type in which majority carriers are injected with the base region as P type. nprI with electron set to
Although the present invention is based on the premise of a type transonstar, the present invention may be logically applied to other pnp types, which will become clear from the following description.
さて、第1図において、l、1. は、正六角形状に
均一区画されたエミッタノぐターンで、いわば網目状の
エミッタ領域2を形作っていて、その直#i1線分境界
は多結晶化ンリコン3,3.・・ によって安定化分散
抵抗が設定されたものである。さら[4,4,・ は、
エミッタパターン1,1.・・・よりは夫々小さい相似
形のベースパターンで、規則的な格子点状に離隔され、
かつ各々のエミッタパターン中に埋め込み配設、すなわ
ち、一つ置きのエミッタパターン1中に一個一個囲繞配
置されたものである。以上のパターン概念に基いて、バ
イポーラパワートランジスタの断mi構造を示したもの
が第2図で、第1図におけるA−A線部分で切断した断
面について設計したものである。第2図において、5は
N−形コレクタ領域、6&″iP形ヘース領域、7は1
形エミッタ領域で、第1図のA−A線17J断箇所に相
当する正六角形区画Bは破線8.8間で示されている。Now, in FIG. 1, l, 1. are emitter grooves uniformly partitioned into a regular hexagonal shape, forming a so-called mesh-like emitter region 2, whose direct #i1 line segment boundaries are polycrystalline silicon 3, 3 . The stabilized distributed resistance is set by... Sara [4,4,・ is,
Emitter pattern 1, 1. ...is a base pattern of similar shapes, each smaller than the other, spaced apart in the form of regular lattice points,
In addition, they are embedded in each emitter pattern, that is, they are surrounded by every other emitter pattern 1. Based on the above pattern concept, FIG. 2 shows the cross-sectional mi structure of a bipolar power transistor, which is designed with respect to the cross section taken along line A--A in FIG. 1. In FIG. 2, 5 is an N-type collector region, 6 is an iP-type heath region, and 7 is 1
In the shaped emitter region, a regular hexagonal section B corresponding to the cut point 17J on line AA in FIG. 1 is shown between dashed lines 8.8.
さらに9はエミッタ及びベース領域形成表1fIを保論
する5102膜、10はS i 、111.等の絶縁膜
である。ざて、11は正六角形区画Bの中央部に位11
するベースパターン4々P″−形のへ一スコンタクト1
2を介して接続したA見のベース電極、そして13は、
正六角形区画B内の周辺部上に、多結晶化シリコンを介
在させて設けたA見のエミッタ面積である。Furthermore, 9 is a 5102 film that holds the emitter and base region formation table 1fI, 10 is S i , 111 . It is an insulating film such as 11 is located in the center of the regular hexagonal section B.
Base pattern 4 P″-shaped bottom contacts 1
A base electrode connected through 2, and 13,
This is the area of the emitter in view A, which is provided on the periphery of regular hexagonal section B with polycrystalline silicon interposed therebetween.
上記構成としたバイポーラパワートランジスタのスイッ
チング動作においては、従来のOF F 時に生してい
たエミッタ有効面積の減少は、次の通り完全に駆逐でき
る。すなわち、第3図に示すようにベース電極11とエ
ミッタ電4傘13とを零又は遊バイアスとした時には、
電源14はエミッタパターン1の中央部直下へ集中しよ
うとするが、中央部はベースパターン4が仕りエミッタ
領域は形成されていないので、結局電流14はベースパ
ターン4の小六角形周縁に環状に流れ、集中電流密度が
減しられ、第1図におけるエミッタ領域2に関しては、
はぼ電流均一分散と見すことができ、エミッタ有効面積
が損われないのである。しかもこのパワートランジスタ
は、ベース領域6での電流集中緩和とともに、−一−ス
パターン4と接するエミッタパターン1は多角杉状に設
定されるから、エミッタ周囲長が大きく、安全動作領域
が犬になるばかりか、ベースパターン4が規則的格子点
状で、従来の櫛形パターンよりも著しく電流均一分散が
行え、二次降伏現象を招く危険性が減少する。In the switching operation of the bipolar power transistor configured as described above, the reduction in the effective emitter area that occurs during the conventional OFF time can be completely eliminated as follows. That is, when the base electrode 11 and the emitter capacitor 13 are set to zero or free bias as shown in FIG.
The power source 14 tries to concentrate directly under the center of the emitter pattern 1, but since the center is covered by the base pattern 4 and no emitter region is formed, the current 14 ends up flowing in a ring around the small hexagonal periphery of the base pattern 4. , the concentrated current density is reduced and for emitter region 2 in FIG.
This can be regarded as a uniform distribution of current, and the effective area of the emitter is not impaired. Moreover, in this power transistor, in addition to alleviating current concentration in the base region 6, the emitter pattern 1 in contact with the -base pattern 4 is set in a polygonal cedar shape, so the emitter circumference is large and the safe operation area becomes a dog. Moreover, since the base pattern 4 has a regular lattice shape, the current can be distributed more uniformly than in the conventional comb-shaped pattern, and the risk of secondary breakdown phenomenon is reduced.
第1図は、この発明の一実施例を示す電力用半導体装置
のエミッタパターン及びベースパターンの構成を示す平
面視概念図、第2図は、そのA−A線で切断したと想定
した電力用半導体装置の要部断面図、第3図はその逆バ
イアススイッチング時の同様な断面図である。
1・ エミッタパターン、
4・・・ ベースパターン、
6・・・・ ベース領域、
7・・−・ エミッタ領域。FIG. 1 is a conceptual plan view showing the structure of an emitter pattern and a base pattern of a power semiconductor device showing one embodiment of the present invention, and FIG. 2 is a power semiconductor device assumed to be cut along line A-A. FIG. 3 is a cross-sectional view of the main part of the semiconductor device, and a similar cross-sectional view during reverse bias switching. 1. Emitter pattern, 4... Base pattern, 6... Base area, 7... Emitter area.
Claims (1)
する半導体装置において、多角形に区画形成したエミッ
タパターンと、上記エミッタパターンとほぼ相似形の多
角形状ベースパターンを規則的格子点状に設けたことを
特徴上する電力用半導体装置。In a semiconductor device in which at least an emitter region and a base region are formed from the same surface, an emitter pattern formed into polygonal sections and a polygonal base pattern substantially similar to the emitter pattern are provided in the form of regular lattice points. A power semiconductor device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17165682A JPS5961178A (en) | 1982-09-30 | 1982-09-30 | Semiconductor device for power |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17165682A JPS5961178A (en) | 1982-09-30 | 1982-09-30 | Semiconductor device for power |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5961178A true JPS5961178A (en) | 1984-04-07 |
JPH0460339B2 JPH0460339B2 (en) | 1992-09-25 |
Family
ID=15927255
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17165682A Granted JPS5961178A (en) | 1982-09-30 | 1982-09-30 | Semiconductor device for power |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5961178A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01262665A (en) * | 1988-04-13 | 1989-10-19 | Mitsubishi Electric Corp | Semiconductor device for power |
DE102005046738A1 (en) * | 2005-09-29 | 2007-03-22 | Infineon Technologies Ag | Bipolar transistor with protection against electrical overloading by transients or peaks, includes emitter structure comprised of two distinct layers |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5043885A (en) * | 1973-08-20 | 1975-04-19 | ||
JPS53103668U (en) * | 1977-01-24 | 1978-08-21 | ||
JPS5691468A (en) * | 1979-12-25 | 1981-07-24 | Nec Corp | Semiconductor |
-
1982
- 1982-09-30 JP JP17165682A patent/JPS5961178A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5043885A (en) * | 1973-08-20 | 1975-04-19 | ||
JPS53103668U (en) * | 1977-01-24 | 1978-08-21 | ||
JPS5691468A (en) * | 1979-12-25 | 1981-07-24 | Nec Corp | Semiconductor |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01262665A (en) * | 1988-04-13 | 1989-10-19 | Mitsubishi Electric Corp | Semiconductor device for power |
DE102005046738A1 (en) * | 2005-09-29 | 2007-03-22 | Infineon Technologies Ag | Bipolar transistor with protection against electrical overloading by transients or peaks, includes emitter structure comprised of two distinct layers |
Also Published As
Publication number | Publication date |
---|---|
JPH0460339B2 (en) | 1992-09-25 |
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