JPS5961178A - Semiconductor device for power - Google Patents

Abstract

PURPOSE:To accelerate a switching rate by partitioning and forming an emitter pattern into polygons, also setting a base pattern to polygons of approximately similar figures to the emitter pattern and regularly forming the polygons on the emitter pattern to a lattice point shape. CONSTITUTION:The emitter patterns 1... uniformly partitioned to a regular hexagonal shape form reticulate emitter regions 2, and stabilized dispersion resistors are set by polycrystallized silicon 3 in the straight-line segment boundaries. The base patterns 4... of similar figures each smaller than the emitter patterns 1... are isolated in the regular lattice point shape, and buried and disposed in each emitter pattern-that is, they are surrounded and arranged one by one in every other emitter pattern 1. When a base electrode 11 and emitter electrodes 13 are brought to zero or reverse bias, currents 14 annularly flow through the fringes of the small hexagons of the base patterns 4, concentrated current density is reduced, the dispersion of currents can be regarded as approximately uniform regarding the emitter regions 2, and the effective areas of emitters are not damaged. Not only the peripheral length of the emitters is large and stable operating regions enlarge because the emitter patterns 1 being in contact with the base patterns 4 are set to a polygonal shape but also currents are dispersed uniformly because the base patterns 4 take the regular lattice point shape, and there is hardly a possibility resulting in a secondary breakdown phenomenon.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Section Af) This invention relates to improving the high-speed switching characteristics of a power semiconductor device having a bipolar power transistor structure.

[Technical countermeasure]

In power devices, bipolar power transistors are generally superior in manufacturing technology compared to MOS FET power transistors, even though they have inferior high-speed switching characteristics, as is well known. It is suitable for mass production and is inexpensive. Therefore, power semiconductor devices having a bipolar power transistor structure are still being used in switching power supplies and the like. However, due to the current need for smaller and lighter switching power supplies, etc., the switching speed of semiconductor devices has been reduced to several hundred KHz.
There is a need to make things extremely fast. However,
As is well known in the past, high-speed switching performance and high voltage resistance are in a contradictory relationship, and therefore, in order to increase the speed, it is unavoidable to sacrifice voltage resistance.

However, this conflict has now been considerably improved through the design of emitter patterns. In other words, by setting the emitter pattern in a comb shape, due to the influence of the lateral resistance of the part directly below the emitter in the base region, a potential difference is generated between the part directly below the emitter and other parts during power transistor operation, and When the switching is OFF, the emitter central Wlt & c electric currents concentrate, the emitter effective m1 decreases, and the switching down F time cannot be sped up after all. In addition, when using a comb-shaped emitter, the ratio of the emitter perimeter to the emitter area (E/A) increases, the so-called safe operating area increases, and the secondary
It is also advantageous in that blindness is also good and pressure resistance can be improved.

However, as mentioned above, in order to increase the supercrystalline speed, it is difficult to inject carriers into the base rather than the emitter with a complementary emitter, and there is a limit to this. The reason is if! It is thought that the width dimension of the teeth of the II cedar emitter cannot be selected sufficiently, but no effective solution has been taken.

[Disclosure of the invention]

This invention was proposed in view of the above problem, and the emitter pattern and the base pattern in the power transistor structure are not comb-shaped, but the emitter pattern is divided into polygons, and the base pattern is also almost similar to the emitter pattern. A polygonal shadow VC is provided, and lattice points 4C are regularly provided in the emitter pattern. Therefore, the present invention is superior to conventional comb-shaped emitters not only in terms of faster switching operation but also in terms of safe operation range including withstand voltage characteristics, and has the advantage that it is easy to change the manufacturing route. There is.

[Best mode for carrying out the invention]

FIG. 1 is a schematic plan view showing conceptually an emitter pattern and a base pattern of a bipolar power transistor according to an embodiment of the present invention. In the explanation of this embodiment, we will use a type that allows the majority carriers accumulated in the base region to flow out more quickly during switching, that is, a type in which majority carriers are injected with the base region as P type. nprI with electron set to
Although the present invention is based on the premise of a type transonstar, the present invention may be logically applied to other pnp types, which will become clear from the following description.

Now, in FIG. 1, l, 1. are emitter grooves uniformly partitioned into a regular hexagonal shape, forming a so-called mesh-like emitter region 2, whose direct #i1 line segment boundaries are polycrystalline silicon 3, 3 . The stabilized distributed resistance is set by... Sara [4,4,・ is,
Emitter pattern 1, 1. ...is a base pattern of similar shapes, each smaller than the other, spaced apart in the form of regular lattice points,
In addition, they are embedded in each emitter pattern, that is, they are surrounded by every other emitter pattern 1. Based on the above pattern concept, FIG. 2 shows the cross-sectional mi structure of a bipolar power transistor, which is designed with respect to the cross section taken along line A--A in FIG. 1. In FIG. 2, 5 is an N-type collector region, 6 is an iP-type heath region, and 7 is 1
In the shaped emitter region, a regular hexagonal section B corresponding to the cut point 17J on line AA in FIG. 1 is shown between dashed lines 8.8.

Furthermore, 9 is a 5102 film that holds the emitter and base region formation table 1fI, 10 is S i , 111 . It is an insulating film such as 11 is located in the center of the regular hexagonal section B.
Base pattern 4 P″-shaped bottom contacts 1
A base electrode connected through 2, and 13,
This is the area of the emitter in view A, which is provided on the periphery of regular hexagonal section B with polycrystalline silicon interposed therebetween.

In the switching operation of the bipolar power transistor configured as described above, the reduction in the effective emitter area that occurs during the conventional OFF time can be completely eliminated as follows. That is, when the base electrode 11 and the emitter capacitor 13 are set to zero or free bias as shown in FIG.
The power source 14 tries to concentrate directly under the center of the emitter pattern 1, but since the center is covered by the base pattern 4 and no emitter region is formed, the current 14 ends up flowing in a ring around the small hexagonal periphery of the base pattern 4. , the concentrated current density is reduced and for emitter region 2 in FIG.
This can be regarded as a uniform distribution of current, and the effective area of the emitter is not impaired. Moreover, in this power transistor, in addition to alleviating current concentration in the base region 6, the emitter pattern 1 in contact with the -base pattern 4 is set in a polygonal cedar shape, so the emitter circumference is large and the safe operation area becomes a dog. Moreover, since the base pattern 4 has a regular lattice shape, the current can be distributed more uniformly than in the conventional comb-shaped pattern, and the risk of secondary breakdown phenomenon is reduced.

[Brief explanation of the drawing]

FIG. 1 is a conceptual plan view showing the structure of an emitter pattern and a base pattern of a power semiconductor device showing one embodiment of the present invention, and FIG. 2 is a power semiconductor device assumed to be cut along line A-A. FIG. 3 is a cross-sectional view of the main part of the semiconductor device, and a similar cross-sectional view during reverse bias switching. 1. Emitter pattern, 4... Base pattern, 6... Base area, 7... Emitter area.

Claims (1)

[Claims] In a semiconductor device in which at least an emitter region and a base region are formed from the same surface, an emitter pattern formed into polygonal sections and a polygonal base pattern substantially similar to the emitter pattern are provided in the form of regular lattice points. A power semiconductor device characterized by: