JPS5960709U - Erasing circuit of tape recorder - Google Patents
Erasing circuit of tape recorderInfo
- Publication number
- JPS5960709U JPS5960709U JP15536782U JP15536782U JPS5960709U JP S5960709 U JPS5960709 U JP S5960709U JP 15536782 U JP15536782 U JP 15536782U JP 15536782 U JP15536782 U JP 15536782U JP S5960709 U JPS5960709 U JP S5960709U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- terminal
- supplied
- erasing
- erase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案になるテープレコーダの消去回路の一実施例
を示す回路図である。
１・・・ＡＣ消去制御端子、２・・・ＤＣ消去制御端子
、３・・・消去ヘッド、Ｔｒｌ、Ｔｒ２・・・スイッチ
ングトランジスタ、Ｔｒ３・・・発振トランジスタ、Ｒ
１，Ｒ２，Ｒ３・・・抵抗、Ｒ４・・・正帰還抵抗、Ｒ
６・・・ＤＣ消去電流調整用抵抗、Ｃ１・・・発振同調
コンデンサ、Ｃ２・・・消去ノイス防止コンデンサ、Ｔ
・・・トランス、Ｌｌ・・・トランスＴの１次側のコイ
ル（発振用コイル）、Ｌ２・・・トランスＴの２次側の
コイル、Ｐ・・・中間端子。The figure is a circuit diagram showing an embodiment of the erasing circuit of the tape recorder according to the present invention. 1... AC erase control terminal, 2... DC erase control terminal, 3... erase head, Trl, Tr2... switching transistor, Tr3... oscillation transistor, R
1, R2, R3...Resistance, R4...Positive feedback resistance, R
6... DC erase current adjustment resistor, C1... Oscillation tuning capacitor, C2... Erasing noise prevention capacitor, T
...transformer, Ll...primary side coil (oscillation coil) of transformer T, L2...secondary side coil of transformer T, P...intermediate terminal.
Claims (1)
れ、該第１のトランジスタのエミッタはトランスの１次
側の中間端子に接続され、該トランスの１次側の一方の
端子は抵抗を介して第２のトランジスタのベースに接続
され、他方の端子は該第２のトランジスタのコレクタに
接続され、二゛ の１次側の両方の端子は第１のコン
デンサを介して互いに接続され、該第２のトランジスタ
のエミ−ツタは接地され、第２の制御端子は第３のトラ
ンジスタのベースに接続され、該第３のトランジスタの
エミッタは前記トランスの２次側の一方の端子に接続さ
れると共に第２のコンデンサを介して′ 接地され、該
トランスの２次側の他方の端子は消去ヘッドに接続され
、前記第１、第２のトランジスタのコレクタはそれぞれ
電源に接続されるよう構成し、前記第１の制御端子より
信号が供給されると前記第１のトランジスタが導通ずる
ことによって、前記消去ヘッドにＡＣ消去電流が供給さ
れ、前記第２の入力制御端子より信号が供給されると、
前記第２のトランジスタが導通することによって、前記
消去ヘッドにＤＣ消去電流が供給され、前記第１、第２
の制御端子に供給する信号を切換えることによって、前
記消去ヘッドに供給されるＡＣ消去電流とＤＣ消去電流
とを切換える♀とを特徴とするテープレコーダの消去回
路。The first control terminal is connected to the base of the first transistor, the emitter of the first transistor is connected to the intermediate terminal of the primary side of the transformer, and one terminal of the primary side of the transformer is connected to the base of the first transistor. and the other terminal is connected to the collector of the second transistor, both terminals of the two primary sides are connected to each other via the first capacitor, and the other terminal is connected to the collector of the second transistor. The emitter of the second transistor is grounded, the second control terminal is connected to the base of the third transistor, and the emitter of the third transistor is connected to one terminal of the secondary side of the transformer. grounded via a second capacitor, the other terminal of the secondary side of the transformer is connected to the erasing head, the collectors of the first and second transistors are respectively connected to a power supply, and the When a signal is supplied from the first control terminal, the first transistor becomes conductive, thereby supplying an AC erase current to the erase head, and when a signal is supplied from the second input control terminal,
When the second transistor becomes conductive, a DC erase current is supplied to the erase head, and the DC erase current is supplied to the erase head.
An erasing circuit for a tape recorder, characterized in that an AC erasing current and a DC erasing current supplied to the erasing head are switched by switching a signal supplied to a control terminal of the tape recorder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15536782U JPS5960709U (en) | 1982-10-14 | 1982-10-14 | Erasing circuit of tape recorder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15536782U JPS5960709U (en) | 1982-10-14 | 1982-10-14 | Erasing circuit of tape recorder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5960709U true JPS5960709U (en) | 1984-04-20 |
| JPH0430642Y2 JPH0430642Y2 (en) | 1992-07-23 |
Family
ID=30343165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15536782U Granted JPS5960709U (en) | 1982-10-14 | 1982-10-14 | Erasing circuit of tape recorder |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5960709U (en) |
-
1982
- 1982-10-14 JP JP15536782U patent/JPS5960709U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0430642Y2 (en) | 1992-07-23 |
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