JPS595976Y2 - リ−ドフレ−ムオサエソウチ - Google Patents

リ−ドフレ−ムオサエソウチ

Info

Publication number
JPS595976Y2
JPS595976Y2 JP1975175190U JP17519075U JPS595976Y2 JP S595976 Y2 JPS595976 Y2 JP S595976Y2 JP 1975175190 U JP1975175190 U JP 1975175190U JP 17519075 U JP17519075 U JP 17519075U JP S595976 Y2 JPS595976 Y2 JP S595976Y2
Authority
JP
Japan
Prior art keywords
lead
lead frame
holding
leads
osae
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1975175190U
Other languages
English (en)
Japanese (ja)
Other versions
JPS5288970U (enrdf_load_stackoverflow
Inventor
博 丑木
Original Assignee
株式会社新川製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社新川製作所 filed Critical 株式会社新川製作所
Priority to JP1975175190U priority Critical patent/JPS595976Y2/ja
Publication of JPS5288970U publication Critical patent/JPS5288970U/ja
Application granted granted Critical
Publication of JPS595976Y2 publication Critical patent/JPS595976Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
JP1975175190U 1975-12-26 1975-12-26 リ−ドフレ−ムオサエソウチ Expired JPS595976Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1975175190U JPS595976Y2 (ja) 1975-12-26 1975-12-26 リ−ドフレ−ムオサエソウチ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1975175190U JPS595976Y2 (ja) 1975-12-26 1975-12-26 リ−ドフレ−ムオサエソウチ

Publications (2)

Publication Number Publication Date
JPS5288970U JPS5288970U (enrdf_load_stackoverflow) 1977-07-02
JPS595976Y2 true JPS595976Y2 (ja) 1984-02-23

Family

ID=28653538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1975175190U Expired JPS595976Y2 (ja) 1975-12-26 1975-12-26 リ−ドフレ−ムオサエソウチ

Country Status (1)

Country Link
JP (1) JPS595976Y2 (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6233432A (ja) * 1985-08-06 1987-02-13 Mitsubishi Electric Corp リ−ドフレ−ム押圧器

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5144864B2 (enrdf_load_stackoverflow) * 1972-05-10 1976-12-01

Also Published As

Publication number Publication date
JPS5288970U (enrdf_load_stackoverflow) 1977-07-02

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