JPS5957575A - Picture signal corrector - Google Patents

Abstract

PURPOSE:To obtain a resolution equal to that of an A/D converting circuit, by performing A/D conversion at an upper limit reference voltage and a lower limit voltage based on a correcting value corresponding to white and black density areas designated on an original picture. CONSTITUTION:A scanning circuit 7 scans a reference white plate ahead the scanning of the original picture, then scans a black density area and obtained white and black reference signals are stored respectively in storage circuits 9, 10. On the other hand, extraction circuits 1, 2 extract respectively white and black data signals of plural picture elements and give them to a mean value circuit 3. The circuit 10 obtains each mean value from the white and black data signals and outputs the white reference signal H and the black reference signal M. A white level tracking circuit 4 and a black level tracing circuit 5 calculate respectively the white reference signal Bb and the black reference signal Bd from the circuits 9, 10 and the upper limit reference voltage VH and the lower limit reference voltage VL from the signal H or M. The A/D conversion circuit 6 takes the volages VH and VL as the upper and the lower limit volage and the A/D conversion is attained with a discriminating level splitting the voltage between them.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an image signal correction device, and more particularly to an image signal correction device for white density and black density regions in an optical reading device for recorded information having halftones.

[Technological environment]

An optical reading device for recorded information that has halftones scans a continuous tone photographic original using a laser beam, converts the reflected light from the original into a photoelectric converter, and converts the white of the original into a high-voltage, black one. A low-voltage image signal is obtained.

In this case, the envelope of the image signal for each scanning line for white is a so-called naging phenomenon.

Further, the dark current of the photoelectric conversion element changes depending on temperature, driving voltage, and aging, and the change in the dark current changes the black voltage region.

Furthermore, some original images have a narrow black-and-white density change range, and others have poor density on the original mount, but in the photoelectric conversion process, all of these are converted into image signals with voltages corresponding to the density. Image signals are digitally converted to facilitate signal processing, but in this conversion process, it is necessary to remove the effects of shading and dark current mentioned above, as well as correct the density range relative to the black and white of the original image, in order to achieve high-quality image reproduction. desirable for

[Prior art]

In a conventional image signal correction device, an upper limit reference voltage and a lower limit reference voltage are fixed to set values in an analog-to-digital conversion circuit that converts an analog signal read by scanning into a digital code, and the upper limit reference voltage and lower limit reference voltage are The analog image signal supplied thereto is divided into y-level judgment levels, and the supplied analog image signal is converted into a digital code corresponding to the judgment level.

Therefore, if the highest voltage for white of the analog image signal is lower than the upper limit reference voltage, or if the lowest voltage for black is lower than the lower limit reference voltage, the y-step resolution of the analog-to-digital conversion circuit cannot be obtained.

Next, the digitally encoded image signal is subjected to necessary correction using digital correction values based on the respective image signal correction elements described above. However, when the analog-to-digital conversion is not resolved into y-step sizes, the resolution cannot be improved by correction.

That is, although the conventional image signal correction apparatus incorporates a high-precision analog-to-digital conversion circuit, it has the disadvantage that it can only output an image with a lower level resolution than the resolution it has.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an image signal modification device that can obtain a resolution equal to that of an analog-to-digital conversion circuit.

[Structure of the invention]

The image signal correction device of the present invention includes a first extraction circuit that extracts all white data signals of a plurality of pixels obtained by scanning a specified white area of an original image, and a first extraction circuit that scans a specified black density area of the original image. a second extraction circuit for extracting black data signals of a plurality of pixels obtained by the above-mentioned processing; Calculate the upper limit reference voltage based on the white reference signal corresponding to one scanning line obtained by scanning the value circuit and the reference white grade, the black reference signal corresponding to the photoelectric conversion element output voltage at zero incident light, and the white correction signal. a white level tracking circuit that calculates a lower limit reference voltage and voltage based on the white reference signal, the black reference signal, and the black correction signal; It is configured to include an analog-to-digital conversion circuit in which the determination level between the upper and lower limit voltages is controlled and which decomposes an image signal obtained by photoelectrically converting the gradation information recorded on the original image according to the determination level.

[Explanation of Examples]

Below, 7A of the present invention! A? II will be explained in detail with reference to Figure E Shinkin Bank.

FIG. 1 is a block diagram showing one embodiment of the present invention, and the image signal correction device shown in FIG. 1 includes extraction circuits 1 and 2, an average value circuit 3, a mill level tracking circuit 4, and a black level tracking circuit 5 and
It is configured to include an analog-to-digital conversion circuit 6.

Below, the operation of the image signal correction device shown in FIG. 1 will be explained in detail with reference to FIGS. 2 to 9.

2 is a detailed block diagram of the extraction circuit l in the embodiment shown in FIG. 1, FIG. 3 is a detailed block diagram of the average value circuit 3 in the embodiment shown in FIG. 1, and FIG. 4 is shown in FIG. FIG. 5 is a detailed block diagram of the white level tracking circuit in the embodiment shown in FIG. 1, FIG. 6 is a detailed block diagram of the black level tracking circuit in the embodiment shown in FIG. 7 is an explanatory diagram of the image signal extraction operation of the extraction circuit 1 shown in FIG. 2, and FIG. 8 is a time chart for explanation.
FIG. 9 is an apparent waveform diagram for explaining the operation of the embodiment shown in FIG. 1. FIG.

[Operation for setting upper limit voltage and lower limit voltage] In the preparation period prior to the start of scanning an original image, the main scanning start enable signal is set to "low" in FIG. 1. The main scanning start enable signal is supplied to a white level tracking circuit 4, and the inverted main scanning start enable signal π whose phase is inverted by an inverter 15 is supplied to a black level tracking circuit 5.

The NAND circuit 408 shown in FIG. 4 is supplied with 10-bit data input and a "low" scan start enable signal I (2). -I 10-bit data is output.

The latch 409 is a 1-pit delay circuit for bit alignment, and the output from the latch 409 is converted to an analog voltage amount by a digital-to-analog conversion circuit 410, and then passed through a low-pass filter 41.
1, the indestructible frequency component is removed and output as the upper limit reference voltage VH.

The value of the upper limit reference voltage ■□ at this time is 1 as shown in FIG.
If all 0-bit digital codes correspond to "...I", V+' port t-K is 9, which is the lower limit voltage of the analog-to-digital conversion circuit 6.

On the other hand, the negative sum circuit 504 shown in FIG. data is output. All ``low'' 1
The 0-bit data is bit-aligned by the latch 505, and the digital-to-analog conversion circuit 506 converts the analog voltage amount to:
After converting into , it is outputted as lower limit reference voltage ■1 through a low-pass filter 507.

The value of the lower limit reference voltage vL at this time is 10 as shown in FIG.
All bit digital codes correspond to “low”
(2)-'' volts, and this voltage value is the lower limit voltage of the analog-to-digital conversion circuit 6.

[White reference signal and black reference signal generation operation 3rd, 1st
In the figure, the scanning circuit 7 scans the reference white plate prior to scanning the original image, and supplies the white reference signal Ab in the photoelectric conversion signal A shown in FIG. 8 to the analog-to-digital conversion circuit #66. Scanning is performed in synchronization with the synchronization clock S2 from the synchronization clock generation circuit 16, and the constant period T shown in FIG. 8 is set to a predetermined value.

The analog-to-digital conversion circuit 6 has an upper limit reference voltage ■□ and a lower limit reference voltage ■ as upper and lower limit voltages, respectively, and has judgment levels divided into 256 levels between them,
It has the function of converting analog input voltage into 8-bit digital code according to its determination level.

The analog-to-digital conversion circuit 6 has an upper limit reference voltage VH.
The white reference signal A is converted into an 8-bit digital white reference signal Bb in the digitally encoded signal B by setting the lower limit reference voltage vL to "V+" volts and the lower limit reference voltage vL to "V-" volts.The digital white reference signal B is the bus switching gate. One scanning line is stored in the memory circuit 9 via the process 8.

After scanning the reference white plate, as a reference point, the output voltage from the photoelectric conversion element when the light source is turned off, that is, when the incident light to the photoelectric conversion element is zero, is obtained as the black reference signal Ad in the optical 11° conversion signal A shown in FIG. , the 8-bit digital black reference signal Bd in the digital encoded signal B is stored in the storage circuit 10 through the same process as above.

Next, for convenience of explanation, the operations of the extraction circuits 1 and 2 and the average value circuit 3 for obtaining the white correction signal H and the point correction signal M will be explained before explaining the white level tracking circuit 4 and the black level tracking circuit 5.
We will describe the operation of.

The white level tracking circuit 4 and the black level tracking circuit 5 are based on the digital white reference signal Bb, the digital black reference signal Bd, the white correction signal H, and the point correction signal M, as shown in the following equations (1) and (2). Digital conversion circuit 6
The upper limit reference voltage vH and lower limit reference voltage ■1 are calculated.

VH=B, +(Bb-B,)H・・・・・・・・・・・・
...(1)■L=Bd+(Bb-Bd)M...
(2) [Operation of white level tracking circuit] As shown in FIG. 4, the white level tracking circuit 4 includes an inverter 4
01,403 and 406. Addition circuit 402゜407,
AND circuit 4042 multiplication circuit 405. Negative product circuit 408
．． Latch 409. It includes a digital-to-analog conversion circuit 410 and a low-pass filter 411 and calculates an upper limit reference voltage VH.

In FIG. 1, the digital white reference signal Bb stored in the storage circuit 9 and the digital black reference signal Bd stored in the storage circuit 10 are phase pulses C generated every scanning period T from the scanning circuit 7. The pixel is activated and read out using the read address generated by the pixel clock Sl from the synchronous clock generation circuit 16.

In FIG. 4, the digital white reference signal Bb and the inverter 4
The inverted digital black reference signal 01 is supplied to the adder circuit 402.

The adder circuit 402 adds "1" to the lowest pit of the inverted black reference signal Bd to add the complement of the digital black reference signal Bd and the digital white reference signal Bb. "High" as signal E from Co
is output, and when there is no carry, outputs "low".

Therefore, in the AND circuit 404, the carry signal E is "high".
When , a logic result is taken and an 8-pit white circuit signal F is output. This operation performs subtraction (Bb-Bd
) is obtained.

The multiplication circuit 405 multiplies the 8-bit white line signal F by the 10-bit white correction signal H, and the upper 10 bits of the 18-bit data of the multiplication result are inverted and phase-inverted by the inverter 406 as data. It is taken in at the rising edge of the pixel clock coffin, and is latched and taken out at the rising edge of the pixel clock 81. This result [(B.

-B d) xH) is calculated.

However, at this point, the white data signal from the extraction circuit 1 shown in FIG. 1 obtained by scanning the designated white density area of the original image is not generated, and the storage circuit in the average value circuit 3 shown in FIG. The white correction signal H1oO in the 10-bit white correction signal H of all “1” representing 100% reflectance stored in advance in the multiplication circuit 404 (see FIG. 3) is applied to the multiplier circuit 405.
supplied to Therefore, ((Bb-Bd)X'H) is equivalent to (Bb-Bd).

Next, the 10-bit data output from the multiplication circuit 405 and the digital black reference signal B are incremented by the addition circuit 407, and the addition result is supplied to the NAND circuit 408. The above process completes the calculation of equation 1), but in the case of the white correction signal H100, vH=Bb.

When the main scanning start enable signal K becomes "high", the NAND circuit 408 takes a negative result, outputs 10-bit digital code data corresponding to the upper limit reference voltage v1 (and supplies it to the latch 409. The operations of the digital-to-analog conversion circuit 410 and the low-pass filter 411 have been described above, so they will not be repeated here.
□ is generated and supplied to the analog-to-digital conversion circuit 6 through 411 low-pass filters.

Therefore, the upper limit reference voltage ■H in the case of the white correction signal Htoo
becomes the “Ab” hole shown in FIG.

[Operation of black level tracking circuit]

Next, the black level tracking circuit 5 shown in FIG.
11 inverter 502. Addition circuit 503. Negative sum circuit 504
．． It is equipped with a digital-to-analog conversion circuit 506 and a low-pass filter 507, and converts the white envelope thin signal F from the white level tracking circuit 4, the black reference signal Bdl, and the low point correction signal M to the lower limit reference voltage vL'lr: calculate.

The operations of the multiplier circuit 501 and the adder circuit 503 are similar to those of the multiplier circuit 405 and the adder circuit 407 of the white level tracking circuit 4 described above, except that the point correction signal M is used as a substitute for the white correction No. 48H. , (2) is calculated.

However, at this point, the black data signal N from the extraction circuit 2 shown in FIG. 1 obtained by scanning the designated blackness area of the original image is not generated, and the average value circuit shown in FIG. 3. A 10-bit point correction signal M representing all zero reflections stored in advance in the storage circuit 305 (see FIG. 3) in FIG.
The unsophisticated signal M in is supplied to the multiplication circuit 501. Therefore, when [(Bb Bd) XMJ in equation (2), VL=Bd is obtained.

The 10-bit digital note month take from the adder circuit 503 is supplied to the N/A circuit 504. When the main scanning start enable signal K is set to "high", the inverted main scanning start enable signal becomes "low", and the negative square sum circuit 504 calculates the sum of negative sums, which corresponds to the lower limit reference voltage VLK. After the bit digital code data is bit-aligned by a latch 505, it is supplied to a digital-to-analog conversion circuit 506.

The digital-to-analog conversion circuit 506 generates a lower limit reference voltage converted into an analog voltage corresponding to the 10-bit digital code data, and uses a low-pass filter 507 to convert the analog-to-digital conversion circuit 6 shown in FIG. supply to.

Therefore, the lower limit reference voltage VL in the case of Masahaku Kurogami M0 becomes "Ad" volts shown in FIG.

[Operation of extraction circuit] Next, in FIG. 1, the upper limit reference voltage of "Ab" volt and the unrefined signal M corresponding to Shirasode Shohaku H1oO. K
The corresponding lower limit reference voltage of "Ad"' volts is supplied to the analog-to-digital conversion circuit 6, and the original image is scanned by the scanning circuit 7.

The scanning circuit 7 outputs an image signal Aa in the photoelectric conversion signal A shown in FIG. As shown in FIG.
101 inverter 102, 103, OR circuit 105. AND circuit 109. Flip-flops 107, 108 and 111. It includes a constant product circuit 112 and a memory circuit 113, and extracts density data corresponding to a plurality of pixels from a specified whiteness area of an original image and outputs a white take signal.

Prior to scanning the original image, specify the density area on the original image that you want to make white. That is, in this example, in order to facilitate understanding,
As shown surrounded by a dashed line in FIG. 7, in the four main scanning lines starting from the first main scanning line to the n-grain main scanning line, the four main scanning lines starting at the mth main scanning line from the main scanning start point, respectively. Assume that we have specified an area that can be composed of 16 itt++ blocks each consisting of pixels.

In the following d brother, ■71 of the detailed block diagram shown in Figure 2.
The operation will be performed with reference to the time chart shown in FIG. 6 and FIG. 7.

A counter 101 is installed at (n-1), and counts (V-phase pulses C) from the time when the sub-running feces start enable No. 1B becomes "high", and counts (n-11th phase pulse At the trailing edge of the pulse, the output 1g is set to "low" and the "low J" state continues until the U-edge of the next phase pulse.

The counter 104 is set to "4", which corresponds to the number of scanning lines including the pixel to be extracted, and receives an inverted phase pulse C whose phase is inverted by the inverter 102 and a counter 101 whose phase is inverted by the inverter 103. The inverted output i = number a or the number j can be obtained.

The counter 104 divides the L phase pulse of the inverted output number i or [starts when high J is +L, 4 (1^). Therefore,
The output signal of the counter 104 becomes "low" at the Nu edge of the nth phase pulse, as shown in FIG. ! The output signal becomes "high" at the leading edge of the 11th (n+4)th phase pulse, but in Figure 1, the output signal is "low". included.

The OR circuit 105 performs an OR operation between the output No. 16 of the counter 104 and the inverted phase pulse C, and the logic is 111 times 1pr.
Four extracted ul-phase pulses d starting from n=14th from 105 are output.

Next, the counter 106 is set to (m-1), which corresponds to the number of image lines in the main scanning direction from the main scanning start point, and the i'1III search clock is activated when the extraction phase pulse d is added. counting S1, occurring at the trailing edge of the extracted phase pulse d;
A "low" extraction start position designation signal @e that disappears after counting (m-1) pieces is generated.

The input terminal DK of the flip-flop 107 is disconnected from the voltage of "10", and the extraction start point is /l of the signal e.
It is set when the output goes out, sets the child Q to high J, and is reset by the reset signal R. However, the reset signal R
is a signal that becomes "low" during a period when the image signals A and 11 are not generated in the area "T" around Ikki Kaifu.

The "high" output signal from the output terminal Q of the flip-flop 107 is supplied to the input terminal of the flip-flop 108 at the next pixel clock S! The flip-flop 108 is set at the leading edge of , a "high" extraction pixel position signal f is outputted from the output terminal Q, and it is reset at the reset No. 1d R.

Next, extract I[! II position signal f and pixel clock S1
The AND circuit 109 calculates the AND of the mth i[! from the main scanning start point. ! Reset signal R from I cumulative clock
The extraction pixel clock h until the occurrence of the extraction pixel clock h is output when the extraction start position designation signal e disappears.

The counter 110 is set to "4", which is the number of extracted pixels in the main scanning direction, and is activated when the extracted pixel position signal f becomes "high", and when the extracted pixel clock h is counted and 4 pixels are counted, "4" is set. , it outputs an output signal k that goes low at the next phase pulse, and supplies it to the clock terminal CKK of the flip-flop 111.

Flip-flop 111 has “+V” frost on the input terminal,
When the pressure is being supplied and the output signal k becomes "high", it is set and reset by the reset signal R, and the negative product circuit 112 connects the output terminal Q to the "low" extraction end position. The transmission signal W with 4 pixel clocks is
is output and instructs the storage circuit 113 to write one piece of 8-bit pixel data, each corresponding to Ichigome Hakugo W included in the digital image signal B≦.

The storage circuit 113 is composed of 16 words of 8 bits, and stores white density data of 16 pixels with 98 bits per pixel. Read concentration data and buffer 1
2, the white data signal and the white data sending signal W8 are supplied to the average value circuit 3.Next, the extraction circuit 2 specifies a density area to be made black on the original image, and corresponds to a plurality of pixels from the area. This is a circuit that extracts density data and outputs a black data signal N. The circuit configuration and operation are the same as those of extraction circuit 1 described above, except that the settings of counters 101, 104, 106, and 110 change depending on the specified area. It is.

However, the white data signal of the extraction circuit 1 described above is the black data signal N1, and the white data sending signal W is the black data sending signal W7.
, buffer 12 is read as buffer 14.

[Operation of average value circuit]

As shown in Figure 3, the average value circuit 3 includes an assisting circuit 301.
．． Register 302. Division circuit 303 and memory circuit 30
4, 305, the average value of each of the white data signal and the black data signal N is extracted, and a 10-bit white correction signal T and h correction signal M are output.

The average value circuit 3Fi extracts a "high" read request signal U from the division circuit 303 when there is no human data to be manipulated.
In this state, the white data signal of 8 pits and 16 words is supplied from the extracting circuit 1 to the 11h next adder circuit 301, so the addition circuit 301 and register 302 perform addition for each word, and when the addition of 16 words is completed, the addition result is supplied to division (b) path 303.

Further, at the same time as the above addition, the number of words added is counted, and the counted number of words is supplied to the division circuit 303.

The division circuit 303 performs division by using the supplied addition data as a dividend and the counted number of words as a divisor, and outputs only the truncated quotient in 10 bits.

Since the memory circuit 16304 is supplied with the day data sending signal W from the extraction circuit 1 to instruct the memory circuit 304 to store data, the 10-bit output data from the division circuit 303 is sent to the memory circuit 304. be remembered.

The average value of the black data signal N from the extraction circuit 2 is also calculated in the same manner as above, and the output data of the performance and results is stored in the storage circuit 305.
I remember too much. However, the extraction circuit 1 is the extraction circuit 2, the white data signal is the black data signal N1, the white data sending signal 1 W,
are read as the black data sending signal W, respectively.

The white correction number H stored in the storage circuit 304 in this manner is a 10-bit digital code of the designated white anti-JH ratio when the reflectance of the digital white basic signal Bb is set to 100. The reason why 10 bits are given is to obtain resolution up to the o1 factor.

The thermal correction signal M stored in the storage circuit 305 is a 10-bit digital encoded version of the designated black reflectance when the reflectance of the digital black reference signal Bd is set to zero.

The white-sleeved positive signal H read out from the memory circuit 304 is supplied to the white level tracking circuit 4, and the crude signal M read out from the memory circuit 305 is supplied to the black level tracking circuit 5.

As shown in FIG. 1, the white level tracking circuit 4 calculates the above-mentioned equation (1) based on the digital white reference signal Bb, the digital black reference signal Bd, and the white correction signal H.
The upper limit reference voltage vH of "VWj'port" shown in the figure is generated and supplied to the analog-to-digital conversion circuit 6.

Further, the black level tracking circuit 5 receives the white line signal F.

Based on the digital black reference signal Bd and the thermal correction signal M, the above-mentioned equation (2) is calculated and "■8" shown in FIG.
Generates the lower limit reference voltage vL of volts and converts analog to digital! Supply to J road 6.

Next, in FIG. 1, the scanning circuit 7 scans the original image and outputs the image signal Aa shown in FIG. It is supplied to the conversion circuit 6.

The analog-to-digital conversion circuit 6 converts an upper limit reference voltage of gVw 17 volts and "
According to the determination level between the upper and lower limit voltages regulated by the lower limit reference voltage v1 of VB#F volts, it is converted into 8-bit tickle encoded data, passed through the bus switching gate 8, and output as the digital signal Ba.

FIGS. 8 and 9 show waveform diagrams of the above operation. In FIG. 8, the k increment 11 indicates the input voltage of the analog-to-digital conversion (b) path 6, and the horizontal axis indicates the cycle T of one-stroke blue. Further, point X is the value obtained by converting the average density value of the specified area in the white density area into a voltage value, and point Y is the value obtained by converting the average density value of the specified area in the black intensity area into a voltage value.

8, the image signal Aa shown in FIG.
It is clear that the 256-step molecular iph capability of the analog-to-digital conversion circuit 6 cannot be obtained when analog-to-digital conversion is performed with ``volts'' as the upper limit reference voltage V and 11 V-'' as the lower limit reference mW pressure VL. When the digital image signal Ba obtained in this manner is recorded and reproduced, the white and black density regions cannot be reproduced, and a type 1 image with good contrast cannot be obtained.

One point mx in Figure 8? When the image signal Aa is digitally transferred with the "■' volts indicated by bV as the upper limit reference ML pressure voltage VB71 volts as the lower limit reference voltage VL, the hatched "A" part of the image signal Aa is the white "mouth". ′ and “ha”
However, the resolution of the analog-to-digital converter circuit 6 can be fully obtained in the other areas.

It should be noted that the parts 'A II, II' and 'C' are the parts that are determined to be unnecessary for reproduction, as they are the gaps in which a specific one-speed area of the white and black speed areas on the original image is designated.Therefore, the digital image When the signal Ba is recorded and reproduced, a reproduced image 1b with good contrast is obtained.

FIG. 9 shows an apparent image signal A corresponding to the judgment classification of the analog digital conversion circuit 60 when the upper limit reference voltage is set to "1-" volts and the lower limit reference voltage is set to "VB" volts.
It is a mirror image.

As explained above, in the embodiment of the present invention, the extraction circuit 1 and the extraction path 2 have the same circuit groove configuration, but similar results can be obtained even if they have different configurations.

Furthermore, the number of pixels to be extracted may be any number, and may not be the same for white and black.

〔Effect of the invention〕

As described above, the image signal correction device of the present invention includes a first extraction circuit, a second extraction circuit, and an average value circuit.

A white level tracking circuit and a focus level tracking circuit are provided to detect the specified white and black on the original image, including shading and dark current compensation, instead of fixing the upper reference voltage and lower reference voltage and performing analog-to-digital conversion. By performing the analog-to-digital iTh using the upper limit reference voltage and lower limit reference voltage based on the correction value corresponding to the density region, a resolution equal to that of the analog-to-digital conversion circuit can be obtained, which has the effect of improving image quality.

[Brief explanation of the drawing]

1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a detailed block diagram of an extraction circuit in the embodiment shown in FIG. A detailed block diagram of the value circuit, the fourth figure is a detailed block diagram of the mortar level tracking circuit in the second embodiment shown in FIG. 1, and FIG. 5 is a detailed block diagram of the black level tracking circuit in the embodiment shown in FIG. 1. 6 is a time chart for explaining the operating sound of the extraction circuit shown in FIG. 2, FIG. 7 is an explanatory diagram of the operation of image signal extraction by the extraction circuit shown in FIG. FIG. 9 is a waveform diagram for explaining the operation of the embodiment shown in the figure, and FIG. 9 is an apparent drum-shaped diagram for explaining the operation of the embodiment shown in FIG. ...Extraction circuit, 3...
...Average 1 series circuit, 4...White level tracking circuit,
5... Black level tracking circuit, 6... Analog digital measuring circuit, 9.10... Memory circuit, A... Photoelectric conversion signal, Aa ...Picture signal, Ab...White reference signal, Ad...
Black reference signal, B... Digital coding code, B
a... Digital image conversion, Bb... Digital white standard No. 11, Bd... Digital black reference No. 15, L... White data signal , N...
...Black data signal, i-1...White stop No. 1d, λ4...Black supplementary No. 1'B, air...Upper limit semi-free pressure, vL・・・・・・Lower Moeki voltage.

Claims (1)

[Scope of Claims] A first extraction circuit that extracts white data signals of a plurality of pixels obtained by scanning a specified white density area of an original image, and a first extraction circuit that scans a specified black density area of the original image. a second extraction circuit that extracts all of the black data signals of a plurality of pixels obtained through the process; Calculate the upper limit reference voltage based on the white reference signal corresponding to one scanning line obtained by scanning the value circuit and the reference white plate, the black reference signal corresponding to the photoelectric conversion element output voltage at zero incident light, and the white correction signal. a white level tracking circuit that calculates a lower limit reference voltage based on the white reference signal, the black reference number 1, and the black correction signal; An image characterized in that an upper limit and a lower limit πV positive pressure judgment level are controlled, and the image is operated with an analog-to-digital conversion circuit that performs multi-value decomposition of an image signal obtained by photoelectrically converting the gradation information recorded on the original image according to the judgment level. Signal modification device.