JPS5956289A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten the write time, by providing a common shunting circuit for many pairs of bit lines and supplying a shunt current automatically only to corresponding lines at the write time. CONSTITUTION:A shunting circuit IW* which increases the current quantity of a current source IW for write to I+I* and increases the current flowed to lines to I* while setting a bit line current to I as it is, is added to lines L1 and L2. The current quantity I is, for example, 2mA and is flowed only to a selected bit line, and the current quantity I* is, for example, 2mA and is flowed out from the shunting circuit IW*. Since the current (current quantity I*) is flowed positively to the line L1 connected to a selected bit line BL, pulling-out of the electric charge of the parasitic capacity, the emitter capacity, etc. incident to the line L1 is accelerated, and the potential of the line L1 falls quickly, and the write time is shortened. If data ''1'' is to be written on the bit line -BL side, a similar quick potential fall occurs with respect to the line L2.

Description

[Detailed description of the invention] (1) Technical field of the invention The present invention relates to semiconductor memories.

(2) Background of the Technology In recent years, aE types of semiconductor memories have been proposed and put into practical use. For example, looking at the format of the memory cells therein, U-shaped ones are known. Regarding saturated type memory cells, SCR type, II
There are many types such as L type and diode load type. The present invention is directed to a semiconductor memory comprising this saturated type memory cell. or,
In this type of memory there is also t! 1 (tashi, ti
There is a method that makes the Kleil (inflow current) at the time of J insertion larger than the current at the time of expulsion (current at the time of expulsion).

Since this is a saturation type memory cell, the switching speed is slow, so this is especially true for 1° IAi.
This is to speed up the time it takes to look at the dog as a fr dog. Furthermore, there is also a type in which the pre-dCC interlocking current (bit line ↑ [[1ifi)] is selectively applied only to the selected bit line. This is effective for reducing consumption and mental energy, and is also useful for shortening access time.

The present invention relates to a semiconductor memory of the type that is composed of the above-mentioned saturation type memory cell, in which the write magnetic current is particularly controlled, and in which bit line current is applied only to the selection pitch if.
It is something that affects people.

(3) Prior Art and Problems FIG. 1 is a circuit diagram partially showing a conventional semiconductor memory, which is the premise of the present invention. In this figure, Me indicates a memory cell, particularly a saturated type memory cell. Each memory cell Me has a plurality of words - w+, w- and a board number of bits ~ pairs BL.

Connected to each intersection of BL. Each bit line pair BL.

A bit line h circuit BD is provided in BL, and the circuit B
D is the corresponding bit line pair B according to the manual address AD
Select L and BL. Then, the manual address AD for selecting the leftmost bit line pair Bl, BL in the figure is 11.
, the transistors T, ,T forming the decoder
, etc., and turn off the emitter follower transistor 1.
゛via γ, and further a level shift diode D-i
A high potential is applied to 71 points in the figure. Here, a bit a switching circuit BSW consisting of transistors 1', , T2, etc.
(ON in the dotted circle in the figure) here is the leftmost bit line pair B, L.

BL is selected. In this case, the high potential is not applied to the 71 points in the unselected bit line switching circuit nsw,
This remains undriven. Transistor '1'1
One of the multi-emitters of the transistor T, together with the corresponding emitters of the other bits and pairs, is connected to a common reading BL 15fe IR so as to form a current □(y). The other emitter is also connected to the common magnetic current source (7) for current generation, together with the corresponding emitters of the other bit line pair groups, so as to form a current switch.

Also, is the emitter group of the transistors connected to the sense Anzo SA also formed into a current switch? )i: 6f
r, +Mi I, K connected. This also applies to the emitter group corresponding to the transistor T2, which satisfies the above-mentioned format in which the bit line current flows only through the selected pair of cut lines.

Further, the type of semiconductor memory on which the present invention is based is such that the cutting magnetic current is particularly large compared to the six-element magnetic current as described above. For this purpose, the tiger 7 nosta T3tT4 was used, and if it was selected, the data would be on the Bl side (or the i〒 side) of the selected bit 1 pair (currently, the leftmost one in the figure). When inputting νf 1#, turn off the corresponding transistor Ts (father is T4).When turning off the transistor T, (or T4), the emitter 5, which is connected to the current source 7 of the transistor TI (or T2), Transistor T3 (or 1
゛4) is lost, Iw is completely applied to the bit line BL (or -B l, ), and the magnetic current (bit line 't
';L IJif,) becomes large. Note that in this case, the transistor pair 1 at the end of the bit line pair BL, BL
Only the left transistor of '7 is turned on in synchronization with the nailing command.

Now, while trying to solve the problem of the present invention, the '@ point will be described. The origin of this lies in the large number quantization of semiconvoluted memory. In other words, the number of bit line pairs increases. Then, the length of the line Ll t L2'';+ in the figure will run 75KJ.

Here, the parasitic capacitance attached to the line increases,
Transistors associated with these lines T 1 r T
The emitter basis weight (junction capacitance) of Group 2 also increases. Thus, the increase in these capacitances increases the load during writing and increases the commitment time on the selected bit/line pair. This obviously runs counter to the goal of shortening memory access time (M6), so I came up with a plan. The idea is to increase the capacity of current source 1. Increased power, which until now had no power, increased to 10I. However, this proposal is not valid. This means that the current of I +I* is all selected bit #
This is because the current flows only to BL (father is 11).In that case, the width of each bit line of all bit line pairs must be made thick so that it can handle the large current of 10I. Even if it leads to a reduction in time, it is not a good idea because it causes a decrease in bit density.

(4) Purpose of the Invention In view of the above-mentioned problems, the present invention has been developed to increase the bit density.
The object of the present invention is to propose a semiconductor memory that does not cause an increase in re-induction u6 even if it is converted to 61+.

(5) Structure of the Invention In order to achieve the above object, the present invention provides a write current source
7 is increased to I + I'', and the bit line current is set to I. A 6tUM path is added to the line to increase the current flowing toward the line to 1 until '=1. This is a characteristic feature.

(6) Embodiment of the Invention FIG. 2 shows one implementation of the shunt circuit added according to the present invention? 1
It is a circuit diagram showing J. In this diagram, the shunt circuit is ■7
The other lines L1+L2 and transistors T3 and T are as shown in FIG. 1 t/W of human power applied to each pace of l transistors 'r3 and 'r4) At the time of reading (R), both are easy to read, but at the time of - reading (W>), the pitch is
1ilB L C or tiB L ) data 61",
” or “0#” to 1.

That is, if bit 91M on the left side of FIG. 1 + t4"i
Select the pair and put data “1#” on the bit line BL side.
If the transistor T3 is to be input to the transistor T3, each pace input R/W is applied to turn off the transistor T3 and turn on the transistor T4.

By the way, according to the present invention, the amount of current of the current source Iw for including i1 in FIG. 1 is increased from ■ to I + I*. current i
The current tI is, for example, 2 mA, and flows only to the selected bit line, while the "current II" is also, for example, 2 mA, and is made to flow out from the shunt circuit (2). In this way, the current (current -!IIHI'') is actively applied to the line Ll connected to the currently selected bit line BL, so the capacitance (parasitic valley IN, emitter The removal of the boxes and loads of container 'i+1:) is accelerated, and the line ■,
A fall of about 10 tons is made rapidly. 1. - The time required to complete the process is shortened. If the bit line nl, data on the side
When writing '1#, a similar rapid fall in the ' potential occurs for line I, 20. Such a diversion 1
,1. The L flow (I) is automatically connected only to the corresponding line L or I, 2 (line Ll or Lx corresponding to the bit line nL or Bl to which data 11# should be inputted) by the shunt circuit. ■- It is preferable to have a constant supply.

The shunt circuit in Figure 2 - is connected to the corresponding line (
With respect to Ll + L2), the shunt current (I + L2)
It is configured as something that can be supplied.

First of all, use the multi-emitter to connect ShiraiyL1. Connected to L2 hN
A transistor T8 is connected to each bit gland pair BL.

Multi-emitter transistor T1 connected to BL,
1 with the same configuration as the group T2 (all with the same configuration)
There are two transistors. Y corresponds to the pace of this transistor T8. The 'TE position of the point is set to be the same potential as the 71 points mentioned above. For this reason, a dummy bit f1M drive circuit BD* is provided. This is bit nd drive circuit BD
The circuit BDI is a simple circuit and is in the selected state.
It has a circuit configuration corresponding to C. Tsumashi, left in Figure 1! Assuming that the circuit BD of 111i is in the selected state,
The transistor T7 of the circuit BD* corresponds to the transistor T7 of the circuit BD, and corresponds to the diode D and the diode D, respectively. Also, since the circuit BD is in the selected state, its transistors 'I'5+'l'g are both off and 1, and the resistors l (and 'torques θ111, 1111■BD
only visible. These R and 'BD are the cod and I director in the circuit BD*. It is indicated by.

Considering the time of reading now, each pace human power lVW of transistors T3 and T4 is at a high potential, and both the 71st point and 10th point are set to a high level, so this dummy circuit B D * The fact is that ``two is non-driving.''

Considering the writing time, which is the current problem, only the pace human power R/W of transistor T3 is low at about ↑h,
Since the 10th point has a high potential with respect to the pace human power R, /'W, and the circuit BD* is equivalent to the circuit BD at the time of writing, the potentials of the 70th point and the 71st point are equal υ, automatically , is now selected and ((() The current begins to be shunted to the line L1 connected to the bit line B L where 1 is written. Note that during reading, both transistors T3 and T are on (as described above).
By dividing the current from these transistors T3+T4 to the current source 28, the bit line current during reading is substantially reduced. Further, the ratio of the current value 1 and I* described above can be appropriately set by the ratio of the transistor ('l'l r T2 ) and each emitter of the transistor 8) IIlt.

(7) Detailed explanation of the invention/As described above, according to the present invention, the branch Oat circuit automatically supplies the branch flow '1 outflow (I'') only to the corresponding line at the time of river inflow. J input time is shortened. However, the installation of this shunt circuit does not reduce the υ bit density. This is because there exists.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1(t) is a circuit diagram partially taken out of a conventional medium 4f memory which is the premise of the present invention. FIG. 2 is a circuit diagram showing one actual row. MC...Memory cell, BL and Bl,...Bit line pair, BSW...Bit H (7I replacement circuit, B1)...
・Bit line drive circuit, T1 to T8+T? *... Transistor, Ll + L2... Line, ■... Current for sinking, B I)"-... Dummy bit line drive circuit, ■-... Shunt circuit. %R'[ Applicant: Sugitsu Co., Ltd. 1) Representative Patent Attorney: Akira K. Patent Attorney Kazuyuki Nishidate 1) Yukio Patent Attorney: Akira Yamaguchi

Claims (1)

[Scope of Claims] (1) A plurality of saturated memory cells each connected to a plurality of bit line pairs, and a plurality of saturated memory cells each connected to a plurality of bit line pairs for each bit +%l pair in order to select one of the bit line pairs. A bit line switching circuit provided, a bit line driving circuit provided for each face bit line pair for selectively activating the bit line switching circuit according to an input address, and commonly connected to the plurality of bit line switching circuits. At least the current source for loading and the plurality of bit line switching circuits are all i11! They are attached to at least two connected lines and both are turned off during reading. Current is shunted and selected to the current source for writing through a transistor that is turned on or off according to the pledged data at the time of loading, and the line connected to the transistor that is turned off at the time of loading. A semiconductor memory comprising a shunt circuit including a configuration equivalent to the bit line drive circuit.