JPS5956132A - Digital type supersonic stress measuring method and device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The invention described herein relates to an intelligent ultrasonic measurement device. More particularly, the invention relates to a device for measuring the average tensile stress in a bolt or tensile load member when a fastener is tightened to a structure to be fastened.

Accurate measurement of tensile stresses within threaded fasteners is useful in controlling the clamping force exerted by such fasteners and in determining the tensile stress that does not lead to the yield stress of the fastener material. This is important in preventing the invalidation of

In the history of threaded fasteners, numerous devices have been developed and used for the purpose of measuring and/or controlling the above-mentioned tensile stresses.

Torque wrenches attempt to control such stresses by determining the rotational energy applied to the nut, and the measurement of such stresses is performed between the nut and the bolt and between the nut and the structure or warp. is accurate because the frictional force is variable.

Hydraulic tensioners apply precise tensile loads to the fixture.

However, unless this load applied to the nut is alleviated, accurate control becomes extremely difficult.

Mechanical micrometers have been used to measure the elongation of a fixture when tightening is proportional to the applied tensile stress. Such devices are time consuming to operate and are subject to operator error.

A variety of ultrasonic instruments (
(echo region) Extensometers generally have a limit in the overall length or elongation that can be measured.

These units measure apparent length changes in the fixture without adjusting for different acoustic phenomena between stressed and unstressed parts of the fixture. Nor are these units readily applicable to different fastener materials or different depth changes.

Therefore, an accurate correlation of the apparent length changes of the fixture dictated by these units is of no practical use.

Therefore, the devices described above do not provide a practical means of measuring or controlling compressive or tensile stresses in bolts or similar members. It is for this purpose that we have developed the present invention.

A typical example of these ultrasonic extensometers is US Pat. No. 3,759 to McFaul et al. No. 090, K discloses an analog device for measuring bolt elongation. In the McFaul patent, an ultrasonic pulse was inserted into the bolt being measured and the echo pulses were received and processed. The reception time of the echo pulse for the unstretched bolt was adjusted to immediately follow the periodically generated marker pulse. The time between occurrences of each marker pulse corresponds to the displayable elongation of the bolt. The time between the occurrence of an echo pulse and the occurrence of the next marker ξ pulse is converted to an analog meter reading, and the deflection of the analog meter needle is calibrated to indicate the magnitude of the stretch. As the bolt stretches, the applied pulse travels the length of the bolt, increasing the time it takes to be reflected back. This reduces the time between the occurrence of an echo pulse and the occurrence of the next reference .xi. pulse.

As a result, the meter reading is also reduced. In this way, the user could monitor changes in elongation by observing the meter reading decrease as the bolt was elongated.

McFoul's ultrasonic extensometer allowed the user to monitor elongation readings, but it did not tell the user the actual stress the bolt was experiencing. Additionally, because the instrument indicates the time between the reception of each echo pulse and the next reference pulse, the instrument movement does not include the normal fluctuations that occur when a series of specimens is measured individually. It was. Furthermore, since the amplitude of the echo pulse changes for each sample, the exact time when the echo pulse is received for each sample is not constant. This not only added further wobbling to the meter's display, but also degraded the accuracy of the indicated stretch. McFoul's ultrasonic extensometer is set so that the received echo pulse occurs immediately after the reference pulse, so the user must first zero the unstretched portion of the bolt. Ta.

The resulting elongation readings further included errors caused by zeroing. In addition, the analog circuitry used to process the ultrasound signals was subject to short and long term drift, resulting in extremely long warm-up times and reduced confidence in the reproducibility of readings. .

The above problems and other problems associated with prior art stress measurement methods and apparatus are overcome by the present method and apparatus for measuring length and stress in tensile load members. The load member in this case has first and second ends, and in the method and apparatus the transducer is actuated to insert an ultrasonic pulse into the medium of the load member, and the transducer is loaded into the load member. Receive the reverberant pulse reflected from the second end of the member and convert the reverberant sound into an equivalent electrical signal. This device is a time interval measuring device for determining the elapsed time between actuation of the transducer and reception of the echo/ξ pulse, and is used for the time interval used in tension members under load and unload conditions. A measuring device and an intelligent processing and control device that receives the elapsed time data sent from the time interval measuring device and the information input by the user, and controls the time interval measuring device and records the elapsed time and the user's input information. and a processing and control device for deriving a plurality of stressed member parameters, including length and stress, related to stress loading from input information.

The apparatus provides a method for measuring the time interval between the start of an actuation signal and a return signal, and includes a first clock signal that occurs between the start of an actuation signal and the reception of a return signal. ), the first clock being synchronized to the onset of the activation signal and having a predetermined frequency; One clock consists of a stage for generating a second clock having a predetermined phase difference, a stage for measuring the first clock interval from the time of reception of the return signal until reaching a specific state after the first clock, and a stage for measuring the return signal. a step for measuring a second clock interval at which a particular state of the second clock signal occurs from the time of reception of the second clock signal; and a step for detecting the longer of the first clock interval and the second clock interval; and combining the cycle count with the selected clock interval to convert the cycle count and the compensated selected clock interval into units of time. and, including.

The above method reduces the problem of quantification errors that occur when the incremental period used to measure time intervals is large relative to the required accuracy.

In the method of the present invention, the time interval measurements transmitted to the intelligent processing and control device are collected over a significant number of measurement cycles or samples, thereby providing more accurate time interval values. This time interval measurement method is based on the echo and ξ
It is necessary that the points considered to indicate the reception of a russ be designated as the 1st and 27th rostral passages of the received analogoda ξ rus echo signal. It has been found that although the amplitude and duration of the echo pulse may vary from sample to sample, the 1st and 27th point passes of the received pulsed echo signal are consistent for any sample. has been done.

The intelligent processing and control device controls the window through which the time interval measurement device receives pulsed echoes from the tensile load member. These windows are automatically adjusted depending on the material, the length of the tensile load member being measured, the amount of elongation the load member has, and other parameters. An intelligent processing and control device receives the time interval data from the time interval measuring device and derives from that data the magnitude of the stress being experienced by the tensile load member. Calculations using this method are based on the measured time intervals obtained from the time interval measuring device, but also include other factors such as flow rate, material of the tensile load member, change in sound velocity due to stress applied to the tensile load member, The overall length and modulus of elasticity of the tensile load member, thermal expansion of the tensile load member, etc. are also taken into consideration. The intelligent processing and control device provides the user with the actual average stress and other data for the loaded length of the bolt by means of indications including visual means and electronic signal means.

The apparatus and method of the present invention thus provides actual stress data, as opposed to providing mere elongation data.

Therefore, the user does not have to rely on tables, pre-calculated numbers, or the interpolations often associated with these materials to determine whether a tensile load member is properly loaded.

By providing a seven-point passing reference point for the received echo signal and performing sample averaging within the time interval measurement unit, measurement fluctuations and uncertainties that were a problem with the previous elongation measuring device +tt can be eliminated. The size is significantly reduced. Control of the time interval measuring device by an intelligent processor and controller reduces the operator adjustments required for accurate readings. By taking into account temperature, modulus of elasticity, thermal expansion and other physical phenomena in stress determination, more realistic and accurate stress measurements are obtained.

It is therefore an object of the present invention to provide a method and apparatus for the measurement of stresses in tensile loaded members.

Another object of the present invention is to provide a method and apparatus for measuring stress in tensile loaded members in which time-spaced measurements are achieved using a biphasic clock so that quantification errors are reduced.

Still another object of the present invention is to provide a stress measurement method and its method in which physical phenomena such as changes in sound speed in a material under stress, modulus of elasticity, thermal expansion, and changes in sound speed due to material properties are taken into account when obtaining stress values. It is to provide the equipment.

Still another object of the present invention is the incidence of ultrasonic pulses and its
ξ A tensile loading member in which the time interval between the reception of the echo pulse is measured digitally and the time at which the echo pulse is received is determined by the first and second zero crossings of the received echo pulse signal. The object of the present invention is to provide a method and device for measuring internal stress.

Yet another object of the present invention is to provide a method and apparatus for measuring stress in a tensile load member in which an intelligent processing and control system adjusts the timing and sampling rate of the time interval measuring device.

These and other objects, features, and advantages of the present invention will be readily apparent upon consideration of the following detailed description of several preferred embodiments of the invention, taken in conjunction with the accompanying drawings.

The general operation of the invention will now be described with reference to FIG.

Conceptually, the device of the invention can be divided into several K functional elements or functional blocks (sections).

The pulse generator/receiver (10) is a piezoelectric crystal transducer (12).
) produces a sharp high voltage stroke (or pulse) to be transmitted to the The transducer (12) is physically held to the end of the threaded fixture or tensile load member (1o) via a coupling medium. The electric pulse is applied to the load member (1
0) Longitudinal direction (high-frequency ultrasonic waves transmitted in
A portion of this pulse is reflected back to the transducer (12) by the opposite end of the load member, where it is again converted with an electrical echo pulse (12) to the pulse receiver (12).
1ro).・The receiver part of the ξ pulse generator/receiver detects the arrival of a reverberating pulse by identifying the point where the signal A, Lugi changes from negative to positive voltage (seven point passage detection). Due to this unique detection, the return of the pulse can be detected accurately regardless of the magnitude of .xi. Sa l'
-)((The receiver is sterilized by the commands generated by the intelligent processing unit (RO0), so that only the first echo from the end of the fixture (or other predetermined point) is detected; All other false echoes or resonances are ignored.

Intelligent processing and control device (30) K allows the time interval measuring device (15) to be controlled. The measuring device (15) is actuated by the pulses emerging from the ξ pulse generator (13) and, as soon as the echo pulse is detected by the receiver part, the number of clock pulses generated by the reference oscillator (38) is and measure the elapsed time for a fraction of the clock ξrus. Furthermore, this measuring device receives instructions from an intelligent processing and control device (30) as to the number of intervals between this pulse and the echoes to be accumulated during the sampling period and thus performs a dynamic averaging of the data obtained. Let's do it.

The intelligent processing and control unit (60) provides a number of functions in coordinating the interaction of the ξ pulse generator and receiver (13) and the time interval measuring device (15). An intelligent processing and control unit (LO0) monitors the collection of pulse data and processes these data to accurately convert the length of the fixture or stress value applied to the tensile load member.

Intelligent Processing and Control Device (30) K is given physical constants for a large number of tensile load members or load members of judgment. These constants and applicable equations allow the pulse data to be interpreted in terms of changes in the speed of sound in different materials, elasticity of different materials, thermal expansion of different materials, and changes in these parameters with temperature. Additionally, the intelligent processing and control device (60) provides the variation in sound velocity with respect to the intensity of the applied stress and the actual length of the tensile load member (10) to which the stress is applied.

The functional operation of each of the above elements will be explained in more detail. Please refer to FIGS. 1 and 2.

The tensile member (1o) whose stress is to be measured is connected to a transducer (12). This converter further includes an irradiation generator (14) and an irradiation generator/receiver (14) as described above.
A receiver/amplifier (16) including a receiver/amplifier (16) is connected to the receiver/amplifier (16). The pulse generator (14) id outputs the actuation signal (19) of FIG. 2 to the transducer (12) in response to the actuation trigger signal of FIG. In response to this actuation signal or pulse, the transducer (12) injects a high energy ultrasound pulse into one end of the tensile load member. This ultrasonic pulse creates a shock wave that is transmitted along the length of the load member and reflected by the other end of the load member.

This reflected pulse or echo/ξ las returns along the length of the load member (10) to the transducer (12) force! Return to the end of the loaded load member. When this reflected signal reaches the transducer (12), the modulator m1d (12) converts the reflected wave of FIG. 2 into an equivalent electrical analog signal (21) of FIG. Prior to this, the converter provides the actuation ξ pulse (19) of FIG. 2 to the receiver and amplifier (16) where it is processed. A receiver/amplifier (16) detects the arrival of the reverberant ξ pulse by identifying the first and second zero crossings of the electrical ξ pulse signal. When such a zero crossing is detected, the receiver-amplifier (16) outputs a reverberant reception pulse (25) of FIG. 2 with a predetermined duration.

The echo signal (21) of FIG. 2 outputted by the transducer (12) is typically an alternating current signal with an amplitude of typically a few hundred millivolts and a duration of various lengths. The activation signal (19) of FIG. 2, which is also received by the receiver and amplifier (16)K, has an amplitude of 100 ports and a duration of approximately 1 microsecond for a typical fIl. During normal operation of the pulse generator (14), transducer (12), and receiver/amplifier (16), a series of actuation signals are transmitted and corresponding echoes and ξ ruses are received.

It is a common phenomenon that a shock wave traveling in a tensile load member can maintain a large amplitude even after making several reflections and reciprocations within the tensile load member. Therefore, the transducer (12) often receives echoes ξ rus from the tensile load member corresponding to the third, fourth and third reflections. A blanking circuit (36), detailed below, for distinguishing between the desired actuation signal and the first reflected echo pulse signal and discarding subsequent reflected signals.
The AGC signal (27) shown in FIG. 2 sent from the terminal is given. This AGC signal (27) effectively shuts off the receiver and amplifier (16) during periods in which non-essential signals may occur.

The received echo from the receiver/amplifier, ξ Lux (25), is ξ
and a pulse receiver (18).・Erus receiver (1
8) converts this signal into a pulse (29) in FIG. 2 with a predetermined duration and rapid rise time. The ξ lux receiver (18) distinguishes between the signal from the receiver/amplifier corresponding to the activation signal and the signal from the receiver/amplifier (16) corresponding to the echo ξ rus (21). In this regard, as soon as the pulse receiver (18) receives the actuation signal and the corresponding echo signal, it transmits a K "fair echo" signal to the sequence control circuit (62), which will be described in more detail below. This "valid echo" signal is used by the Sequence I control circuit (port 2) to monitor sample processing.

The echo signal extracted by the pulse receiver (18)K is provided to an error detection circuit (20)K. Error detection circuit (2
0) provides a method for eliminating time interval measurement errors that can greatly reduce the quantification errors that often exist in digital measurements. In this method, time intervals are measured with respect to a two-phase clock. Preferably the phase difference between the two clocks is 1
It is 80°. Phase differences of more than 180° can also be used satisfactorily by applying appropriate adjustment. A first clock (31) and a second clock (33) are shown in FIG. Second clock (3
3) has a phase shift of 180° from the first clock (three).

In this method, the time interval is determined to begin at the moment the echo pulse is received. The time interval is determined to end when the selected condition within each clock occurs. This selected state is the rising edge of the clock signal,
It may be a falling edge, crossing zero, or other conditions. Furthermore, the clock state can also be represented by specifying the occurrence of a particular numbered state, eg, the first occurrence.

In a preferred embodiment of the invention, the first rising edge after reception of the echo pulse is selected as the clock state that defines the end of the time interval. Each clock is 180% different from the others
Because of the phase difference of .degree., a rising edge in one clock occurs one cycle before or after a rising edge in the other clock. If the longer time interval between the reception of the echo ξrus and the occurrence of a particular state in the clock is chosen, the time interval involved is always at least as long as the clock frequency recycles. That will be understood. Furthermore, since the time interval to be measured has a minimum value,
Interpolation errors are greatly reduced. In FIG. 2, it can be seen that the time interval corresponding to the second clock signal (36) is the longer time interval.

Theoretically, the accuracy when digitally measuring a particular interval is determined by the width of the sample interval used. For example, if the sample interval is 50 nanoseconds, the quantification error associated with a measurement using this sample interval is 50 nanoseconds. When measuring time interval increments of size less than or equal to the sample interval, the accuracy of the measurement decreases as the increment interval becomes smaller. Beyond a certain point, this time interval increment cannot be measured at all. On the other hand, in the present invention the incremental time period is chosen to be at least half the sampling period used. Therefore, the incremental time intervals are always large enough to allow accurate measurements.

The output of the error detector (20) is a second incremental time interval with a time interval corresponding to the longer of the two incremental time intervals.
This is the pulse (35) in the figure. This pulse is applied to an error storage circuit (22) where the pulse widths for a large number of individual samples are accumulated. The sum of this error is converted into digital form by an analog-to-dental converter (A/D) (40)K and provided to an output register (24).

At the same time, the counting control circuit (26) using the second clock (gate 1) of FIG. 2 with the detection of the above-mentioned error signal inserts the actuation start signal (17) of FIG. 2 and receives the echo pulse (21). Controls the number of clock pulses =ta occurring between. The counting control circuit (26) receives a signal indicating that an activation signal has been transmitted from the main pulse circuit and blanking circuit (36), which will be described in detail later. Upon receiving this signal, the counting control circuit (26) provides a series of pulses from the second clock (33) of FIG. 2 to the output register (24) K. This clock pulse train (39) in FIG.
) is disconnected by the counting control circuit (26) in accordance with the counting adjustment signal from ). This counting adjustment signal is necessary in the two-phase clock method of determining error as described above.

When the error is referenced to the second clock (33), pulse counting ends after the first pulse of the second clock (33). This first pulse comes after the echo signal is received. By examining the signal (41) of FIG. 2, it can be seen that the difference between the pulse count value (39) minus the error signal value (41) gives the correct time interval.

On the other hand, when the error is based on the first clock (31), as in the error signal (43) in Fig. 2, by directly subtracting this incremental time interval from the corresponding pulse count value (39), , a time interval as small as the noise cycle is obtained. This noise cycle error must therefore be taken into account in the time interval calculations.

One way to provide this correction is to: every other time when the error signal (39) is referenced to the first clock (31)
Adding another pulse to the count. Adding a -pulse to the pulse count corresponds to a time overtime of two more half cycles than two sample periods. The half-cycle loss that occurs every sample period is removed as follows.

The "counting adjustment signal" is the first clock (31) that is the error signal (
When used as a measurement reference signal in 35), the "count adjustment signal" terminates pulse counting (69) on the arrival of the next second clock pulse.

The output register (24) accumulates the number of pulses sent by the counting controller (26). Furthermore, for each sample set, A/
Contains the error sum from the error storage circuit (22) which is converted to digital form by the D counter (37). Output register (24
) provides this data to the intelligent processing and control device (60) after the question and answer request signal (IRQ) is sent to the intelligent processing and control device (30). This question and answer request signal is sent to the sequence control circuit (32) after all sample sets have been obtained.
) Sent from K. The register selection circuit (28) receives call data from the intelligent processing and control unit (30), decodes it, and selects the decision in the output register (24) that provides the data to the intelligent processing unit (30). Indicates the register. The number of samples mentioned above is based on the sequence control circuit (32
) controlled by The sequence control circuit (62) receives question and answer instructions on line (engineering NTE) from the intelligent processing and control unit (30).

This question and answer command initiates the counting of the predetermined number of valid samples taken by the time interval measurement device (75)K in the sequence control circuit (32). Engine case control circuit (32
) outputs a signal on the line (IRQ) to the intelligent processor (30) K, indicating that a valid sequence of samples has occurred. In the preferred embodiment of the invention, a sample sequence containing approximately 500 samples is selected. A sequence of valid samples is a collection of samples that are in a continuous sequence and all of which are determined to be valid. If there is even one invalid sample during collection, counting is restarted anew.

A fixed delay device (34) provides a start pulse to the main pulse/blank control circuit (36). This starting pulse and blanking circuit (66) generates an actuation trigger pulse, and when the actuation trigger pulse is given to the pulse generating circuit (i4) K, this actuation trigger pulse transfers the actuation signal to the converter ( 12). Fixed delay (34) includes a device that provides a starting pulse at each predetermined periodic interval. This pulse is synchronized to the second clock (33).

Once the system is input activated, the fixed delay circuit is essentially free to operate. This circuit then continuously provides a start pulse to the pulse and blank circuit (36) periodically.

Therefore, the pulse and blanking circuit (lo 6) continues to output actuation trigger pulses until it receives an instruction to abort. In the present invention, the down-counting decoder (139) provides a reset signal to the pulse/blank control circuit (36) for resetting the pulse generation function.

- A blanking circuit included in the ξ pulse and blanking circuit (66) provides a blanking signal to the receiver and amplifier (16).

These blanking signals indicate the window within which the receiver and amplifier (16) is commanded to monitor the signal received from the transducer (12). For all time intervals other than the indicated window, the receiver and amplifier (16) is effectively turned off. These blanking windows are activated by the intelligent processing unit (30) at the moment when the activation pulse is output from the pulse and blanking circuit (36), i.e. at the moment when the echo pulse is received by the pulse receiver (18). ) is evaluated according to the blanking data given by As mentioned above in connection with the receiver/amplifier, the blanking window, i.e. the time at which the receiver/amplifier (16) is turned on, is the time at which the bang trigger pulse is output. is "opened" just before the time at which the first echo signal is thought to occur.

These windows are closed as soon as there is an output signal of the actuation signal and reception of the echo signal. Since the only significant part of any signal is the initial signal edge, and since the actuation and reverberation signals are potentially multiwave and contain multiple frequencies and amplitudes, it is not necessary to analyze only the significant intervals. The use of blanking windows greatly enhances the operation of the present invention.

Blank data provided by the intelligent processing unit (3o) is received via a control and input register (42). The intelligent processing unit (30) derives this blanking data from the information it contains as well as the information it receives from the user.

Generally, this blanking data indicates a time interval following the main bang trigger pulse. After this, it is expected that a reverberation pulse will be received for the particular tensile load member under test. This process includes consideration of temperature, material, length, and other physical parameters involved in the specific specimen conditions.

The two-phase clock (31) (33) is the clock circuit (3
8) is given by The clock circuit (38) is made of crystal (
Derive these clocks from a crystal oscillator. The output of this crystal oscillator is output in response to a reset signal applied to the intelligent processing unit (30).

As mentioned above, the intelligent processing device (30) provides control and timing signals to the time interval measurement device (15) and receives time interval data from the device (15).

Essentially, the intelligent processor (30) determines when to start a new sample set, the blanking window to use, the amount of sample to take and when to start evaluating the measurements.
) to give commands. The intelligent processing device (30) may selectively receive data stored in the output register (24) of the time interval measuring device (15).

The intelligent processing device also receives information from the user via a data input device, such as a keyboard (44). The information received from the user may include bolt length, type, specifications including grip length, stress limits,
There is a temperature and display unit. The intelligent processing device then
This user input information is evaluated and the time interval measurement device (15
) is equipped with a bi-intelligent processing device (30) which provides instructions not only for sampling/collecting the tensile loaded member during the test but also for determining the length of the tensile loaded member and determining the stress to which the tensile loaded member is being subjected. The user is then given a visual readout (46
) and a record (48) by a printing machine, etc. Among the satisfactory visual readers are light emitting diode displays and liquid crystal displays. Contained within the intelligent processor (60) is a table containing information regarding the various tensile load members specified by the user. This table contains quantities describing the physical properties of various tensile loading members with respect to temperature changes and stress changes.

Determination of stress by the intelligent processor includes a variety of user input parameters, a self-contained table of values, and the application of measurement time intervals to Hooke's law. Hooke's law is given by the following equation g -3''5- where S - stress, △L = change in length due to applied load, E
= bullet recess (this is a function of temperature), and Lg - the actual load applied, such as the distance between the bolt head and the location where the nut screw receives the applied load. is the partial length of the tensile load member.

The grip length Lg is given by the user. Elastic modulus E
is calculated by the following equation.

E=E, )-cB(T-72). Here, EO = elastic modulus of a specific material at a temperature of 72 (22,2°C), OE
- the temperature coefficient of the elastic modulus, and T - the actual temperature at which the measurement is carried out (F).

Elongation or ΔL is the change in length due to the load applied to the tensile load member. This elongation is determined by an intelligent processor (30) from the time intervals obtained from the time interval measurement device (15).

This interval data includes interval measurements for unloaded tensile loaded members and loaded tensile loaded members. For each interval measurement, an intelligent processing and control unit determines the length of the response. The difference in these lengths gives ΔL or elongation.

The intelligent processor (30) determines the length of the tensile load member from the total pulse count in each sample set, the clock to which each pulse corresponds, and the number of samples in each sample set. The number of pulses provided to the intelligent processing unit (60) by the time interval measurement device (15) includes the total number of pulses counted and also a digital value representing the sum of the error signals for the sample set. The intelligent processing unit (30) converts this digital error amount into an equivalent number of pulses, which is added to the total number of pulses. In a preferred embodiment of the invention,
This number of pulses is directly used to determine the length of the tensile loaded member when unloaded and when loaded, taking into account sound speed differences due to temperature and stress changes. Alternatively, the number of pulses can be converted to a time interval, which can then be applied to the velocity of the ultrasound in a particular material and used to derive an equivalent length.

The operations performed on the data are described in more detail in attached transcript A. In general, these calculations are based on the extra length of the tensile loaded member due to temperature changes and the fact that ultrasonic shock waves traveling through a material of a particular form have a velocity that is a function of temperature and the fact that ultrasonic shock waves traveling through a material under stress This takes into account the fact that the velocity of the shock wave varies as a function of the stress to which the material is subjected. Furthermore, since the tensile load member has several different stress regions, the sound velocity factor used must naturally also be corrected for this.

The details carried out to derive the length and stress information by the intelligent processing unit (30) K are set out in Appendix AK.

A preferred embodiment of the invention will now be described in further detail with particular reference to FIGS. 3 and 4.

3 and 4 are simplified schematic diagrams of the preferred embodiment of the present invention. In this preferred embodiment, the intelligent processing unit includes a microcomputer (110). The first clock reference signal is called a transducer (1), and the second clock reference signal is called a transducer (2). As used below, the terms PUP(1) and ptrp(2) N refer to pull-up voltage (1) and pull-up voltage (2), respectively. R8T
(1) When starting the whole system, the intelligent processing unit (
30) to the timed borehole device (15). In the pulse generation circuit (14), a capacitor (i oo) is connected via a resistor (102).
is charged to a very high voltage. Capacitor (100)
One end of the output series resistor (104) and the resistor (102
) is connected to one end of the The other end of the resistor (102) is connected to a high voltage source. The other end of the output resistor (104) is applied to the output end of the pulse generation circuit (14). The other end of the capacitor (ioo) is a silicon controlled rectifier (SOR)
(106) is connected to the anode. The cathode of the SCR is grounded, but its gate receives the input of the pulse generating circuit (14). The resistor (108) is a capacitor (i oo
) and 5OR (106) between the anode junction and ground. In operation, the capacitor (100) is brought to a high voltage through the resistor (102), and the 5OR (10
6). This discharge of capacitor (100) causes a large negative spike output from resistor (104). This is the activation signal (19) in Figure 2.
Then, S is added to the converter (12). 5OR(i
06) Id is activated to discharge the discharge container (ioo) by applying an appropriate signal to the gate. This gate signal is the main pulse and blanking circuit (36)
The actuation trigger signal (17) of FIG. 2 is applied from .

A detailed description of the invention of the transducer (12) K applied actuation ξ rus will now be given. The operation/ξ pulse is a pulse generation circuit (14), a main pulse/blank circuit (36), and a fixed delay circuit (34).
arises from interaction with As previously described, the fixed delay circuit (34) generates a start pulse at every id periodic interval.

Referring to FIG. 3, one circuit for generating this pulse is shown.

The D flip-flop (110) is clocked by the oscillator (1) and the D flip-flop (110) is clocked by the oscillator (1).
) is reset by the inverted output. The non-inverting output of the D Noritub flop (IIO) is connected to the OR gate (11
4) is connected to the input of the D flip-flop (112).

○R gate-1 (114) is also a D flip-flop (1
12). D flip-flop (
112) is clocked by the oscillator (2), and the counter (11
It is reset by the output of 6). Counter (116)
It is repeated by the signal provided by the uAND gate (iis). The signal given by the AND gate (11B) corresponds to the signal of the oscillator (2) when the output of the D flip-flop (112) is high.

The inverted output of the D flip-flop (112) is connected to the counter (1
6) is connected to the load input. In this way, when the inverted output of the D flip-flop is low, the counter (116)
is ordered to resume its counting. In a preferred embodiment of the present invention, the counter (116) is initially set to start counting from zero and provides an output pulse to the D-flip 70 tube (112) when 500 Hals have been counted.

In operation, the start signal R8T (1) is applied to the input of the 'D flip-flop (110) as soon as the system is started by the intelligent processing unit (30). Oscillator (1) K synchronized, D7 lip-flop (11
0) is brought to a high level. This high level is further input from the KOR gate (114) to the D flip-flop (112). This high level is the oscillator (2)
It is transferred to the non-inverting output of the D Noritub flop (112) in synchronization with. This high level transition of the non-inverting output of the D flip-flop (112) lowers the inverting output. This also causes the D flip-flop (112) to be reset. At this point, the D Noritub flop (112) remains high. The reason is D 71) Rough Flor Rough (11)
2) A high bell at the output end. R/7'-t (114
) is re-inputted to the input of the D clip 70 tube (114).

When the non-inverting output of the D flip-flop (112) becomes high, the AND game (118) applies the signal of the oscillator (2) to the counting power of the counter (116). At this point, the counter (116) is connected to the above-mentioned D clip 70 tube (110).
It has already been initialized to Cero by resetting.

The counter (116) then counts 5 [10 cycles] of the oscillator (2). The counter then resets the D flip-flop (112). D flip-flop (
This reset of the D flip-flop (112)
) causes a zero to be output from the non-inverting output of the counter (116), and the D-Norbit flop (112) further removes the clock pulse of the oscillator (2) from the counting input of the counter (116).

Counter (116) is thus disabled.

Counter (116) D flip-flop by K (112
) reset is D flip float two! A high level output is generated from the inverted output of (112). Until this point D
Flip-flop (110) is disabled.

When a high level is applied to the reset input of the D flip-flop (110), the non-inverted output of the D flip-flop (i io) can take a high level when the next clock signal ξcis of the oscillator (1) arrives. It becomes possible. Due to this,
The non-inverting output of the D flip-flop (112) is made high, which also causes the counter (116) to start counting anew.

The signal present in the non-inverting output of the D flip-flop (110) is thus shaped by the non-inverting output of the D flip-flop (112). D flip-flop (11
When the non-inverted output of 0) goes high, the D flip-flop (112) causes the KD flip-flop (110) to reset after % clock pulse cycles. In the preferred embodiment of the invention, this interval is 50 nanoseconds. This means that the frequencies of vibrator (1) and vibrator (2) are I
This is because OMH2K is selected.

Since the oscillator (1) is 180° out of phase with the oscillator (2), the high level at the non-inverting output terminal of the D flip-flop 70 tube (1'10) will change to the high level at the non-inverting output terminal of the D flip-flop (1'10) after 50 nanoseconds.
12) Transferred into the inside. Therefore, the D flip-flop (1
50 nanoseconds elapse from when the non-inverted output of 10) goes high until the inverted output of D flip-flop (112) resets the D-flip 70 knob (110). .

The non-inverted output of the D flip-flop (110) is connected to the D flip-flop (120) in the main pulse and blanking circuit (66).
) is connected to the clock input of the The signal present in the non-inverting output of the D flip-flop (110) is the activation signal mentioned above.

The main ξ russ and blanking circuit (36) is the ξ russ generating circuit (
14) as well as a blanking signal to the receiver and amplifier circuit (16). The derivation of the actuation trigger signal will now be described. D flip-flop (120
) is clocked by the activation signal from the fixed delay circuit (filter 4). The input to D flip-flop (120) K is kept high by PUP 2 or pull-up voltage (2). D Flip Flop (120) A high level is applied to the non-inverting output of the D Flip Flop (120) for each positive pulse edge applied to the vine lock input. The non-inverting output of the D'' flip-flop (120) is connected to the input of the D flip-flop (122) oRk-).
(124). The inverted output of the D flip-flop (122) is also connected to the input of the D flip-flop (122) via an OR gate (124). Inverted output I of D flip-flop (122)
Connected to the reset input of the D flip-flop (120). The clock for the D flip-flop (122) is provided by the oscillator (2).

For each activation signal from the fixed delay circuit (34), the D7 lip-flop (120) provides a high level at its non-inverting output. This high level is further increased by the oscillator (2
) K is synchronized and clocked into the D flip-flop (122). The high level is a D flip-flop (122
) is applied to the D flip-flop (122
) causes the D flip-flop (120) to be reset.

At this point, the D flip-flop (120) is ready to receive the next activation signal provided by the fixed delay circuit (34). The non-inverting output of the D flip-flop (120) is thus forced low. The non-inverting D flip-flop Flo2' (122) is a D flip-flop (12
2) is maintained at a high level because its input is connected to its output via an OR gate (124).

The non-inverting output of the D flip-flop (122) indicates that this flip-flop is connected to the clock circuit (38) and down-counting decoder (
139) remains at the high level until reset by a reset signal provided from 139).

When the inverted output of the D flip-flop (122) is low, the NAND gate (126)
) outputs a high level to the 5OR (101S) gate. This is the activation trigger signal. This is 5CR (1
06) to discharge the capacitor (100). The transducer is thus provided with an actuation pulse.

In a preferred embodiment of the invention, a decoder circuit (139
) to the D flip-flop (122) occurs approximately 1 microsecond after the D flip-flop (120) is reset, ie, 1 microsecond after the activation trigger signal is sent. The decoder circuit (139) includes a set counter that is activated whenever an activation ξ pulse is sent. When the setting counter counts zero, the decoding circuit (139) outputs a reset signal to the D flip-flop (122) K.

In a preferred embodiment of the invention, the activation trigger signal therefore has a pulse width of approximately 1 microsecond and is activated by the activation signal from the fixed delay circuit (34).

The blanking function of the main pulse blanking circuit (36) is used by the receiver/amplifier (16) K to specify a window within which the time interval measuring device (15) examines the waveform sent from the converter (12).
A blanking signal is given to the target. D flip-flop (128
) is connected to the non-inverting output of the D flip-flop (122) via 0R (130). In this way, when the non-inverting output of the D flip-flop (122) goes high, the non-inverting output of the D flip-flop (128) goes high.

The 0R gate (130) is still a control/input circuit (42)
It also receives signals from This signal is sent to a positive/negative converter (13
2) is inverted. This signal (d) is generated according to the information provided by the intelligent processing unit (30) K and represents a time interval after which a reverberation signal is expected to occur.

Inverted output of D flip-flop (128) 'fiAND
D flip-flop (1
It is connected to the input of filter 4). AND game'-1 (1ro6)
The other input is provided by the pulse receiver circuit (18). The operation of the AND gate (i36) is applied to the D flip-flop (134) K in synchronization with the oscillator (2). The D flip-flop (134) is connected to the inverted output of the D flip-flop (134) in synchronization with the oscillator (2).
A low level clocked in appears. The non-inverting output of the D flip-flop (12,8) and the pulse receiver (1
When the signals from 8) are both high, the D flip-flop (
A low level appears at the inverted output of 134). If any of the above signals is low, a high level is clocked into the inverted output of the D flip-flop (134). The inverted output of the D flip-flop (134) is the D flip-flop (134).
128). Therefore, the D flip-flop (128) is the D flip-flop (13
4) is reset when a low level is present at the inverted output.

The inverted output of the D flip-flop (128) is provided to the AGO input of the receiver and amplifier circuit (16) via a converter (138). When a high level is present at this AGO input, the receiver and amplifier circuit (16) is turned on. When a low level is applied to the AGO input, the receiver amplifier (16) is turned on, but when the inverted output of the D flip-flop (128) is high, the receiver-amplifier circuit (16) is turned off. be made into

In operation, the signal applied to the clock input of the D flip-flop (128) is
) as a result of reducing the inverted output of the positive/negative converter (138)
provides a high level to the AGO input of the receiver and amplifier circuit (16). These signals are transferred to the receiver/amplifier circuit (16)
opens a window to examine the signal from the transducer (12). AND game) The signal entering (136) closes this window. This is because when a high level is output from the AND gate (136), a high level is given to the non-inverting output of the D flip-flop (134) in synchronization with the oscillator (2). This results in a D flip-flop (134
)'s inverted output takes a low level. Furthermore, this causes the inverted output of the D flip-flop (138) to go high, causing the AG of the receiver/amplifier circuit (16) to
The D flip-flop (128) is reset so that the level applied to the O input is low. This will close the window.

The AND gate (134) provides a high level to the D flip-flop (134) when a high level is received from the ξ pulse receiver circuit (18) and when the non-inverting output of the D flip-flop (128) is high. . The actuation trigger circuit therefore opens the window of the receiver and amplifier circuit (16), which is similar to what the intelligent processor signal provided from the positive/negative converter (132) does. Additionally, an actuation signal or a reverberation signal from the transducer is received and processed by the pulse receiver to cause the window to close.

The signal from the pulse receiver (18) is always at a high level when received from the active-ξ-Rus or echo-ξ-Ruscani transducer (12).

These windows (27a) in the blanking signal (27) K (
27b) is shown in FIG. Blank signal (27a
) corresponds to a high level reception from the D flip-flop (122). The falling edge of the blanking signal (27a) is the AND signal obtained from the pulse receiver circuit (18).
(136) Corresponds to receiving a high level at the input. The rising edge of the blanking signal (27b) corresponds to the reception of the low pulse obtained from the ff1l control and input circuit (42), and this reception indicates that the time at which the echo/ξ pulse is expected to occur has arrived. show. Blank signal (2
The falling edge of 7b) corresponds to the fact that the echo signal 75 is actually received by the pulse receiver (18) K, and the reception of this signal causes the AND gate (136) K to be connected to the pulse receiver (18) ) is given a high level.

The reception and processing of signals from the transducer (12) will now be described with reference to FIG. The receiver and amplifier circuit (16) includes a signal conditioning stage, an amplifier stage, and a level transfer stage.

The signal conditional is received at the stage by one end of the capacitor (140) from the converter (12).

The other end of the capacitor (140) is one end of the resistor (142), the anode of the diode (140), and the diode (146).
and the input of the amplifier stage (148).

The other end of the resistor (142) is grounded, just as the cathode of the diode (144) and the anode of diode-1'' (146) are grounded.
40) and the resistor (142)...
By providing a filter function, DC voltages are blocked, but high frequency phenomena are allowed to pass through. diode(
144) (146) keeps the level applied to the amplifier section (148) at a peak-to-peak value below a few volts. This retention is done because there are very large variations in the amplitude of the signal from the transducer (12). For example, the signal from the transducer (12) corresponding to the actuation signal has a level of several tens of volts, while the level corresponding to the echo pulse (d) is of the order of a few tenths of a volt.

The input signal thus maintained is provided to an amplifier stage (148). The amplifier stage includes a high frequency amplifier capable of handling transients in the nanosecond rise time domain. The amplifier section also has an automatic gain control (AGO) that allows the amplifier to be turned on and off. As mentioned above, the AGO input blanking signal is provided from the main pulse and blanking circuit (lo 6).

The output of the amplifier stage is provided to a level transfer stage.

Connect the output of the capacitor (150) l″i amplifier (148) to the junction of the resistors (152) (154). The other end of the resistor (152) is grounded;
) is connected to the base of the transistor (156). The emitter of transistor (156) is grounded, while the collector of transistor (156) is connected to resistor (158).
) and the input of the pulse receiver (18). The other end of resistor (158) is connected to a DC power source of approximately 4.5 volts.

In response to the signal from the amplifier (142), the rail transfer circuit outputs 0 volts and 4.5 volts to the signal receiving circuit (18).
Outputs a signal between volts.

This level-shifted output is received by the Schmitt trigger circuit (160) K in the pulse receiving circuit (18). These circuits square the received signal to provide sharp rising edges to the receiving circuit (162). Receiving circuit (16
2) is a repetitively triggered "single shot" multiple oscillator which outputs a single ξ pulse of varying width depending on the number of pulses obtained from the Schmitt trigger (160). In a preferred embodiment of the invention, this pulse width is about 6
More than a microsecond.

The output of the receiver (162) is sent to the blanking circuit (
36) provides a signal that can close the window generated within. The ξ pulse duration of the output of the receiver (162) is such that the transient following the initial rising edge of the signal received from the receiver-amplifier circuit (16) causes no change in the output of the receiver circuit (162). Selected long enough to make it tough. In this way, unwanted transient signals are rejected. Therefore, in operation, the receiving circuit (162
) is connected to the converter circuit (12) by the receiver/amplifier circuit (16).
), the blanking circuit (36) provides a K high level when an activation signal or a phantom echo signal is received from the blanking circuit (36).

The output of the receiver (162) is also the D-flimp Flossoff (
164) and the clock input of the D-flip 70 (166). The input of the D flip-flop (164) is connected to pUP2. Therefore, its inverted output is given a high level when the receiving circuit (162) provides a rising edge to the clock output of the D flip-flop (164). The input of the D flip-flop (166) is connected to the non-inverting output of the D-flip 70 tube (164). Both flip 70 tubes are main/ξ rus and blanking circuits (
36) is reset by the low level obtained from the inverted output in the D flip-flop (120). The pulse from the fixed delay circuit (24) is D-flip 70 tubes (120
Recall that the inverted output of D-flip 70 (120) is low when applied to the clock input of ). This corresponds to the actuation trigger signal. Therefore, both D flip-flops (164) and (166) are reset when the activation signal is generated. Therefore, each cycle in which the actuation signal and the echo signal are generated, the operation of the D-flip 70 (164) (166) is reset and a new operation is initiated.

In operation, the first clock of a new cycle received by the D flip-flop (164) corresponds to the activation signal. Since both the D flip-flops (BS4) (166) have been reset prior to receiving this actuation signal clock, the inverted output of the D flip-flop (164) is low, and this low level causes the D flip-flop (166) to be activated by the actuation signal. ) is input to the clock. This actuation signal causes a high level to be applied to the non-inverting output of the D flip-flop (164). This high level then connects the D flip-flop (166) as soon as there is a reception of a clock pulse or echo of the clock pulse.
given from time to time. D flip-flop (166)
The non-inverting output of therefore assumes a high level only after two consecutive pulses have been received from the transducer (12) within the current interval of actuation signal and echo signal.

The non-inverted output of the D flip-flop is given not only to the input of the iD flip-flop (168) but also to the error detection circuit (20). The D flip-flop (168) provides a counting adjustment signal not only to the sequence control circuit but also to the error storage circuit (22).

The non-inverted output of the D-flip 70 knob (166) represents the point in time indicating that an echo signal has been received. The signal in Figure 2 (
29). From Figure 2, this signal (29)
It is understood that the duration of . . . continues until the next activation signal is generated. . This is to prevent the secondary reflected signals received from the transducer (12) from influencing the time interval measuring device (15).

The error detection circuit (20) is a D flip-flop (166)
receive the non-inverted output of The error detection circuit (20) detects the time when the echo signal is received as instructed and the reference vibrator (i).
Recall that H2) measures the time interval between specific states. D flip 7 Rozzo (1
The input of 70) is ptrp 2 K connected, as is the input of D flip-flop (172). The non-inverting output of the D flip-flop (170) is the non-inverting output of the D flip-flop (170).
4) is connected to the input. D flip-flop (172
) is connected to the input of a D flip-flop (176). The clock input of the D flip-flop (174) is connected to the transducer (2) K, while the clock input of the D flip-flop (176) is connected to the camera (1).

In the preferred embodiment of the invention, the reference clock state used to indicate the end of a false interval is chosen to be the rising edge of each clock. Therefore, D flip 70ff (174
) and D-flip 70 knob (176) are selected to respond to the rising edge of transducer (2) and transducer (1), respectively. The inverted output of the D flip-flop (174) is connected to the reset input of the HD flip-flop (170), but the inverted output of the D flip-flop (176)
The inverted output of [D] is connected to the reset input of the flip-flop (172). Therefore, Frituzo 70 Tsubu (166
) becomes high, the D flip-flop (17
0) and the non-inverting output of the D flip-flop (172) are given a high level.

This high level is applied to the D flip-flop (174) until the oscillator (2) provides a rising edge to the clock input.
input to the non-inverting output of the clock (no bow).

D flip-flop (176) The same can be said about K. That is, the vibrator (1) is a D flip-flop (176
) until a rising edge is applied to the clock input of D flip-flop (176). The vibrator (2) is
Since the phase is shifted by 180° with respect to the oscillator (1), the points at which the non-inverted outputs of the D flip-flops (174) and (176) take a high level differ by % clock cycle. This means that the D flip-flop (176) is reset by one clock cycle before or after the D flip-flop (174) is reset. When the D flip-flops (170) (172) are reset, their non-inverted outputs go low.

The signal at the non-inverting output of the D flip-flop (170) thus represents the time between reception of the echo signal and the subsequent first rising edge of the oscillator (2). The signal at the non-inverting output of the D-flip-flop (172) therefore corresponds to the time interval representing the time between the reception of the echo-mires and the subsequent first rise in the waveform of the transducer (1). These two outputs are then applied to an OR gate (178). Therefore, D flip-flop (170) or D flip-flop (17
2) is high and D flip 70 knobs (17
As long as either 0) or D flip 70 knob is high, O
The output of the R gate (I78) becomes high. Therefore OR
The output of the gate gives the longer of the two measured false time intervals. This error signal is sent to the error storage circuit (22)
K is used to obtain the average error over a large number of samples.

To provide compensation for using oscillator (1) or oscillator (2) as a basis for calculating the total ξ Lus count, an additional circuit is provided as follows. AND game as input)
(180) receives the inverted output of D flip-flop (170) and the non-inverted output of D flip-flop (172). The output of the AND gate (180) is applied to the clock input of the D flip-flop (182).

NAND gate (184) has D flip 70 as input
The non-inverting output of the flip-flop (172) and the D flip-flop (1
72). NAND gate (18
The output of 4) is given to the reset input of the D flip-flop (182). D flip-flop (182) K
The input for is connected to PUP 2.

Also, when the D flip-flop (170) is reset by the D flip-flop (174) K,
The non-inverting output of the D flip-flop (182) is transferred to a high level, and at the same time the D flip-flop (172)
The non-inverting output of is made high. D flip-flop (18
The clock input of 2) is responsive to rising edges. Therefore, the time point at which the D flip-flop (170) is reset by the D flip-flop (174)K determines the time point at which the non-inverting output of the D flip-flop (182) transitions to a high level. On the other hand, if the D flip-flop (170) is reset before the D flip-flop (170), no four clock pulses will be provided to the D flip-flop 70 (182).

A reset signal is provided from the NAND gate (184), which occurs when there is a falling edge of the signal.

This falling edge indicates that the condition in which either the non-inverting output of the D-flip-flop (170) or the inverting output of the D-flip-flop (172) is at a low level means that the D-flip-flop (1
70) non-inverting output and D flip-flop (172)
is applied to the reset input of the D flip-flop (182) when the inverted outputs of the D flip-flop (182) both transition to a high level. This is a D flip-flop (1,72)
This occurs whenever D-flip 70 is reset before D-flip 70 (170). This corresponds to a case where the false time interval based on the transducer (2) is longer than the false time interval based on the transducer (1).

Therefore, the non-inverting output of the D flip-flop (182) is
If the time interval based on oscillator (1) is longer than the time interval based on oscillator (2), the time interval based on oscillator (2) is clocked at a high level, and the time interval based on oscillator (2) is If the interval is longer than the time interval based on transducer (1), then Kid;
will be reset. NAND gate (186) has D
The non-inverting output of flip-flop 70 (182) and the non-inverting output of D flip-flop (172) are provided. NA
The output of the ND gate (186) is the D flip-flop (1
88). The inverted output of the D flip-flop (iss) is the D flip-flop (188
) is connected to the input of In this configuration, the non-inverting output of the D flip-flop (188) is connected to the NAND gate (186).
Alternate between high and low levels with each successive ξ rus from. The output of the NAND gate (186) is such that the non-inverting output of the D flip-flop (172) is high and the D
When the state where the non-inverting output of the flip-flop (182) is high changes to the state where either one of these is low, K1-1
, giving the necessary positive transition.

This means that the incorrect time interval based on the oscillator (1) is the oscillator (
2) Occurs when the time interval is longer than the standard.

The non-inverted output of the D flip-flop (188) is provided to a counting control circuit (26) K. This output is the oscillator (1)
When the false time interval based on the oscillator (2) is longer than the false time interval based on the transducer (2), the high level and the low level are alternated. In this way, the counting control circuit (26) K
On the other hand, instructions are given. and f'L are then used to subtract clock pulses from the pulse counting function to accommodate the use of different reference signals in pulse counting as described above.

The actual method of subtracting one pulse from the pulse count is performed in the counting control circuit (26). The NAND gate (190) receives input signals from the non-inverting output of the D flip-flop (182), from the non-inverting output of the D flip-flop (172), and also from the non-inverting output of the D flip-flop (188). NAND gate (19
2), the non-inverting output of the D flip-flop (176) is D
It receives the same input as the NAND gate (190) receives, except that it is provided in place of the non-inverting output of the flip-flop (172). NAND gate (
194) is input from the non-inverting output of the D flip-flop (182) and the non-inverting output of the D flip-flop (174). NAND gate (190) (192) (19
The outputs of 4) are combined into one D flip-flop (1
96). D flip-flop (19
A pull-up resistor (191) is connected between the input of 6) and the positive voltage source.
is connected. The D flip-flop (196) is set by a signal from the main pulse and blanking circuit (36) and the non-inverting output of the D flip-flop (120). In this way, the D flip-flop (19
The non-inverted output of 6) is set to a high level when the activation trigger signal is output from the main/ξ pulse/blank circuit (66). The clock input to the D flip-flop (196) is provided from the output of the AND game (198). AND game) (198) input is vibrator (1)
and the output of the D flip-flop (196). Therefore, when the non-inverting output of the D flip-flop (196) is high, the AND gate (196)
) passes through the D flip-flop (196)
clock input.

Otherwise, when the non-inverting output of the D flip-flop (196) is at a low level, the clock pulse cannot pass to the input of the D flip-flop (196).

Non-inverting output of D flip-flop [NAND gate (2
00). NAND gate (200)
Other inputs to the oscillator (2) are provided by the oscillator (2). When the non-inverting output of the D flip-flop (196) is high, N
(200) passes the transducer signal. The setting signal from the main/ξ pulse/blank circuit (36) is NA
This non-inverting output is initially set so that the ND gate (200) reaches the high level necessary to pass the signal of the vibrator (2). NAND gate (190) (192
) or (194) to convert the D flip-flop (196
) by timing the insertion of a zero level at the input of the NAND game ) (
200) can be determined.

NAND (190) (192) (194) checks the state of the circuit in the error detection circuit (2o) and determines that the error time interval based on the oscillator (2) is longer than that for the oscillator (1). causes a low level to be inserted at the input of the D flip-flop (196) when the D flip-flop (182) is reset. At this point, the oscillator (2)
corresponds to the end of the false interval. Further, when the error interval with respect to the oscillator (1) is longer, a low level is inserted at the input of the ld, D flip-flop (196). However, in this case this low rail is inserted after a further -clock cycle for the recess sample with reference to transducer (2).

The output of the NAND gate (200) is applied to the "count up" clock input of the counter (202) found in FIG. A counter (202) accumulates pulse counts corresponding to all samples taken within the sample set.

, Returning to FIG. 3, the error storage circuit (22) will be explained. The false time interval signal provided by the OR gate (178) of the error detector circuit (20) is provided to one end of the resistor (204) and to the anode of the diode (206). Resistor (204
) is connected to a positive voltage source, but the other end of the diode (206
) is connected to the capacitor (208) and the error amplifier (21).
0) and the output of the NOR gate (212).

The false time interval provided by OR gate (178) charges capacitor (208) to a positive voltage through resistor (204) and diode (206). The time interval corresponding to the error signal from the OR gate (17B) determines the voltage at which the capacitor (208) is charged. When the output of the OR gate (178) returns to zero, the diode (2
06) prevents the capacitor from discharging. In this way, the voltage on the capacitor (208) is passed through the error amplifier (210) to the analog-to-digital (A/D) converter (40).
It is maintained in preparation for subsequent sampling after K, or in preparation for receiving an additional voltage corresponding to the next sampled error interval. The amplifier (210) is an amplifier with high input impedance and high gain, and its output is A/
Connected to the input of the D converter (40).

Capacitor (2) for output of NOR gate (212)
The connection 08) is made in order for K to discharge the capacitor (208) whenever a new sample set is desired to be taken. The NOR gate (212) is activated when the intelligent processing unit (30) provides a positive interrupt signal via the sequence control circuit (32) or when the pulse receiver circuit (18)
) When the non-inverting output of the D flip-flop (168) in K goes high, the capacitor (208) is discharged. In the latter case, this positive waveform represents the case where the activation signal is sent before the echo signal flip-flop (166) is reset.

This condition corresponds to an invalid sample sequence.

In the sequence control circuit (32), an intelligent processing device (
An interrupt signal from K (30) is received and an interrupt request signal is provided to the intelligent processing unit (30) K. Intelligent processing device (
The interrupt signal coming from the D flip-flop (214)
) and is received by converter (216) K. This causes the inverted output of the D flip-flop (214) to take a high level.

This high level is applied to the input of the D flip-flop (218) and immediately before the next actuation trigger pulse from the fixed delay circuit (34) is generated.
18).

When the non-inverting output of the D flip-flop (218) takes a high level, this high level is applied to the input of the D flip-flop (220) via the OR gate (222).

This high level is synchronized to the oscillator (1) and clocked against the non-inverting output of the D flip-flop (220). D
The non-inverting output of the flip-flop (220) is connected to the input of the OR gate (222) and the input of the AND (224). This connection to the input of the OR gate (222) allows the non-inverting output of the D flip-flop (220) to remain high even after the D flip-flop (218) has gone low. AND gate (224)
id counter (226) controls the counting sequence in K that determines whether a sufficient number of samples have been taken to constitute a valid and complete sample set.

The counter (226) is preset to start counting from zero upon arrival of the load signal coming from the inverted output of the D flip-flop (218). AND gate (224
) is the output of the counter (226).
up) input and connected to the D flip-flop (220)
starts counting when the non-inverted output of is high and a high level is applied to the OR gate (228).

OR gate (228) is D flip-flop (168)
When the inverted output of the D-flip 70 tube (120) is high and the non-inverted output of the D-flip 70 tube (120) is high, or
When the non-inverting output of (168) is high, the non-inverting output of D flip-flop (170) is high, or the non-inverting output of D flip-flop (172) is high.
Give a high level. In other words, when the activation signal is generated and the D flip-flop (168) is not in reset mode, or when the D flip-flop (168)
D flip-flop (17) is in reset mode.
0) When either of the U or D flip-flops (172) receives an indication from the pulse receiver that a reverberation signal has been received, K is legitimately sampled.

In this way, the counter (226) is provided with a count up signal for each sample taken. In this case, each sample represents the reception of an actuation signal and a reverberation pulse.

When the counter (226) achieves its intended count value, the D flip-flop (
220) is reset. D flip-flop (22
This reset of D flip-flop (22
0) is made to take a high level, which further resets the KD flip-flops (218) (214). Additionally, this clocks a high level at the non-inverting output of the D flip-flop (232). This blanks the counter (226). The inverted output of the D flip 70 tube (232) is provided to the drive input of the A/D converter (40). This is the A/D conversion INK capacitor (2
08) Takes a sample of the voltage present and commands that the analog voltage be converted to an equivalent digital word. The output of the converter (216) is a D flip-flop (234).
clock input.

The input of the D flip-flop (234) is provided from PUP2. A high level is transferred to the non-inverting output of the D flip-flop (234) in response to the positive output provided by the number converter (216). D flip-flop (
This positive output from the D flip-flop (234)
32), the simultaneous KOR key (2) is reset.
36) provides an interrupt request signal to the intelligent processing unit (30).

The output Renstar circuit (24) will now be described with reference to FIG. Output register (24) HA/D converter (40)
and stores it in the launch (238). The .xi.rus count value from the NAND (200) is given to the up count input of the counter (200). Counter (2
The output of 02) is applied to the latch (240), and the output of the latch (240)
K is held 7'L.

A call decoding circuit (28) receives call data from an intelligent processing device (30), e.g.
8) decode to drive a specific latch, such as (248).

A latch (242) in the control and input circuit (42) receives blanking interval data from the U-intelligent processing unit (60).

This blanking interval data is then applied to preset the counter (244). Count! The clock for (244) is given from the counting control circuit (26). More specifically, the D flip-flop (246) is the D flip-flop (12) in the main pulse and blanking circuit (36).
2) receives a clock signal from The input of the D flip-flop (246) is connected to PUP 2, and the non-inverting output of the D flip-flop (246) is connected to the AND gate (2
48). The other input of the AND game (248) is connected to the vibrator (1). The reset input of the D flip-flop (246) is connected via a converter (250) to the output of a counter (244) in the control and input circuit (42).

Whenever an output is generated from the counter (244), the D-flip 70 knob (246) is reset. This forces the non-inverting output of the D flip-flop (246) to go off the rails, which further prevents the oscillator (1) from passing through the AND gate (248). This in turn disables the clock input to the down count input of the counter (244) and the counter (244) stops counting.

This down counting clock is a D flip-flop (246)
When a positive level is given to the clock input of
It is applied again through the gate (248). In other words, when the operation start signal is generated, the counter (244
) is disabled. The counter (244) counts down from the preset number given by the intelligent processor (3o) and outputs a high level when the count reaches zero.

This high level is then connected to the main/ξrus/blank circuit (36)
is received by the converter (132) of the circuit (36) and then the circuit (36)
anticipates the reception of the echo/zorus and activates the receiver/amplifier circuit (
16) Open the window.

The preset value provided by the intelligent processor to the counter (244) is the estimated time required for the echo signal to be received after the actuation signal is output once.

This estimate is a function of, for example, the length of the tensile load member, the material, the temperature, and the applied load.

In a preferred embodiment of the invention, the clock signal (38) is
Based on a 0 MH2 crystal (crystal) controlled clock. This clock is divided into two parts with a phase difference of 18 to generate a reference frequency for oscillator (1) and oscillator (2).
Shifted by 0°. These reference frequencies are then provided to the time interval measurement device (15) K. Clock circuit (3
8) is initialized by a reset signal from the intelligent processing unit (30).

FIG. 5 is a diagram illustrating the interaction between the intelligent processing and control circuit (30) and the time interval measuring device (15).

After the power boost stage (300), the intelligent processing unit (30) starts the internal circuits and then receives data from the user in the stage (302). This data includes the operating temperature, the units in which stress measurements are to be expressed, the group to which a particular tensile load member belongs, the type of tensile load member within that group, the approximate length of the tensile load member, and the user's There is a stress limit to be notified at the time of occurrence, a reference number for the particular tensile load member under test, and a grip length. Step (303
), an intelligent processing and control unit (30) retrieves data from the user from the storage device for processing.

Based on the above-mentioned data entered by the user, the intelligent processing device determines in stage (304) that, following the insertion of the actuation signal into the tensile load member under test, a Determine the approximate time it will take to complete the process. In stage (306), the intelligent processing and control unit (30) provides this time-spaced data to the time-spaced measuring device (15)K. This data is stored in the control/input circuit (4
2) K is incorporated (10aa).

This blanked data is then used by the time interval measurement device (15
) can be used.

After the blanking circuit is provided in stage (306), the intelligent processing and control device (60) controls the time interval measuring device by sending an interrupt drive signal to the sequence control circuit (32) in stage (312). Actual sample collection according to (15) is started. In stage (310), the intelligent processing and control circuit (32) determines whether an interrupt request signal (RQ) has been received from the time interval measuring device (15).

Until such an IRQ signal is received, the intelligent processing and control unit (30) advances through stages (314) K and returns to stage (310) in a "wait" loop. Time interval measuring device (1
Recall that the IRQ signal from 5) indicates that a valid and complete sample set has been obtained.

In stage (31,8) the intelligent processing unit sends the call data to the output register selection circuit (28). This data then allows the error count to be read from the output register (24) and the pulse count register (24). This .xi. rus count and error data are then used in step (320) to determine length and stress values for that particular tensile load member. These numbers are in the next row (322
) is displayed to the user and output. Stage (324) compares the measured stress magnitude to user-entered stress limits.

If a limit exceedance is observed, the intelligent processor will
26) to emit a warning sound. If no limit exceedance is observed, the intelligent processor advances to stage (314)K. At this stage, whether a new test and tensile loading member should be processed or whether the current sampling should be continued;
is determined. If a new test is to be started, the intelligent processor returns to step (303) K where user data is collected as described above.

In operation, the unloaded length of the tensile load member is first obtained. Following this, the length under stress of the tensile loaded member is determined, incorporating compensation for temperature, sound velocity changes, material effects on the sound velocity of the tensile loaded member, and other physical and ξ parameters that affect elongation measurements. . The length and stress values are determined by the intelligent processor according to the equations set out in Appendix A.

As the user increases the load on the tensile load member, the intelligent processor starts taking new sample sets with the time interval measurement device, obtains these new sample sets, and calculates the updated length. and stress, and notify the user of these values. In this way, the user receives an immediate, moment-by-moment indication as to the conditions to which the tensile load member under test is being subjected.

In this way the user can also precisely adjust the tensile loading member to the desired stress and elongation.

The terminology and designations used herein are for purposes of explanation and not limitation. In using these terms and expressions, there is no intention whatsoever to exclude equivalents or partial equivalents to the features illustrated and described, and various design changes may be made within the scope of the claims of the present invention. Please understand that it is possible.

Appendix A where P = total pulse counts for all samples obtained from the output register (24).

N = total number of samples in the sample set.

KD - A constant value indicating the inherent system delay.

KPl = pulse counting method adjustment constant.

EFIRONT = Erroneous count value in digital form given from the output register (24).

KP2 = constant for calculating the digital word to the equivalent average pulse amount per sample.

△T=T −7 However, T = temperature during the test measured by Mr. Ka.

Modulus of elasticity at T ET ET = EO - CE△T where the nominal elastic modulus of the material at -72° CB = temperature coefficient of elasticity coefficient of thermal expansion at T AT AT, = AQ - OA△T where Ao = '% nominal coefficient of thermal expansion of a member with a given tensile load.

Temperature coefficient of thermal expansion coefficient for OA-temperature T.

Sound velocity VTV at TK for a given tensile loaded member
T=VO-CT△T where VO=sound velocity O in tensile load member at 72°FK
T - Temperature coefficient of sound velocity where K = = Stress coefficient of sound velocity for a particular tensile load member.

Lg = Grip length for the specific application Stress on the tensile load member 5TRESSELONG x
ET STR[SS:□ Lg

[Brief explanation of drawings]

FIG. 1 is an overall block diagram of the present invention, FIG. 2 is a diagram showing timing and waveforms at representative points within the device of the present invention, and FIG. 3 is a partial diagram of a preferred embodiment of the device of the present invention. FIG. 4 is a simplified route diagram of a portion of the preferred embodiment apparatus of the present invention; FIG. 5 is a simplified route diagram of a portion of the preferred embodiment apparatus of the present invention; FIG. 1 is a flowchart illustrating a method by which stress information is obtained by . Time interval measuring device...15 Intelligent processing and control device...30 Patent attorney Yuki Yamazaki Tsuzuki Tsuzuki Amended Printed October 1987, Commissioner of the Japan Patent Office, 1. Indication of the case Patent Application No. 156477 of 1981 2 Title of invention Digital supersonic stress measurement method and device 3 Relationship with the person making the amendment Case Applicant name Title Sl-Resdell Corporation 4, Agent

Claims (1)

[Scope of Claims] (1) A device for measuring the length and stress of a tensile load member, wherein a transducer is activated to inject a supersonic pulse into one end of the load member, and the transducer is connected to the load member. The transducer receives the supersonic ξ lux reverberant sound reflected back from the other end, and the transducer converts the reverberant sound into an equivalent electrical signal, wherein the a time interval measuring device for obtaining an elapsed time corresponding to an interval until reception of a pulse echo sound; and a time interval measuring device for receiving the elapsed time data and data input by a user to control the time interval measuring device. and an intelligent processing and control device for deriving length, stress and other parameters describing the tensile load member from the elapsed time data and the user input data. (2. In the length and stress measuring device according to claim (1), an actuation signal indicating the beginning of the time interval is generated and indicating the end of the time interval. (3) A length and stress measuring device, wherein the time interval measuring device includes a time interval measuring device configured to receive a return signal of the length and stress. and a stress measuring device, the intelligent processing and control device including a general purpose digital computer, the computer providing control and timing signals to the time interval measuring device, and the computer providing control and timing signals to the time interval measuring device. a device for receiving elapsed time data from and for the calculator to further convert the elapsed time data into elongation and stress values; and a device for providing elongation and stress values to a user. Apparatus. (4) In the length and stress measuring apparatus according to claim (3), the digital calculator for the overall application also accommodates multiple tensile load members, operating temperatures, and operating stresses. (5) In the length and stress measuring device according to claim (3), the length and stress measuring device is provided with elongation values. and a length-responsive force measuring device, said device containing a visual indicator, which provides a stress value. (7) In the length reaction force measuring device according to claim (3), the length reaction force measuring device provides an elongation value and a stress value to a user. (8) A length and stress measuring device according to claim 3, wherein the device includes a light emitting diode reader. and the length and stress measurements, wherein the device for providing the stress values includes a liquid crystal display reader. The distance measuring device has first and second clocks, the second clock has the same frequency as the second clock, the second clock differs from the second clock by a predetermined phase difference, and a time interval measuring device for counting the number of cycles of the second clock occurring within the interval; and a time interval between reception of the pulse reverberation and occurrence of the determination state of the second and second clocks. an error detection device for detecting the distance; and a length and stress measuring device comprising: (]O)% In the length and stress measuring device according to claim (1), the intelligent processing device A length and stress measurement device that automatically evaluates the elapsed time data and includes adjustments for temperature effects and physical properties of the tensile load member material. 01) A device for measuring time intervals, wherein an actuation signal indicating the beginning of the time interval is generated and a return signal indicating the end of the time interval is received, the device measuring the time intervals determining the scheduled phase. a first reference signal having a predetermined phase and frequency, the second reference frequency being synchronized to the actuation signal; and a second reference signal having a predetermined phase and frequency. a second reference signal, the second reference signal having a frequency equal to that of the first reference signal, and the second reference signal differing from the first reference signal by a predetermined phase difference; and generating the actuation signal. a counting device for counting the number of cycles of the first reference frequency wave occurring between the reception of the return signal and the reception of the return signal; an error signal detection device for deriving an error signal for correcting the cycle count value to include the corresponding time until the reception of the return signal; A device for measuring an interval, a device for measuring an interval from reception of the return signal to subsequent occurrence of a determination state of the second reference signal, and an interval between the second reference signal interval and the second reference signal interval. A time interval measuring device, comprising: a device for selectively identifying the longer one; and a device for converting the cycle count value and the selected error signal into units of time. 0 ■ Claim No. (1) ), wherein the return signal has a plurality of zero crossings, and the time of reception of the return signal is equal to the first two zero crossings occurring within the received return signal. (1) In the time interval measuring device according to Claim No. (1η), the error signal detecting device derives a dynamic average error signal. A time interval measuring device which accumulates a significant number of error signals to be output. a counter for counting the number of cycles of the first clock that occur until reception of the return signal, the second clock being synchronized to the onset of the actuation signal and having a predetermined frequency; a stage for generating a second clock having the same frequency as the second clock and offset from the second clock by a predetermined phase; measuring a first clock interval to a particular state of the clock and a second clock interval from reception of the return signal to a subsequent particular state of the second clock; and selecting the longer of the second clock intervals; and compensating the selected clock interval for a phase difference between the second clock and the second clock; and the cycle count value. and converting the cycle count value and the compensated selected clock interval into units of time. α→ A method for measuring the time from the start of an actuation signal to the reception of a return signal according to claim 14, wherein the subsequent specified state in the clock interval measuring stage is determined by the time of the return signal. The occurrence of the first rising edge of a clock waveform following reception. (17) Length of tensile load member. and a method for measuring stress comprising activating a transducer to inject an ultrasonic pulse into the loaded member and receiving a subsequent ultrasonic pulse reverberation from the loaded member. a step for measuring the time interval from the time of incidence of the ultrasonic wave to the reception of a ξ Lus echo in the tensile loaded member under no load; A stage for measuring the time interval until reception of a pulse echo; a stage for converting the nuclear time interval of the member under no load to a reference length based on the sound speed factor; and a stage for converting the time interval of the member under load. When converting to length, this conversion is further used to calculate the change in the speed of sound in the material under stress.The stage adjusts the sound speed factor and is used to calculate the length of the tensile loaded member under stress. A method of measurement comprising: adjusting a sound velocity factor to apply; a transformation comprising: calculating a stress by applying Hooke's law to the difference between the reference length and the loaded length. (In the method for measuring length and stress described in the former claim (17), the difference between the reference length and the length under load is further considered as a temperature factor for length changes due to temperature effects. A method that includes steps to adjust based on.