JPS5955562A - Program loading system - Google Patents

Program loading system

Info

Publication number
JPS5955562A
JPS5955562A JP16586082A JP16586082A JPS5955562A JP S5955562 A JPS5955562 A JP S5955562A JP 16586082 A JP16586082 A JP 16586082A JP 16586082 A JP16586082 A JP 16586082A JP S5955562 A JPS5955562 A JP S5955562A
Authority
JP
Japan
Prior art keywords
program
processor
load
memory
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16586082A
Other languages
Japanese (ja)
Inventor
Ryoichi Ikeda
良一 池田
Kensaku Kinoshita
研作 木下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP16586082A priority Critical patent/JPS5955562A/en
Publication of JPS5955562A publication Critical patent/JPS5955562A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/445Program loading or initiating

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To avoid an increment of the number of ROMs, by distributing load processing programs to a common memory for plural processors and replacing a program which is under execution with an indicated program by processor received a load indication. CONSTITUTION:A CPU2, (n) units of input/output devices IOP3-1-3-n and a common memory CM5 are connected to a common bus 1, and the memory 5 receives an access from each IOP3. The CPU2 contains a processor 6 and a main memory MM7; while the IOP3 contains processors 8 and 10 and local memories LM9 and 11. A load processing program 12 and IOP programs 15-1- 15-n are loaded to the CM5. A processor received a load indication from the CPU2 replaces the program address which is under execution with the head address of the program 12 distributed on the CM5 and loads the programs 15-1- 15-n to the memories LM9 and 11 from the CM5. Thus a load processing program is shared to reduce the number of ROMs.

Description

【発明の詳細な説明】 〔発明の属する分野〕 本発明は複数のプロセッサから構成されるマルチプロセ
ッサシステムにおけるプログラムロード方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a program loading method in a multiprocessor system composed of a plurality of processors.

〔従来技術〕[Prior art]

マルチプロセッサシステムの構成として、複数のプロセ
ッサを単一の共通バスでコモンメモリに結合し、複数の
プロセッサがこのコモンメモリヲ共通にアクセスする構
成がとられる。このようなシステムでは、コモンメモリ
に各プロセッサ用のプログラムがファイル媒体からロー
ドされている。
A multiprocessor system is configured in such a way that a plurality of processors are connected to a common memory through a single common bus, and the plurality of processors commonly access this common memory. In such a system, a program for each processor is loaded into the common memory from a file medium.

実行にあたっては、各プロセッサ用のプログラムをコモ
ンメモリから各プロセッサが持つローカルメモリにロー
ドし、谷プロセッサは自ローカルメモリ内のプロ、ダラ
ムを実行する。各プロセッサ用のプログラムを口〜カル
メモリヘロードするロード処理プログラムは、書込み等
による破壊を防ぐため各プロセッサのリードオンリーメ
モリ(I(OM)上に格納されている。この韮うにロー
ド処理プログラムは各プロセッサのlt OMに格納し
ておく構成のため、ROM容量が増加し、メモリの宥効
利用が図れない欠点がある。またR OIVIであるた
め、デバグ効率が悪くなるといった欠点がある。
During execution, the program for each processor is loaded from the common memory to the local memory of each processor, and the valley processor executes the program and Durham in its own local memory. The load processing program that loads the program for each processor into the local memory is stored in the read-only memory (I (OM)) of each processor to prevent destruction due to writing etc. This load processing program is Since the data is stored in the ltOM of each processor, the ROM capacity increases and the memory cannot be used efficiently.Furthermore, since it is an ROIVI, debugging efficiency deteriorates.

〔発明の目的〕[Purpose of the invention]

本発明の目的は上述の欠点を除去し、メモリの有効利用
およびデバグ効率の向上を図るプログラムロー ド方式
を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a program loading method that eliminates the above-mentioned drawbacks, makes effective use of memory, and improves debugging efficiency.

〔発明の概要〕[Summary of the invention]

上記の「」的を達成するため、本発明はロート処理ブロ
クラムをコモンメモリに配置し、プログラムロー1・を
統括するプロセッサによりロード指示を受理したプロセ
ッサは現在英行中のプログラムアドレスをコモンメモリ
上に配置されたローl・処理プログ8ラムの先頭アドレ
スに置き換えてコモンメモリからプログラムロートを行
なうことをft徴とする。
In order to achieve the above object, the present invention arranges a rotary processing block in a common memory, and the processor that receives a load instruction from the processor that controls program row 1 stores the program address currently being processed in the common memory. The ft characteristic is to perform a program load from the common memory by replacing it with the start address of the row 1/processing program 8 program located in .

〔発明の実施例〕[Embodiments of the invention]

図は本発明の一実施例を示すブロック図である。 The figure is a block diagram showing one embodiment of the present invention.

図において、共通バス1に中央処理装置=(CI) U
 )2.0台の入出力処理装置(ft、)P)3−1〜
3−11およびコモンメモ+)(CM)5が結合され、
CM 5が共通にアクセスされるよう構成されている。
In the figure, common bus 1 has a central processing unit = (CI) U
)2.0 input/output processing devices (ft,)P)3-1~
3-11 and Common Memo +) (CM) 5 are combined,
CM 5 is configured to be commonly accessed.

CPU2はプロセッサ6およびCPU2のメインメモリ
(Ivl”M ) 7で構成され、I OP 3− ]
はプロセッサ8とローカルメモリ(L IVI ) 9
で、10 P 3− nは同様にプロセッサ10とL 
Mllで構成される。CM5にはファイル媒体からロー
ド処理プログラム12および各10 P用のプログラム
15−1〜+5−11がロードされて(・る。ロード処
理プロクラム12ば・@IQP用のロー1〜処理プログ
ラム13−1〜13− nを含んている。CP U 2
のプロセッサ6には各10 ))用のロードトリガン/
メタl7−1〜17−■】が設けられ、I OP 3−
1のプロセッサ8と1すP :3−nのプロセッサ10
にはそれぞれ、(fp LJ用のロードトリガレジスタ
I9.20、ロード処理プログラムの先頭アドレスを格
納ずろロードレジスタ21.22、プロクラムステータ
スレジスタ27.28が設けられている。CPU2のロ
ードトリガレジスタ17−1〜17−nからばIOPの
ロードトリガレジスタ19.20ヘロ−ドトリガ線23
、石が、I (J Pのロードトリガレジスタ19.2
0からはCPLIのロードトリガレジスタ17−1〜1
7− nヘロードトリガ信号線241.26がそれぞれ
橋続されている。
The CPU 2 is composed of a processor 6 and a main memory (Ivl"M) 7 of the CPU 2, and has an IOP 3-]
is a processor 8 and a local memory (L IVI) 9
Similarly, 10P3-n is the processor 10 and L
It is composed of Mll. The load processing program 12 and the programs 15-1 to +5-11 for each 10P are loaded into the CM5 from the file medium. ~13- Contains n.CPU 2
The processors 6 each have a load trigger for each 10))
IOP 3-
1 processor 8 and 1sP: 3-n processor 10
are respectively provided with a load trigger register I9.20 for (fp LJ), a zero load register 21.22 that stores the start address of the load processing program, and a program status register 27.28.Load trigger register 17- of the CPU 2 From 1 to 17-n, IOP load trigger register 19.20 Herod trigger line 23
, stone is I (J P's load trigger register 19.2
From 0, CPLI load trigger registers 17-1 to 1
7-n Herod trigger signal lines 241 and 26 are connected to each other.

次にrop3−1のプロセッサ8およびI OP 3−
nのプロセッサ1oカ自プロセッサのローカルメモリ9
および10へ各10 P用のプログラム15−1”−1
5−11をロードする動作について説明する。本ンステ
ムてはCP U 2のプロセッサ6がロードを統括する
プロセッサとされており、まず、プロセッサ6はI (
J P3−1へロード) l)ガ線2:うを使用してト
リガをがける。トリガを受けたI (J P 3−1の
プロセッサ8はロートレジスタ21に設定され  4た
I Of) 3−1用ロード処理グロクラム13−1の
先頭アドレスを、現在実行中のプロクラムの番地が格納
されているプロクラムステータスレジスタ27に置き換
える。これによってプロセッサ8は01〜45の特定番
地にあるIOP3−1、用ロード処理プログラム13−
1を実行し、これによってI OP3−1用プログラム
15−1をIOP:3−1のローカルメモリ9にロード
する。ロードが完了すると、プロセッサ8はロードトリ
ガ線24を使用してC1)U2のプロセッサ6ヘトリガ
をかける。ロード完了通知を受けたC P U 2のプ
ロセッサ6は以下l0P3−nまて上述の手順を繰り返
してロードを行なう。谷10Pではローカルメモリへロ
ードさ−Jtたプログラムを実行する。
Next, processor 8 of rop3-1 and IOP3-
n's processor 1o local memory 9 of own processor
and program for each 10 P to 10 15-1”-1
The operation of loading 5-11 will be explained. In this system, the processor 6 of the CPU 2 is the processor that controls the load.
JP Load to P3-1) l) Use the trigger wire 2: to activate the trigger. Trigger received I (Processor 8 of JP 3-1 is set in the rotor register 21.) The start address of the load processing program 13-1 for JP 3-1 is stored as the address of the program currently being executed. Replace it with the program status register 27. As a result, the processor 8 loads the load processing program 13- for the IOP3-1 located at specific addresses 01 to 45.
1 is executed, thereby loading the program 15-1 for IOP3-1 into the local memory 9 of IOP:3-1. When the load is complete, the processor 8 uses the load trigger line 24 to trigger the processor 6 of C1)U2. The processor 6 of the CPU 2, which has received the load completion notification, repeats the above-mentioned procedure until I0P3-n is loaded. In the valley 10P, the program loaded into the local memory is executed.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、ロート処理プログラムがコモンメモリ
に配置されるので、プロセッサの台数が多くなるほどl
t 01VI削減によるメモリの有効利用およびテバグ
効率の向上か大きくなる効果がある。
According to the present invention, since the rotary processing program is placed in the common memory, the larger the number of processors, the more
The reduction in t01VI has the effect of making effective use of memory and improving the bugging efficiency.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の一実施例〉示すブロック図である。 1 共通バス、2・中央処理装置(CPtJ、)、3−
1〜3−11  入出力処理装置(1(JP)、5・ 
コモ/メモ’)(CM)、6.8.10・・・プロセッ
サ、7− メ’l 7 /’ モリ(Ivl +ν1)
、9.10 ・= 0−カルメモリ。
The figure is a block diagram showing one embodiment of the present invention. 1 Common bus, 2 Central processing unit (CPtJ, ), 3-
1 to 3-11 Input/output processing device (1 (JP), 5.
Como/Memo') (CM), 6.8.10... Processor, 7- Me'l 7/' Mori (Ivl +v1)
, 9.10 ・= 0−cal memory.

Claims (1)

【特許請求の範囲】[Claims] (1)  複数のプロセッサと、該複数のプロセッサが
共通にアクセスできるコモンメモリを単一の共通バステ
結合したマルチプロセッサシステムにおいて、上記プロ
セッサの一つはプログラムロードを統括するプロセッサ
であり、該統括プロセッサによりロード指示を受理した
プロセッサは現在実行中のプログラムアドレスを上記コ
(ンメモリ上に配装置されたロード処理プログラムの先
頭アドレスに置き換えて上記コモンメモリからプログラ
ムロードを実行し、ロード完了により上記統括プロセッ
サへロード完了を通知することを特徴とするプログラム
ロード方式。
(1) In a multiprocessor system in which a plurality of processors and a common memory that can be commonly accessed by the plurality of processors are combined into a single common bus step, one of the processors is a processor that controls program loading, and the The processor that has received the load instruction replaces the address of the currently executing program with the start address of the load processing program allocated on the above common memory, executes the program load from the above common memory, and upon completion of the load, the processor A program loading method characterized by notifying completion of loading.
JP16586082A 1982-09-22 1982-09-22 Program loading system Pending JPS5955562A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16586082A JPS5955562A (en) 1982-09-22 1982-09-22 Program loading system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16586082A JPS5955562A (en) 1982-09-22 1982-09-22 Program loading system

Publications (1)

Publication Number Publication Date
JPS5955562A true JPS5955562A (en) 1984-03-30

Family

ID=15820360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16586082A Pending JPS5955562A (en) 1982-09-22 1982-09-22 Program loading system

Country Status (1)

Country Link
JP (1) JPS5955562A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148354A (en) * 1986-12-12 1988-06-21 Nec Corp Initial program loading system
JPS63233460A (en) * 1986-11-20 1988-09-29 アルカテル・エヌ・ブイ Method and circuit device for loading initial program loader to secondary computer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63233460A (en) * 1986-11-20 1988-09-29 アルカテル・エヌ・ブイ Method and circuit device for loading initial program loader to secondary computer
JPS63148354A (en) * 1986-12-12 1988-06-21 Nec Corp Initial program loading system

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