JPS5954233A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPS5954233A
JPS5954233A JP16447082A JP16447082A JPS5954233A JP S5954233 A JPS5954233 A JP S5954233A JP 16447082 A JP16447082 A JP 16447082A JP 16447082 A JP16447082 A JP 16447082A JP S5954233 A JPS5954233 A JP S5954233A
Authority
JP
Japan
Prior art keywords
layer
substrate
thick
integrated circuit
thick film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16447082A
Other languages
Japanese (ja)
Inventor
Kenji Furuya
賢二 古屋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16447082A priority Critical patent/JPS5954233A/en
Publication of JPS5954233A publication Critical patent/JPS5954233A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To solder a lead onto a thick-film circuit positively by forming the thick-film circuit on an insulating substrate, plasma-ashing a fouling and foreign- matter depositing layer generated on the circuit and the substrate and removing the ashed substances through ultrasonic washing using a washing liquid. CONSTITUTION:Conductor layers 2, 22, 32, 42 are formed on the insulating substrate 1 washed sufficiently through screen printing, a section extending over the end section of the layer 32 from the surface of the substrate 1 exposed from the layer 42 is coated with a resistance layer 3, and the layer 3 is coated with an insulating layer 4. Since the depositing layer 5 of fouling and foreign matters is generated to the surface, etc. of the substrate 1 from the layer 2 during a forming process for these layers at that time, a thick-film substrate 11 manufactured in this manner is ashed in plasma 9, and the depositing layer 5 is changed into a fragile depositing layer 10 which can be removed easily. The layer 10 is removed through ultrasonic washing using trichloroethylene, isopropyl alcohol, pure water, etc. Accordingly, the hybrid thick-film integrated circuit of high reliability is obtained.

Description

【発明の詳細な説明】 本発明は混成厚膜集積回路の製造方法、特に信:lii
’i性に優れた厚膜基板の製造方法に関するものである
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a hybrid thick film integrated circuit, and more particularly to a method for manufacturing a hybrid thick film integrated circuit.
The present invention relates to a method for manufacturing a thick film substrate with excellent i properties.

従来、厚膜基板の製造方法として、絶縁基杓上にスクリ
ーン印刷法により所望の厚膜回路を形成ずろ方法が一転
支に広く知られている。
Conventionally, as a method for manufacturing thick film substrates, a method of forming a desired thick film circuit on an insulating substrate by screen printing is widely known.

第11ソ1は従来の厚膜基板の製造方法の1例を説明す
るための断面図である。
No. 11 is a cross-sectional view for explaining an example of a conventional thick film substrate manufacturing method.

絶縁基板1にスクリーン印刷法により導体層2゜22.
32.42を形成する(第1図(a))。次にスクリー
ン印刷法により抵抗1曽3、続いて絶縁層4を形成する
(第1図(1)) ’)。
A conductive layer 2.22. is formed on the insulating substrate 1 by screen printing.
32.42 (Fig. 1(a)). Next, a resistor 1 and 3 and then an insulating layer 4 are formed by screen printing (FIG. 1(1))').

しかしながら、導体層2.22,32,42を形成した
後に抵抗層3および絶縁層4を形成するために、例えは
導体層2−Fにけ抵抗層3、さらに絶縁層4を形成する
工程中の汚れ、異物等の堆積層5が形成されてしまう(
第1図(C))。尚、第1図(C)は第1図(b)の導
体層2の近傍を拡大した断面図である。このため、ワイ
ヤホンティングにより前記導体層にIJ−1線を扱看し
た場合、リード線の導体層への接着強度が劣化するとい
う欠点があった。また、厚膜基板をハンダ浸しした場合
、前記導体層へのハンダののり性/ハ悪くなるという欠
点があった。
However, in order to form the resistive layer 3 and the insulating layer 4 after forming the conductive layers 2.22, 32, and 42, for example, during the process of forming the resistive layer 3 and further the insulating layer 4 on the conductive layer 2-F. A deposited layer 5 of dirt, foreign matter, etc. is formed (
Figure 1 (C)). Note that FIG. 1(C) is an enlarged cross-sectional view of the vicinity of the conductor layer 2 in FIG. 1(b). Therefore, when the IJ-1 wire is attached to the conductor layer by wire honting, there is a drawback that the adhesive strength of the lead wire to the conductor layer deteriorates. Furthermore, when a thick film substrate is dipped in solder, there is a drawback that the adhesion of the solder to the conductor layer becomes poor.

本発明の目的は上記の欠点を除去した混成)ツ、膜集積
回路の製造方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a hybrid film integrated circuit which eliminates the above-mentioned drawbacks.

本発明の特徴は、絶縁基板上に厚膜回路を形成する工程
と、該厚膜基板をプラズマ灰化処理する工程と、該)9
膜基板を超音波洗浄する工程を少なくとも含む混成集積
回路の製造方法にある。
The features of the present invention include a step of forming a thick film circuit on an insulating substrate, a step of plasma ashing the thick film substrate, and
A method of manufacturing a hybrid integrated circuit includes at least a step of ultrasonically cleaning a membrane substrate.

以下、本発明を実施例に糸づいて詳細に説明する。第2
図(a)乃至第2図(d)および第3図は本発明による
混成厚膜集積回路の製造工程における断面図である。従
来の厚膜基板の形成工程と同様に、充分に洗浄された絶
縁基板1上にスクリーン印刷法により導体層2.22.
32.42.  続いて抵抗層3、続いて絶縁層4を形
成する(糖2図(a))。
Hereinafter, the present invention will be explained in detail with reference to Examples. Second
Figures (a) to 2(d) and 3 are cross-sectional views showing the steps of manufacturing a hybrid thick film integrated circuit according to the present invention. Similar to the conventional process for forming thick film substrates, conductor layers 2, 22, .
32.42. Subsequently, a resistive layer 3 and then an insulating layer 4 are formed (see Figure 2 (a)).

このとき、例えば導体層2上には抵抗層3および絶縁層
4を形成する工程中の汚れ、異物等の堆積層5が形成さ
れる(第2図(b))。尚、第2図(I))は第2図(
a)の導体層2の近傍を拡大した断面図である。次に形
成された厚膜基板11を例えば酸素プラズマ9中にて灰
化処理する(第2図(C))。このとき、例えば導体層
2」二の汚れ、異物等の、9積層5は、酸素プラズマの
衝突により比較的容易に除去可能な脆い状態の汚れ、異
物等の堆積層10となる(第2図(d))。尚、第2図
(d)は酸素プラズマ灰化処理後の導体層2の近傍を拡
大した断面図でちる。次に)λ−膜基板11をfi?(
−71波ねL浄し、脆い状態の汚れ、置物等の堆積層1
0を除去する(第3図)。
At this time, for example, a deposited layer 5 of dirt, foreign matter, etc. during the process of forming the resistance layer 3 and the insulating layer 4 is formed on the conductor layer 2 (FIG. 2(b)). In addition, Fig. 2 (I)) is similar to Fig. 2 (I)).
FIG. 3 is an enlarged cross-sectional view of the vicinity of the conductor layer 2 in a). Next, the formed thick film substrate 11 is subjected to ashing treatment in, for example, oxygen plasma 9 (FIG. 2(C)). At this time, for example, the nine laminated layers 5 of dirt, foreign matter, etc. on the conductor layer 2 become a deposited layer 10 of dirt, foreign matter, etc. in a brittle state that can be relatively easily removed by collision with oxygen plasma (see Fig. 2). (d)). Note that FIG. 2(d) is an enlarged cross-sectional view of the vicinity of the conductor layer 2 after the oxygen plasma ashing treatment. Next) λ-film substrate 11 is fi? (
-71 Nami L cleaning, brittle dirt, figurines, etc. accumulation layer 1
Remove 0 (Figure 3).

洗浄液としてV↓、剥削効果の高い、例えば東京応化工
業■製OM i−?、緑囲1液+502、 トリクロー
ルエチレン、インプロビールアルコーノへ純水等を単独
あるいは糾合ぜて使用する。面、卯、3図に超音波洗浄
後の導体層2の近傍を拡大した断面図である。
As a cleaning liquid, V↓ has a high exfoliating effect, such as OM i-? manufactured by Tokyo Ohka Kogyo ■. , Green Box 1 Liquid + 502, Trichlorethylene, Improvir Alcono, Pure Water, etc. are used alone or in combination. Figures 3 and 3 are enlarged cross-sectional views of the vicinity of the conductor layer 2 after ultrasonic cleaning.

以上、実施例で説明したように、本発明の方法によれば
、厚膜基板を形成する際に導体層」二に形成される汚れ
、異物等の堆積層をプラズマ灰化処理を施すため、プラ
ズマの衝突により脆い状軽にすることができ、さらに超
音波洗浄を施すため、超音波の物理的作用と洗浄液の化
学的作用とにより汚れ、異物等の堆積層は除去されろ。
As described above in the embodiments, according to the method of the present invention, the deposited layer of dirt, foreign matter, etc. that is formed on the conductor layer when forming a thick film substrate is subjected to plasma ashing treatment. Plasma collision can make the material brittle and light, and since ultrasonic cleaning is applied, the deposited layer of dirt, foreign matter, etc. is removed by the physical action of the ultrasound and the chemical action of the cleaning solution.

このため、ワイヤボンディングにより4体層にリード線
を接着した場合、m体層表面は清浄な状態とな−)でい
るため、リード線の導体層への接着強度は第4図に示す
如く向上し、またハンダ浸しした場合、27y休層への
ハングののり性が良好となり、安定且つ信頼性に優れた
混成厚膜集積回路の製造が可能となった。すなわち第4
図で、100は本発明の実施例の製造方法による厚膜基
板の場合であり、200け従来技術の製造方法による厚
膜基板の場合である。
Therefore, when the lead wire is bonded to the 4th body layer by wire bonding, the surface of the mth body layer remains clean, so the adhesion strength of the lead wire to the conductor layer is improved as shown in Figure 4. Furthermore, when immersed in solder, the hang adhesiveness to the 27y free layer became good, making it possible to manufacture a hybrid thick film integrated circuit with excellent stability and reliability. That is, the fourth
In the figure, 100 is the case of a thick film substrate manufactured by the manufacturing method of the embodiment of the present invention, and 200 is the case of a thick film substrate manufactured by the manufacturing method of the prior art.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)乃至第1(ツ1(C)は従来の混成厚膜集
積回路の製造方法を説明するための断面図、第2図(1
)乃至第2図(d)および第3図は本発明の詳細な説明
するための混成厚膜集積回路の製造工程の断面図、第4
図は従来の製造方法と本発明の製造方法とにより形成で
れた)す、膜基板上の導体層へのワイヤボンディングに
よるリード線の接着強度を比較した概1賂図である。 尚、図において、1・・・・・・絶縁基板、2,22゜
32.42 ・・・・・・導体層、3・・・・・・抵抗
層、4・・・・・・絶縁層、5・・・・・・汚れ、異物
等の堆積層、9・・・・・・酸素プラズマ、10・・・
・・脆い状態の汚れ、異物等の堆ィ゛U層、11・・・
・・・厚1iiJ基板、100・・・・・・本発明の実
施例の製へ方法による1、j、’5.膜、S版の19゛
1合におけイ)リード線の接着強度、200・・・・・
従来の製造方法にょろり−ト線の接扁強10゛でを)る
。 〃 冥  / 図 /7′ 第 3 冴 箔 4 ス
1(a) to 1(C) are cross-sectional views for explaining the conventional method of manufacturing a hybrid thick film integrated circuit, and FIG.
) to FIG. 2(d) and FIG. 3 are cross-sectional views of the manufacturing process of a hybrid thick film integrated circuit for explaining the present invention in detail, and FIG.
The figure is a rough diagram comparing the adhesion strength of lead wires formed by wire bonding to a conductor layer on a membrane substrate formed by a conventional manufacturing method and a manufacturing method of the present invention. In the figure, 1...Insulating substrate, 2,22゜32.42...Conductor layer, 3...Resistance layer, 4...Insulating layer , 5...Deposition layer of dirt, foreign matter, etc., 9...Oxygen plasma, 10...
...Brittle dirt, foreign matter, etc. deposited U layer, 11...
... Thickness 1iiJ substrate, 100 ... 1, j, '5. according to the manufacturing method of the embodiment of the present invention. A) Adhesive strength of lead wire, 200...
In the conventional manufacturing method, the tangent strength of the wire is 10゜. 〃Mei/Figure/7' 3rd Saekaku 4th

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板上に厚膜回路を形成する工程と、該厚膜基板を
プラズマ灰化処理する工程と、該厚膜基板を超音波洗浄
する工程を少なくとも含むことを特徴とする混成集積回
路の製造方法。
A method for manufacturing a hybrid integrated circuit, comprising at least the steps of forming a thick film circuit on an insulating substrate, plasma ashing the thick film substrate, and ultrasonically cleaning the thick film substrate. .
JP16447082A 1982-09-21 1982-09-21 Manufacture of hybrid integrated circuit Pending JPS5954233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16447082A JPS5954233A (en) 1982-09-21 1982-09-21 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16447082A JPS5954233A (en) 1982-09-21 1982-09-21 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS5954233A true JPS5954233A (en) 1984-03-29

Family

ID=15793784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16447082A Pending JPS5954233A (en) 1982-09-21 1982-09-21 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5954233A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63313894A (en) * 1987-06-17 1988-12-21 Nippon Mektron Ltd Method of working external shape of wiring substrate by using laser
US7066456B2 (en) 2002-08-30 2006-06-27 Honda Giken Kogyo Kabushiki Kaisha Hydraulic shock absorber mounting structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63313894A (en) * 1987-06-17 1988-12-21 Nippon Mektron Ltd Method of working external shape of wiring substrate by using laser
US7066456B2 (en) 2002-08-30 2006-06-27 Honda Giken Kogyo Kabushiki Kaisha Hydraulic shock absorber mounting structure

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