JPS5953712B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS5953712B2
JPS5953712B2 JP55050864A JP5086480A JPS5953712B2 JP S5953712 B2 JPS5953712 B2 JP S5953712B2 JP 55050864 A JP55050864 A JP 55050864A JP 5086480 A JP5086480 A JP 5086480A JP S5953712 B2 JPS5953712 B2 JP S5953712B2
Authority
JP
Japan
Prior art keywords
silicon
thin film
compound
oxide
tantalum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55050864A
Other languages
Japanese (ja)
Other versions
JPS56147471A (en
Inventor
恵彦 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP55050864A priority Critical patent/JPS5953712B2/en
Publication of JPS56147471A publication Critical patent/JPS56147471A/en
Publication of JPS5953712B2 publication Critical patent/JPS5953712B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

Description

【発明の詳細な説明】 本発明は半導体装置に係り、特に大規模集積回路の実現
に適している金属酸化物半導体に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a metal oxide semiconductor suitable for realizing a large-scale integrated circuit.

例えば本発明は、ゲルマニウム、ガリウム・ヒソ化合物
等の半導体基体を用いて該基体上にタンタル、ハフニウ
ム、ジルコニウム等の陽極化成可能な難溶性金属と、シ
リコン、ゲルマニウム・ヒソ等の半導体との混合物ある
いは化合物から形成された誘導体薄膜を被着形成させ、
更に該誘電体上に多結晶シリコン等を具備させることを
特徴とするものである。
For example, the present invention uses a semiconductor substrate such as germanium, gallium-hysterol compound, etc., and a mixture or Depositing and forming a dielectric thin film formed from a compound,
Furthermore, it is characterized in that polycrystalline silicon or the like is provided on the dielectric.

以下図面を参照して説明する。This will be explained below with reference to the drawings.

第1図は、1−トランジスタセルのd−RAM(ダイナ
ミック ランダム アクセスメモリ)の回路を示すもの
であり、MOS電界効果トランジスタ(T部)とコンデ
ンサ(C部)及びワード線11、、ビット線12、グラ
ンド又は電源線13とからなり、第2図に示す構造によ
り製造されるものである。
Figure 1 shows the circuit of a 1-transistor cell d-RAM (dynamic random access memory), which includes a MOS field effect transistor (T section), a capacitor (C section), a word line 11, a bit line 12 , a ground or power supply line 13, and is manufactured with the structure shown in FIG.

即ち、二酸化シリコン22を約1μmの厚さで所望の形
状に形成させたP型シリコン基体21を約1000℃の
温度で処理し、約700Λの二酸化シリコン薄膜23を
形成させ、更に電極として機能する多結晶シリコン薄膜
24をシランガスの分解で約5000入の厚さに積層形
成させる。
That is, a P-type silicon substrate 21 on which silicon dioxide 22 is formed into a desired shape with a thickness of about 1 μm is treated at a temperature of about 1000° C. to form a silicon dioxide thin film 23 with a thickness of about 700 Λ, which further functions as an electrode. A polycrystalline silicon thin film 24 is laminated to a thickness of approximately 5,000 layers by decomposing silane gas.

該多結晶シリコン薄膜を所望の形状24及び24′に形
成させた後、約80KV程度に加速したヒ素イオンを照
射し、シリコン基体21の所望部25及び25′をn型
に変換し、ドレイン及びソース部を形成する。しかる後
基体21を高温で熱処理し、二酸化シリコン薄膜26を
基体及び多結晶シリコン上に形成させ、その後、ドレイ
ン及びソース部25及び25′上の二酸化シリコン薄膜
23及び26をJ所望の形状に除去し、その際、ゲート
電極及びドレイン電極として機能する多結晶シリコン薄
膜24及び24′上の二酸化シリコン薄膜26をも同時
に所望の形状に除去する。しかる後アルミニウム薄膜2
7、27’等を所望の形状に形成させ、門第1図に示す
回路を提供するものである。しかしながら、1−トラン
ジスタセルは増幅機能を具備しておらず、従つて第1図
のCで示されるコンデンサは単なる浮遊容量というわけ
にはいかず、相当の面積を要して形成されるものである
。即ち、S/N比はセルの容量Cとビツト線の浮遊容量
CBとの比C/CBで定まり、C部の面積をトランジス
タTの占める面積と同程度にしてもC/CBは1/10
程度になるのがせいぜいであり、かかるS/N比等のた
めにセルの小型化には限度があり、更に大規模集積回路
を小型化する際の障害なつていたものである。また、第
2図において、薄膜23″は、比誘電率が約4の二酸化
シリコンが用いられるが、タンタル、チタン等の難溶性
金属の酸化物は通常二酸化シリコンの数倍の比誘電率を
有し、従つて、薄膜23″として前記難溶性金属酸化物
を用いれば第1図に示すC部の面積を数分の1程度に小
型化できるものである。
After forming the polycrystalline silicon thin film into the desired shapes 24 and 24', it is irradiated with arsenic ions accelerated to about 80 KV to convert the desired portions 25 and 25' of the silicon substrate 21 into n-type, and convert the desired regions 25 and 25' of the silicon substrate 21 into n-type, Form a source part. Thereafter, the substrate 21 is heat-treated at a high temperature to form a silicon dioxide thin film 26 on the substrate and polycrystalline silicon, and then the silicon dioxide thin films 23 and 26 on the drain and source parts 25 and 25' are removed into a desired shape. At this time, the silicon dioxide thin film 26 on the polycrystalline silicon thin films 24 and 24', which function as gate electrodes and drain electrodes, is also removed at the same time into a desired shape. After that, aluminum thin film 2
7, 27', etc. are formed into a desired shape to provide the circuit shown in FIG. However, the 1-transistor cell does not have an amplification function, so the capacitor shown by C in Figure 1 cannot be simply a stray capacitance, and requires a considerable area to form. . In other words, the S/N ratio is determined by the ratio C/CB between the cell capacitance C and the stray capacitance CB of the bit line, and even if the area of the C part is made to be the same as the area occupied by the transistor T, C/CB is 1/10.
At best, the S/N ratio and other factors limit the miniaturization of cells, and this has been an obstacle to further miniaturizing large-scale integrated circuits. Furthermore, in FIG. 2, the thin film 23'' is made of silicon dioxide with a dielectric constant of approximately 4, but oxides of refractory metals such as tantalum and titanium usually have a dielectric constant several times that of silicon dioxide. Therefore, if the above-mentioned hardly soluble metal oxide is used as the thin film 23'', the area of the portion C shown in FIG. 1 can be reduced to a fraction of the size.

しかしながら、難溶性金属酸化物薄膜を所望の形状に形
成させるための腐触液は、通常基体のシリコン21及び
二酸化シリコン薄膜22をも容易に腐触するものであり
、従つて、該金属酸化物を基体等に損傷を与えることな
く所望の形状に再現性よく形成させることが困難であり
、それ故、製造されるMOS電界効果トランジスタの歩
留りも当然低くなるものであつた。従つて、本発明の目
的は、二酸化シリコン薄膜23及び23″に代つて大規
模集積回路の製造に適し、再現性よく金属酸化物体を提
供できるように特に比誘電率の大なる誘電体膜を有する
半導体装置を提供することにある。以下に、本発明の実
施例を第3図を用いて説明する。
However, the corrosive liquid used to form the poorly soluble metal oxide thin film into a desired shape usually corrodes the silicon 21 and the silicon dioxide thin film 22 that are the substrates. It is difficult to form the MOS field effect transistor into a desired shape with good reproducibility without damaging the substrate, and as a result, the yield of manufactured MOS field effect transistors is naturally low. Therefore, it is an object of the present invention to develop a dielectric film having a particularly large dielectric constant in place of the silicon dioxide thin films 23 and 23'', which is suitable for manufacturing large-scale integrated circuits and can provide a metal oxide object with good reproducibility. An object of the present invention is to provide a semiconductor device having the following features.Examples of the present invention will be described below with reference to FIG.

第3図は、比誘電率が約24の五酸化タンタル誘電体を
提供することができるタンタル中にシリコンを含有せし
めて形成した化合物あるいは混合物のシリコン原子組成
負分率と、該化合物あるいは混合物から形成された酸化
物(以下化合物酸化物と記述する)の比誘電率εとの関
係を、五酸化タンタルの比誘電率ε。
Figure 3 shows the negative fraction of silicon atoms of a compound or mixture formed by incorporating silicon in tantalum that can provide a tantalum pentoxide dielectric with a dielectric constant of about 24, and the negative fraction of the silicon atomic composition from the compound or mixture. The relationship between the relative permittivity ε of the formed oxide (hereinafter referred to as compound oxide) is expressed as the relative permittivity ε of tantalum pentoxide.

との関係で示したものである。図から明らかなように、
該化合物酸化物は、シリコンの原子組成百分率が60%
以上の化合物から形成されたものであつても、二酸化シ
リコンの比誘電率よりも2倍程度以上も大きな値を示し
、従つて、第1図に示すC部、又は第2図に示す23″
の面積の小型化に適しており、大規模集積回路の実現を
可能ならしめるものである。前記化合物は、シリコン原
子組成百分率が15%程度以上で非晶質となり、従つて
形成される薄膜の性質はシリコンの含有率増大に伴なつ
て多結晶シリコン薄膜の性質に類似していくものである
。それ故、前記化合物あるいは混合物薄膜は比較的容易
に所望の形状とすることができ、該薄膜の陽極化成によ
る酸化物は従つて二酸化シリコンの場合と同様比較的容
易に所望の形状に付需形成することができ、それ故製造
されるMOS電界効果トランジスタは、前記化合物ある
いは混合物の腐触液あるいは該化合物酸化物の腐触液に
よつても損傷を受けることが少なく、高歩留りで製造で
きるものである。尚実験の結果、前記酸化物を構成させ
る化合物のシリコン原子組成百分率は実用上10%以上
で好ましい結果の得られることが判明した。前記化合物
酸化物を基体上に約700人程度の厚みに付着形成させ
る方法は種々あり、例えば以下に示す方法がある。
This is shown in relation to As is clear from the figure,
The compound oxide has an atomic composition percentage of silicon of 60%.
Even if it is formed from the above-mentioned compounds, it exhibits a value that is about twice as large as the dielectric constant of silicon dioxide, and therefore, it has a relative dielectric constant that is about twice as large as the dielectric constant of silicon dioxide.
It is suitable for miniaturizing the area of the circuit and makes it possible to realize large-scale integrated circuits. The compound becomes amorphous when the silicon atomic composition percentage is about 15% or more, and the properties of the thin film formed become similar to those of a polycrystalline silicon thin film as the silicon content increases. be. Therefore, the compound or mixture thin film can be formed into a desired shape relatively easily, and the oxide formed by anodizing the thin film can be formed into the desired shape relatively easily, as in the case of silicon dioxide. Therefore, the manufactured MOS field effect transistor is less likely to be damaged by the corrosive liquid of the compound or mixture or the corrosive liquid of the compound oxide, and can be manufactured at a high yield. It is. As a result of experiments, it has been found that preferable results can be obtained practically when the silicon atom composition percentage of the compound constituting the oxide is 10% or more. There are various methods for depositing the compound oxide on the substrate to a thickness of about 700 mm, for example, the following method.

即ち、タンタル・シリコン化合物をスパツタリング法、
蒸着法等により一端基体上に形成させた後、陽極化成法
、熱酸化法等により該化合物を酸化物に変換させる方法
、あるいはタンタルをシランガスとアルゴンガス中で活
性スパツタリングし、前記化合物を基体上に形成させ、
酸化物に変換させる方法、あるいはタンタル・シリコン
化合物をアルゴンと酸素の混合ガス中にて活性スパツタ
リングし、基体上に直接酸化物を付着形成させる方法、
あるいはタンタル・シリコン化合物酸化物ターゲツトを
用いて、高周波スパツタリング法により直接基体上に酸
化物を付着させる方法等があるが、本発明は前述した効
果を有する以上、該化合物酸化物の付着方法は特に限定
されるべきものではなく、また膜厚等も特に規定される
べきものではないことは当然である。又、タンタル、チ
タン、ハフニウム、ジルコニウム等の難溶性金属は類似
した物理的性質を示すことより、前記化合物酸化物のタ
ンタル原子に代つてこれら難溶性金属原子を用いてもよ
く、また該金属を複数種類組み合わせた化合物酸化物を
用いて本発明を実施しても、本発明による効果は何ら損
なわれるものではなく、又、半導体成分としてはシリコ
ンに限らず、ゲルマニウム、ガリウム・ヒソ等を用いて
もよいことは当然である。更にまた、窒素あるいは炭素
等を含む難溶性金属から形成された誘電体は良質の誘電
体を提供することから、前記化合物あるいは混合物を窒
素あるいはメタン等とアルゴン等の混合ガス中にて活性
スパツタリングして窒化物あるいは炭化物等を形成し、
更に該窒化物あるいは炭化物に変換して本発明を実施し
てもよいことは勿論である。また、本実施例においては
、第1図及び第2図に示す所謂単層多結晶シリコン技術
を引用して説明したが、例えば、第2図に示す多結晶シ
リコン24及び24″を多層に形成させた所謂多層多結
晶シリコン技術に対しても本発明は当然適用できるもの
であり、その製造方法、構造等は特に限定されるもので
はないことは論を待たない。
That is, a tantalum silicon compound is sputtered,
The compound is first formed on a substrate by a vapor deposition method or the like, and then the compound is converted into an oxide by an anodization method, a thermal oxidation method, etc., or tantalum is activated sputtered in silane gas and argon gas to form the compound on the substrate. formed into
A method of converting it into an oxide, or a method of actively sputtering a tantalum-silicon compound in a mixed gas of argon and oxygen to form an oxide directly on the substrate.
Alternatively, there is a method of directly depositing the oxide onto the substrate by high frequency sputtering using a tantalum/silicon compound oxide target, but since the present invention has the above-mentioned effects, the method of depositing the compound oxide is particularly suitable. It goes without saying that the film thickness and the like are not particularly limited. In addition, since sparingly soluble metals such as tantalum, titanium, hafnium, and zirconium exhibit similar physical properties, these sparingly soluble metal atoms may be used in place of the tantalum atom in the compound oxide. Even if the present invention is carried out using a combination of multiple types of compound oxides, the effects of the present invention will not be impaired in any way, and the semiconductor component is not limited to silicon, but germanium, gallium, histo, etc. may be used. Of course it's a good thing. Furthermore, since a dielectric material formed from a poorly soluble metal containing nitrogen or carbon provides a high quality dielectric material, the above compound or mixture may be activated sputtered in a mixed gas of nitrogen or methane, etc., and argon, etc. to form nitrides or carbides,
Of course, the present invention may also be carried out by converting it into the nitride or carbide. Furthermore, although this embodiment has been described with reference to the so-called single-layer polycrystalline silicon technology shown in FIGS. 1 and 2, for example, polycrystalline silicon 24 and 24'' shown in FIG. The present invention is naturally applicable to the so-called multilayer polycrystalline silicon technology, and it goes without saying that the manufacturing method, structure, etc. thereof are not particularly limited.

また、本発明においては、容量として寄与するC部の誘
電体23″とMOSトランジスタのゲート酸化膜23と
を同一材料で形成したが、本発明による酸化物を23″
で示す誘電体に対してのみ適用し、ゲート酸化膜を二酸
化シリコンで形成することも当然可能であり、更にはま
た、酸化物23″を比誘電率が二酸化シリコンよりも大
きい窒化シリコン、アルミナ等の絶縁膜と本発明による
誘電体とを積層させた薄膜として用いることも可能であ
り、金属酸化物半導体の構造及び用途等も特に限定され
るべきものではない。
Further, in the present invention, the dielectric 23'' of the C portion contributing to capacitance and the gate oxide film 23 of the MOS transistor are formed of the same material, but the oxide according to the present invention is
It is of course possible to apply this method only to the dielectric material shown in , and to form the gate oxide film with silicon dioxide.Furthermore, the oxide 23'' can be replaced with silicon nitride, alumina, etc., which has a relative dielectric constant higher than that of silicon dioxide. It is also possible to use the metal oxide semiconductor as a thin film in which an insulating film and a dielectric according to the present invention are laminated, and the structure and use of the metal oxide semiconductor are not particularly limited.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はダイナミツク・ランダム・アクセス・メモリの
回路を示す図、第2図は容量成分を具備する金属酸化物
半導体の断面を示す図、第3図は本発明の実施例による
タンタル・シリコン化合物酸化物の比誘電率εをタンタ
ル・シリコン化合物のシリコン原子組成百分率との関係
で示した特性図で゛ある。 尚図において、11・・・・・・ワード線、12・・・
・・・ビツト線、13・・・・・・グランド又は電源線
、21・・・・・・P型シリコン基体、23,23″,
26・・・・・・二酸化シリコン薄膜、24・・・・
・・多結晶シリコン薄膜、25・・・・・・ドレイン部
、25″・・・・・・ソース部。
FIG. 1 is a diagram showing a circuit of a dynamic random access memory, FIG. 2 is a diagram showing a cross section of a metal oxide semiconductor having a capacitive component, and FIG. 3 is a diagram showing a tantalum silicon compound according to an embodiment of the present invention. This is a characteristic diagram showing the relationship between the dielectric constant ε of an oxide and the silicon atomic composition percentage of a tantalum-silicon compound. In the figure, 11... word line, 12...
... Bit line, 13 ... Ground or power supply line, 21 ... P-type silicon substrate, 23, 23'',
26...Silicon dioxide thin film, 24...
...Polycrystalline silicon thin film, 25...Drain part, 25''...Source part.

Claims (1)

【特許請求の範囲】 1 シリコン、ゲルマニウム、ガリウム・ヒソ等の半導
体基体上に酸化物薄膜を被着させて形成させる所謂金属
酸化物の半導体装置において、コンデンサ容量成分を提
供する部分の絶縁膜が、タンタル、チタン、ハフニウム
、ジルコニウム等の難溶性金属と、シリコン、ゲルマニ
ウム、ヒソ等の半導体とを含む誘電体から構成されてい
ることを特徴とする半導体装置。 2 シリコン、ゲルマニウム、ガリウム・ヒソ等の半導
体基体上に酸化物薄膜を被着させて形成させる所謂金属
酸化物の半導体装置において、コンデンサ容量成分を提
供する部分の絶縁膜が、タンタル、チタン、ハフニウム
、ジルコニウム等の難溶性金属と、シリコン、ゲルマニ
ウム、ヒソ等の半導体とを含む誘電体と、二酸化シリコ
ンよりも比誘率の大なる窒化シリコン、アルミナ等の絶
縁膜とを多層にして形成していることを特徴とする半導
体装置。
[Scope of Claims] 1. In a so-called metal oxide semiconductor device formed by depositing an oxide thin film on a semiconductor substrate such as silicon, germanium, gallium/hysterol, etc., an insulating film in a portion providing a capacitor capacitance component is , tantalum, titanium, hafnium, zirconium, etc., and a dielectric material containing a semiconductor such as silicon, germanium, histho, etc. 2. In a so-called metal oxide semiconductor device formed by depositing an oxide thin film on a semiconductor substrate such as silicon, germanium, gallium/hiso, etc., the insulating film in the portion that provides the capacitor capacitance component is made of tantalum, titanium, hafnium, etc. , a dielectric material containing a hardly soluble metal such as zirconium, a semiconductor such as silicon, germanium, or histo, and an insulating film such as silicon nitride or alumina, which has a higher dielectric constant than silicon dioxide, are formed in multiple layers. A semiconductor device characterized by:
JP55050864A 1980-04-17 1980-04-17 semiconductor equipment Expired JPS5953712B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55050864A JPS5953712B2 (en) 1980-04-17 1980-04-17 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55050864A JPS5953712B2 (en) 1980-04-17 1980-04-17 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS56147471A JPS56147471A (en) 1981-11-16
JPS5953712B2 true JPS5953712B2 (en) 1984-12-26

Family

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Family Applications (1)

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JP55050864A Expired JPS5953712B2 (en) 1980-04-17 1980-04-17 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5953712B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5978553A (en) * 1982-10-27 1984-05-07 Hitachi Ltd Capacitor and manufacture thereof
JPS61232660A (en) * 1985-04-09 1986-10-16 Nec Corp Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54133089A (en) * 1978-04-06 1979-10-16 Nec Corp Thin film capacitor and its manufacture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54133089A (en) * 1978-04-06 1979-10-16 Nec Corp Thin film capacitor and its manufacture

Also Published As

Publication number Publication date
JPS56147471A (en) 1981-11-16

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